Abstract: Methods, systems, and apparatus for operating a system of qubits. In one aspect, a method includes operating a first qubit from a first plurality of qubits at a first qubit frequency from a first qubit frequency region, and operating a second qubit from the first plurality of qubits at a second qubit frequency from a second first qubit frequency region, the second qubit frequency and the second first qubit frequency region being different to the first qubit frequency and the first qubit frequency region, respectively, wherein the second qubit is diagonal to the first qubit in a two-dimensional grid of qubits.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

Abstract: Methods, systems, and apparatus for operating a system of qubits. In one aspect, a method includes operating a first qubit from a first plurality of qubits at a first qubit frequency from a first qubit frequency region, and operating a second qubit from the first plurality of qubits at a second qubit frequency from a second first qubit frequency region, the second qubit frequency and the second first qubit frequency region being different to the first qubit frequency and the first qubit frequency region, respectively, wherein the second qubit is diagonal to the first qubit in a two-dimensional grid of qubits.

Abstract: A method of fabricating a polymer wire according to the present embodiment includes preparing an electrode platform having a micro gap, forming a plurality of single polymer wires on the electrode platform, and a heat treatment operation of aggregating the plurality of single polymer wires to form an aggregated polymer wire.

Abstract: Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

Abstract: A method of depositing nanowire chains includes applying a nanowire mixture to a chain-site. The chain-site includes a patterned conductive film covering at least a portion of a surface of a substrate. The patterned conductive film includes a gap. The method also includes, after applying the nanowire mixture, forming a nanowire chain suspended adjacent to a portion of the patterned conductive film by generating an electric field proximate to the patterned conductive film; and depositing the nanowire chain across the gap by removing a liquid portion of the nanowire mixture. An average length of the nanowires of the nanowire mixture is less than a width of the gap.

Abstract: Systems and methods of fabricating and functionality patterned nanowire probes that are stable under fluid reservoir conditions and have imageable contrast are provided. Optical imaging and deconstruction methods and systems are also provided that are capable of determining the distribution of nanowires of a particular pattern to determine the mixing between or leakage from fluid reservoirs.

Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

Abstract: A system for quantum computation and a readout method using the same are provided. In some aspects, the system includes at least one qubit circuit coupled to a resonant cavity, wherein each of the at least one qubit circuit is described by multiple quantum states, and a controller configured to provide microwave irradiation to the resonant cavity such that a quantum state information of the at least one qubit circuit is transferred to a resonant cavity occupation. The system also includes a readout circuit, coupled to the resonant cavity, configured to receive signals corresponding to the resonant cavity occupation, and generate an output indicative of the quantum states of the at least one qubit circuit. Optionally, the system further includes at least one single flux quantum (“SFQ”) circuit coupled to the readout circuit and configured to receive the output therefrom.

Abstract: A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors.

Abstract: An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer.

Abstract: A wavelength-tunable, depletion-type infrared metamaterial optical device is provided. The device includes a thin, highly doped epilayer whose electrical permittivity can become negative at some infrared wavelengths. This highly-doped buried layer optically couples with a metamaterial layer. Changes in the transmission spectrum of the device can be induced via the electrical control of this optical coupling. An embodiment includes a contact layer of semiconductor material that is sufficiently doped for operation as a contact layer and that is effectively transparent to an operating range of infrared wavelengths, a thin, highly doped buried layer of epitaxially grown semiconductor material that overlies the contact layer, and a metallized layer overlying the buried layer and patterned as a resonant metamaterial.

Abstract: An organic light-emitting display device and a method of its manufacture are provided, whereby manufacturing processes are simplified and display quality may be enhanced. The display device includes: an active layer of a thin film transistor (TFT), on a substrate and including a semiconducting material; a lower electrode of a capacitor, on the substrate, doped with ion impurities, and including a semiconducting material; a first insulating layer on the substrate to cover the active layer and the lower electrode; a gate electrode of the TFT, on the first insulating layer; a pixel electrode on the first insulating layer; an upper electrode of the capacitor, on the first insulating layer; source and drain electrodes of the TFT, electrically connected to the active layer; an organic layer on the pixel electrode and including an organic emission layer; and a counter electrode facing the pixel electrode, the organic layer between the counter electrode and the pixel electrode.

Abstract: Provided is an LED device which is capable of reducing the emission size without changing the size of an LED and is capable of switching the emission size arbitrarily. The LED device includes, on a substrate, a carrier control layer, a lower current confinement layer, an active layer, and an upper current confinement layer. A p-type electrode is provided on the upper current confinement layer. Two n-type electrodes are arranged on the carrier control layer so as to dispose the p-type electrode between the two n-type electrodes in an in-plane direction of the substrate.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: A semiconductor light emitting device includes: n-type and p-type semiconductor layers; and an active layer disposed between the n-type and p-type semiconductor layers. The active layer has a structure in which a plurality of quantum well layers and a plurality of quantum barrier layers are alternately disposed, wherein the plurality of quantum well layers are made of AlxInyGa1-x-yN (0?x<1, 0<y?1) and each of the plurality of quantum well layers contains a different indium (In) content. And, among the plurality of quantum barrier layers, a quantum barrier layer adjacent to a quantum well layer having a higher indium (In) content is thicker than a quantum barrier layer adjacent to a quantum well layer having a lower indium (In) content.

Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).

Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.

Abstract: A semiconductor light emitting element includes a substrate 11 having a defect concentrated region 11a which has a crystal defect density higher than in the other region. On the substrate 11, a semiconductor layer 12 is formed. On the defect concentrated region 11a, a first electrode 13 is formed. On the semiconductor layer 12, a second electrode 14 is formed.

Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

Abstract: The fabrication method comprises a step of exposing at least one organic diode to a gas, before packaging of the device, to form a plurality of randomly distributed black spots by impairment. Increasing the exposure time enables the size of the black spots to be increased, also randomly. The surface distribution of the black spots, visible by electroluminescence, enables an object associated with this distribution to be identified in reliable manner.

Abstract: A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.

Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold. Insulating substrates can be employed, which facilitates inclusion of these devices in photonic integrated circuits.

Abstract: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members.

Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.

Abstract: An apparatus and method for making it. Some embodiments include a light-emitting device having a light-emitting active region; a tunneling-barrier (TB) structure facing adjacent the active region; a TB grown-epitaxial-metal-mirror (TB-GEMM) structure facing adjacent the TB structure, wherein the TB-GEMM structure includes at least one metal is substantially lattice matched to the active region; and a conductivity-type III-nitride crystal structure adjacent facing the active region opposite the TB structure. In some embodiments, the active region includes an MQW structure. In some embodiments, the TB-GEMM includes an alloy composition such that metal current injectors have a Fermi energy potential substantially equal to the sub-band minimum energy potential of the MQW. Some embodiments further include a second mirror (optionally a GEMM) to form an optical cavity between the second mirror and the TB-GEMM structure.

Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Abstract: A silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions. An insulating layer lies above the substrate, and on top of the insulating layer is a lower layer of one or more aluminium gates. The surface of each of the lower gates is oxidised to insulate them from an upper aluminium gate that extends over the lower gates.

Abstract: A fine vacuum tube element and other electronic elements are integrated and formed on a semiconductor substrate, and the fine vacuum tube element and the other electronic elements transmit signals to and from each other. When integrating the vacuum tube element with the other electronic elements, a quantum effect is realized in a room temperature environment by utilizing ballistic electrons (non-scattering electrons) traveling through the vacuum, and in the integrated circuit, an A/D converter is constructed by an interference system such as a Mach-Zehnder interferometer. Also an integrated circuit of an advanced function-integrated type is provided, comprising an interference system such as a Mach-Zehnder interferometer wherein weighting of the Mach-Zehnder interferometer is constituted for image processing and signal code conversion.

Abstract: The object of the present invention is to provide a method of manufacturing a semiconductor element which can produce a semiconductor element provided with a semiconductor layer having a high carrier transport ability, a semiconductor element manufactured by the semiconductor element manufacturing method, an electronic device provided with the semiconductor element, and electronic equipment having a high reliability.

Abstract: A n-type layer, a multiquantum well active layer comprising a plurality of pairs of an InGaN well layer/InGaN barrier layer, and a p-type layer are laminated on a substrate to provide a nitride semiconductor light emitting element. A composition of the InGaN barrier included in the multiquantum well active layer is expressed by InxGa1-xN (0.04?x?0.1), and a total thickness of InGaN layers comprising an In composition ratio within a range of 0.04 to 0.1 in the light emitting element including the InGaN barrier layers is not greater than 60 nm.

Abstract: A light emitting heterostructure and/or device in which the light generating structure is contained within a potential well is provided. The potential well is configured to contain electrons, holes, and/or electron and hole pairs within the light generating structure. A phonon engineering approach can be used in which a band structure of the potential well and/or light generating structure is designed to facilitate the emission of polar optical phonons by electrons entering the light generating structure. To this extent, a difference between an energy at a top of the potential well and an energy of a quantum well in the light generating structure can be resonant with an energy of a polar optical phonon in the light generating structure material. The energy of the quantum well can comprise an energy at the top of the quantum well, an electron ground state energy, and/or the like.

Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).

Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.

Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.

Abstract: A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor saturable absorber and the fabrication method thereof are provided. The semiconductor saturable absorber includes a Fe-doped InP substrate, a periodic unit comprising an AlGaInAs QW formed on the Fe-doped InP substrate and an InAlAs barrier layer formed on one side of the AlGaInAs QW, and another InAlAs barrier layer formed on the other side of the AlGaInAs QW. Each of the InAlAs barrier layers has a width being a half-wavelength of a light emitted by the AlGaInAs QW.

Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

Abstract: An integrated circuit is provided with a photonic device and a spot-size converter waveguide device integrated on a common substrate. The spot-size converter waveguide device provides for transformation between a larger spot-size and a smaller spot-size corresponding to the photonic device. The spot-size converter waveguide device includes at least one of a bottom mirror and top mirror, which provide highly-reflective lower and upper cladding, respectively, for vertical confinement of light propagating through the waveguide device. The top mirror overlies opposing sidewalls of the spot-converter waveguide device, which provide highly-reflective sidewall cladding for lateral confinement of light propagating through the waveguide device. Advantageously, the highly-reflective lower cladding provided by the bottom mirror limits optical loss of the waveguide device. Similarly, the highly-reflective upper cladding and sidewall cladding provided by the top mirror limits optical loss of the waveguide device.

Abstract: A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may be InGaN; InAlGaN; or quaternary InxAlyGa1-x-yN and x is greater than or equal to y/2. The polarization generating layers create polarization fields along a common, predetermined direction constructively increasing the total polarization fields experienced by the channel layer to increase confinement of carriers in the conductive channel.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A photodetecting device which is capable of performing photodetection with a high sensitivity in a wide temperature range. A quantum dot structure including an embedding layer and quantum dots embedded by the embedding layer is formed. A quantum well structure including embedding layers and a quantum well layer whose band gap is smaller than those of the embedding layers is formed at a location downstream of the quantum dot structure in the direction of flow of electrons which flow perpendicularly to the quantum dot structure during operation of the photodetecting device. This reduces the temperature dependence of the potential barrier of a photodetecting section, which has to be overcome by electrons, whereby it is possible to lower the potential barrier of the embedding layers at high temperature.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.

Abstract: To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate of a silicon nitride layer is obtainable, and a polishing method employing such a composition. A polishing composition which has silicon oxide abrasive grains, an acidic additive and water, wherein the acidic additive is such that when it is formed into a 85 wt % aqueous solution, the chemical etching rate of the silicon nitride layer is at most 0.1 nm/hr in an atmosphere of 80° C. Particularly preferred is one wherein the silicon oxide abrasive grains have an average particle size of from 1 to 50 nm, and the pH of the composition is from 3.5 to 6.5.

Abstract: Channelizing an applied current and applying a voltage to the channelized current enables switching of the applied current. According to the present invention, an applied current enters through a signal input carrier (12) and is channelized by a plurality of lateral potential wells created by a plurality of polysilicon fingers gates (14). A first voltage is applied to a first set of the plurality of polysilicon finger gates (32) and a second differential voltage is applied to a second set of the plurality of polysilicon finger gates (34), which results in a differential current flow among the lateral potential wells beneath the first and second sets of polysilicon fingers (32, 34), respectively. The differential current then flows to first and second signal output carriers (40, 42).