Current Flow Across Well Patents (Class 257/23)
  • Patent number: 7155684
    Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keiichi Kusumoto
  • Patent number: 7132677
    Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 7, 2006
    Assignee: Dongguk University
    Inventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung
  • Patent number: 7098471
    Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 29, 2006
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7077982
    Abstract: A molecular electric wire that is formed of an environmentally benign ecological material and enables a microscopic wiring, a molecular electric wire circuit using the molecular electric wire, and the like are provided. The molecular electric wire comprises a rod-shaped organic molecule and an electroconductive material, the electroconductive material being carried by the rod-shaped organic molecule, and the molecular electric wire circuit is formed by using the molecular electric wire.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: July 18, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Takatoshi Kinoshita, Shintaro Washizu
  • Patent number: 7038233
    Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi, Ltd., Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Tsukuru Ohtoshi
  • Patent number: 6998306
    Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sik Kim, Ji-Hye Yi
  • Patent number: 6897468
    Abstract: Methods for coupling a superconducting qubit to a resonant control circuit. An interaction term between the qubit and the circuit initially has a diagonal component. A recoupling operation is applied to the qubit. The circuit is tuned so that a frequency of the qubit and circuit match. A second recoupling operation transforms the term to have only off-diagonal components. A method for entangling a state of two qubits coupled to a bus with a control circuit. An interaction term between at least one of the qubits and the circuit has a diagonal component. A recoupling operation is applied to at least one of the qubits such that the term has only off-diagonal components. The frequency of the circuit is tuned to the frequency of the first qubit, and then tuned to the frequency of the second qubit. The recoupling operation is reapplied to at least one of the qubits.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: May 24, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton, Alexandre M. Zagoskin
  • Patent number: 6891189
    Abstract: A nitride semiconductor laser device includes a nitride semiconductor substrate, and a layered portion corresponding to a nitride semiconductor film grown on the nitride semiconductor substrate, the layered portion including an n-type layer and a p-type layer and a light emitting layer posed between the n- and p-type layers, of the n- and p-type layers a layer opposite to the nitride semiconductor substrate with the light emitting layer opposed therebetween serving as an upper layer having a stripe of 1.9 ?m to 3.0 ?n in width, the light emitting layer and the upper layer having an interface distant from a bottom of the stripe by 0 ?m to 0.2 ?m.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: May 10, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigetoshi Ito, Yuhzoh Tsuda
  • Patent number: 6885023
    Abstract: An optical device such as a radiation detector or an optically activated memory includes a barrier region located between two active regions. One or more quantum dots are provided such that a change in the charging state of the quantum dot or dots affects the flow of current through the barrier region. The charging states of the quantum dot is changed by an optical device.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: April 26, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Andrew James Shields, Nalin Kumar Patel
  • Patent number: 6870178
    Abstract: A quantum dot (QD) laser having greatly reduced temperature sensitivity employs resonant tunnel-injection of carriers into the QDs from a pair of quantum wells (QWs). The carriers are injected through barrier layers. Because the tunnel-injection process is essentially temperature-independent, and because the tunnel-injection of carriers is the dominant source of current through the device, temperature-dependent currents are virtually eliminated, resulting in a device having a temperature-independent threshold current. In an additional device, carriers are injected into QDs from a pair of optical confinement layers (OCLs), either by tunnelling or thermionic emission. Each barrier layer is designed to have a low barrier height for carriers entering the QDs, and a high barrier height for carriers exiting the QDs. As a result, parasitic current from carriers leaving the QDs is greatly reduced, which enables the device to have low temperature sensitivity even without using resonant tunnel-injection and/or QWs.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 22, 2005
    Inventors: Levon V. Asryan, Serge Luryi
  • Patent number: 6855959
    Abstract: A nitride based semiconductor photo-luminescent device has an active layer having a quantum well structure. The active layer has both a high dislocation density region and a low dislocation density region that is lower in dislocation density than the high dislocation density region, wherein the low dislocation density region includes a current injection region into which a current is injected, and the active layer is less than 1×1018 cm?3 in impurity concentration.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 15, 2005
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Patent number: 6853018
    Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: February 8, 2005
    Assignee: Sony Corporation
    Inventor: Takayuki Toyama
  • Publication number: 20040238812
    Abstract: The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (110) located over a substrate (115) and a quantum island (120) situated between the source and drain (105, 110), to form tunnel junctions (125, 130) between the source and drain (105, 110). The device (100) further includes a movable electrode (135) located adjacent the quantum island (120) and a displaceable dielectric (140) located between the moveable electrode (135) and the quantum island (120). The present invention also includes a method of fabricating a single-electron device (200), and a transistor circuit (300) that include a single-electron device (310).
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicant: Texas Instruments, Incorporated
    Inventor: Christoph Wasshuber
  • Patent number: 6812483
    Abstract: Disclosed is an optical semiconductor device which has a quantum well structure comprising a quantum well made of a zinc oxide or a zinc oxide mixed crystal thin film, and utilizes optical transition between subbands in the quantum well structure. An element of this device can be formed as a film on a transparent substrate or a plastic substrate at a temperature of 200° C. or lower. The quatum well structure includes a barrier layer made of an insulating material such as ZnMgO; a homologous compound expressed by the following general formula: RMO3(AO)m, wherein R=Sc or In, M=Fe, Cr, Ga or Al, A=Zn, Mg, Cu, Mn, Fe, Co, Ni or Cd, and m=a natural number; or (Li, Na)(Ga, Al)O2.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: November 2, 2004
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Ohno, Masashi Kawasaki, Keita Ohtani
  • Patent number: 6803598
    Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: October 12, 2004
    Assignee: University of Delaware
    Inventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
  • Patent number: 6774389
    Abstract: A semiconductor optical device with improved optical gain and enhanced switching characteristics. The semiconductor optical device includes positive and negative electrodes for providing holes and electrons, respectively. The semiconductor optical device also includes an active layer between the positive and negative electrodes. The active layer includes a multiple quantum well structure having p-type quantum well layers and barrier layers. The quantum well layers are doped with an impurity that diffuses less than zinc so that trapping holes are produced and excessive electrons contributing no light emission are quenched by the trapping holes. The impurity can be beryllium, magnesium, or carbon.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiko Hanamaki
  • Patent number: 6774391
    Abstract: A logic device formed at least one chain of dots of magnetic material. Each dot has a width of 200 nm or less and is spaced at a distance that is sufficiently small to ensure magnetic interaction of adjacent dots.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: August 10, 2004
    Assignee: Cambridge University Technical Svcs.
    Inventor: Russell Cowburn
  • Publication number: 20040119065
    Abstract: A semiconductor device includes a memory portion in which a plurality of magneto-resistance effect elements each having a hard-axis of magnetization and an easy-axis of magnetization are arranged and one of binary data is written in all the magneto-resistance effect elements, and a circuit portion to which a write current is supplied to write only the other one of the binary data in only a selected magneto-resistance effect element selected from the magneto-resistance effect elements.
    Type: Application
    Filed: March 21, 2003
    Publication date: June 24, 2004
    Inventor: Takeshi Kajiyama
  • Patent number: 6717969
    Abstract: In a semiconductor laser device, a current confinement structure is realized by p-type and n-type layers formed above an active layer, where the p-type and n-type layers include a current stopping layer which has an opening for allowing current injection into only a predetermined stripe region of the active layer. In addition, a semiconductor layer is formed above the current confinement structure, and a pair of trenches are formed on both sides of the opening along the predetermined stripe region so as to extend from the semiconductor layer through the current stopping layer to at least the active layer. Further, an insulation film is formed on the semiconductor layer except that an area of the semiconductor layer located right above the predetermined stripe region is not covered by the insulation film, and an electrode is formed on the area of the semiconductor layer.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: April 6, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Hideki Asano
  • Patent number: 6703645
    Abstract: A spin filter is composed of a first magnetic semiconductor multi-quantum well structure, a second magnetic semiconductor multi-quantum well structure and a non-magnetic semiconductor quantum well structure which is located between the first magnetic semiconductor multi-quantum well structure and the second magnetic semiconductor multi-quantum well structure. The first magnetic semiconductor multi-quantum well structure and the second magnetic semiconductor multi-quantum well structure are split in spin state. Carriers in down-spin state are penetrated through the first magnetic semiconductor multi-quantum well structure and carriers in up-spin state are penetrated through the second magnetic semiconductor multi-quantum well structure.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: March 9, 2004
    Assignee: Tohoku University
    Inventors: Hideo Ohno, Keita Ohtani
  • Patent number: 6686610
    Abstract: A light emitting diode structure is formed on a substrate. A nucleation layer at low temperature is formed on the substrate. A buffer layer is formed on the nucleation layer for easing the subsequent formation of crystal growth. N active layer is disposed between an upper confinement layer and a lower confinement layer. The active layer include the semiconductor material doped with III-N elements. A contact layer is disposed on the upper confinement layer. A reversed tunneling layer is form on the contact layer, wherein the conductive types for both are different. A transparent layer is formed on the reversed tunneling layer. A cathode electrode contacts with the conductive buffer layer and is separated from the active layer and the transparent electrode.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: February 3, 2004
    Assignee: South Epitaxy Corporation
    Inventor: Jinn-Kong Sheu
  • Patent number: 6677624
    Abstract: Transistor, is disclosed, including a base having a bundle of (n,n) nanotubes, and an emitter and a collector connected to opposite sides of the base each having (n,m, n−m≠3 l) nanotubes, whereby substantially reducing a device size and improving an operation speed as the carbon nanotube has a thermal conductivity much better than silicon.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: January 13, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Ji Soon Ihm
  • Patent number: 6664559
    Abstract: Supermolecular structures and devices made from same. Semiconductor materials and devices are manufactured and provided which use controlled, discrete distribution of and positioning of single impurity atoms or molecules within a host matrix to take advantage of single charge effects. Single-dopant pn junctions and single-dopant bipolar cells are created. Each bipolar cell can function as a bistable device or an oscillator, depending on operating temperature. The cells can be used alone or in an array to make useful devices by adding an insulating substrate and contact electrodes.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: December 16, 2003
    Assignees: Semiconductor Research Corporation, North Carolina State University
    Inventors: Daniel Joseph Christian Herr, Victor Vladimirovich Zhirnov
  • Patent number: 6661022
    Abstract: An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: December 9, 2003
    Assignee: Japan Science and Technology Corporation
    Inventors: Takashi Morie, Atsushi Iwata, Makoto Nagata, Toshio Yamanaka, Tomohiro Matsuura
  • Patent number: 6646283
    Abstract: A switch device includes a source, a drain, and a gate electrode which are conductive, one or more semiconductor island layer(s) formed between the source and drain, an insulating film between the source and island layer, an insulating film between the drain and island layer, an insulating layer between island layers if a plurality of island layers are provided, and a gate capacitor formed by the gate electrode, at least one island layer, and a gate insulating film provided between the gate electrode and the island layer. The electric field applied to the gate capacitor is set to be substantially parallel with a channel current flowing via the island between the source and the drain.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 11, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hajime Akimoto, Kozo Katayama
  • Patent number: 6646285
    Abstract: The present invention provides a molecular device including a source region and a drain region, a molecular medium extending there between, and an electrically insulating layer between the source region, the drain region and the molecular medium. The molecular medium in the molecular device of present invention is a thin film having alternating monolayers of a metal—metal bonded complex monolayer and an organic monolayer.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Cherie R Kagan, Chun Lin
  • Patent number: 6617607
    Abstract: A nitride semiconductor laser device includes a nitride semiconductor substrate, and a layered portion corresponding to a nitride semiconductor film grown on the nitride semiconductor substrate, the layered portion including an n-type layer and a p-type layer and a light emitting layer posed between the n- and p-type layers, of the n- and p-type layers a layer opposite to the nitride semiconductor substrate with the light emitting layer opposed therebetween serving as an upper layer having a stripe of 1.9 &mgr;m to 3.0 &mgr;m in width, the light emitting layer and the upper layer having an interface distant from a bottom of the stripe by 0 &mgr;m to 0.2 &mgr;m.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: September 9, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigetoshi Ito, Yuhzoh Tsuda
  • Patent number: 6597011
    Abstract: An improved optical modulator and photodetector suitable for high frequency operation and compatible with monolithic microwave integrated circuit technology. Typical implementations use a reversed biased diode containing not intentionally doped (NID) optically active region sandwiched between conductive layers of p-doped and n-doped semiconductor layers, respectively. With monochromatic optical radiation incident upon the device a photocurrent (comprising of an electron-hole pair created for each photon absorbed) can be generated using the optical nonlinearity of the multiple quantum well structure inside the active region. This photocurrent can be used in an external circuit to provide photocurrent feedback to the device itself.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: July 22, 2003
    Assignee: Defence Science and Technology Organization
    Inventor: Petar Branko Atanackovic
  • Patent number: 6586787
    Abstract: A single electron device. Fabricated from nanoparticle derivatives, particularly from Au and fullerene nanoparticle derivatives, the device reduces thermal fluctuation in the nanoparticle array and has 15 nm of spacing between two electrodes.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: July 1, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Ming Shih, Wei-Fang Su, Yuh-Jiuan Lin, Cen-Shawn Wu, Chii-Dong Chen
  • Patent number: 6469315
    Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: October 22, 2002
    Assignee: Sony Corporation
    Inventors: Toshikazu Suzuki, Hideki Ono
  • Patent number: 6413880
    Abstract: The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm. The present invention also provides a method for forming Au and other metal nanowires that may be used for electrical conductors and both positive and negative etch masks to form a plurality of ridges at a pitch of 0.94 to 5.35 nm containing at least two adjacent grooves with widths of 0.63 to 5.04 nm.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: July 2, 2002
    Assignees: StarMega Corporation, Virginia Commonwealth University
    Inventors: Alison Baski, Don Kendall
  • Patent number: 6392914
    Abstract: A nonlinear coupling oscillator array is configured in such a manner that, for example, two layers in each of which a number of quantum dots as oscillators are arranged two-dimensionally are laid one on another. Adjacent quantum dots in the upper layer have tunnel coupling that exhibits a nonlinear current-voltage characteristic. The quantum dots in the upper layer receive an input of initial data/bias current, and each quantum dot in the upper layer is coupled with one quantum dot in the lower layer via a gate function having a time constant. Adjacent quantum dots in the lower layer do not interact with each other and the quantum dots in the lower layer are connected to the ground. For example, initial data are input by generating electron-hole pairs by applying light having an intensity profile corresponding to data, and injecting resulting electrons into the quantum dots of the upper layer.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: May 21, 2002
    Assignee: Sony Corporation
    Inventors: Yoshihiko Kuroki, Yoshifumi Mori, Ryuichi Ugajin
  • Patent number: 6339227
    Abstract: A monomolecular electronic device is provided that includes a molecular diode having at least one barrier insulating group chemically bonded between a pair of molecular ring structures to form a pair of diode sections, at least one dopant group chemically bonded to one of the pair of diode sections, and a molecular gate structure chemically bonded to the one diode section for influencing an intrinsic bias formed by the at least one dopant group. The device thus produced operates as a molecular electronic transistor, exhibiting both switching and power gain. By adding yet another insulating group to the other of the diode sections, an electrical resistance is formed to define an output which represents an inverter or NOT gate function. The NOT gate can be chemically bonded to molecular diode-diode logic structures to form a single molecule that exhibits complex Boolean functions and power gain.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: January 15, 2002
    Assignee: The Mitre Corporation
    Inventor: James C. Ellenbogen
  • Patent number: 6326311
    Abstract: There is provided a microstructure producing method capable of achieving satisfactory uniformity and reproducibility of the growth position, size and density of a minute particle or thin line and materializing a semiconductor device which can reduce the cost through simple processes without using any special microfabrication technique and has superior characteristics appropriate for mass-production with high yield and high productivity as well as a semiconductor device employing the microstructure. An oxide film 12 having a region 12a of a great film thickness and a region 12b of a small film thickness are formed on the surface of a semiconductor substrate 11. Next, a microstructure that is a thin line 15 made of silicon Si is selectively formed only on the surface of the small-film-thickness region 12b of the oxide film 12.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: December 4, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Fumitoshi Yasuo
  • Patent number: 6323504
    Abstract: A single-electron memory device using the electron-hole Coulomb blockade is provided. A single-electron memory device in accordance with an embodiment of the present invention includes a plurality of quantum dot tunnel-junction arrays, a gate electrode, and source and drain electrodes. The plurality of quantum dot tunnel-junction arrays include at least two tunnel-junctions, are parallelly coupled to each other, and are well separated from each other to prevent single-electron tunneling between them. One of the plurality of quantum dot tunnel-junction arrays includes the gate electrode, and the voltage applied to the gate electrode can vary the number of electron-hole pairs.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: November 27, 2001
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Min Cheol Shin, Seong Jae Lee, Kyoung Wan Park
  • Patent number: 6320216
    Abstract: It is made possible to conduct writing and erasing information at high speed with a low gate voltage, to attain high integration with reduced power dissipation and to retain information accurately. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. The conduction layer, the transition layers, and the charge accumulation layer are respectively made of Si. The barrier layers are respectively made of SiO2 so that electron affinity is made large and small alternately between those layers. Each capacitance respectively of the barrier layers is made smaller than e2/kBT so that charge transition does not occur according to the Coulomb blockade effect even if a voltage within a predetermined range is applied.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: November 20, 2001
    Assignee: Sony Corporation
    Inventor: Kazumasa Nomoto
  • Patent number: 6256767
    Abstract: A demultiplexer for a two-dimensional array of a plurality of nanometer-scale switches (molecular wire crossbar network) is disclosed. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction. The connector species comprises a bi-stable molecule. The demultiplexer comprises a plurality of address lines accessed by a first set of wires in the two-dimensional array by randomly forming contacts between each wire in the first set of wires to at least one of the address lines. The first set of wires crosses a second set of wires to form the junctions. The demultiplexer solves both the problems of data input and output to a molecular electronic system and also bridges the size gap between CMOS and molecules with an architecture that can scale up to extraordinarily large numbers of molecular devices.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: July 3, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Philip J. Kuekes, R. Stanley Williams
  • Patent number: 6204513
    Abstract: A heterostructure interband tunneling diode includes a contact layer comprising indium gallium arsenide of a first conductivity type, an injection layer comprising indium gallium arsenide of a second conductivity type, a first doped layer of the first conductivity type positioned adjacent to the contact layer, and a second doped layer of a second conductivity type juxtaposed between the first doped layer and the injection layer, wherein at least one of the first and second tunnel barrier layers comprises indium aluminium arsenide. A second embodiment includes a doped layer of the first conductivity type positioned adjacent to the contact layer, and a barrier layer positioned adjacent to the injection layer, and a quantum well layer comprising indium gallium arsenide juxtaposed between the doped layer and the barrier layer, wherein at least one of the doped and barrier layers comprises indium aluminium arsenide.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Nada El-Zein, Jonathan Lewis, Mandar R. Deshpande
  • Patent number: 6080996
    Abstract: The present invention discloses both an n+ and a p+ unipolar, three-terminal, resonant-tunneling transistor that can be operated as a hot-electron transistor or a field effect transistor at temperatures at least as low as 77 degree Kelvin. The doped first terminal (collector or gate) is made of 3D metal or semiconductor material. An undoped insulating barrier is deposited on the first terminal. The doped electrically-contacted second terminal (emitter or source), made of a 2D semiconductor material, is deposited on the insulating barrier. An undoped double-barrier resonant-tunneling structure is deposited on the second terminal. A doped third terminal, made of 3D metal or semiconductor material, is deposited on a portion of the double-barrier resonant-tunneling structure. A doped tunneling-contact, made of 3D metal or semiconductor material, is deposited on the double-barrier resonant-tunneling structure so that the tunneling contact is isolated from the third terminal.
    Type: Grant
    Filed: December 29, 1993
    Date of Patent: June 27, 2000
    Assignee: The United States of America as represented by the Director of the National Security Agency
    Inventor: Chia-Hung Yang
  • Patent number: 6064077
    Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: May 16, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Ravishankar Sandaresan
  • Patent number: 6060724
    Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 9, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Curt A. Flory, R. Stanley Williams
  • Patent number: 6060723
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: May 9, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 6044100
    Abstract: A VCSEL comprises a pair of multi-layered mirrors forming an optical cavity resonator having its axis perpendicular to the layers of the mirrors, an active region disposed within the resonator, and a current guide for directing pumping current through an aperture to generate stimulated emission of radiation which propagates along the resonator axis. A portion of the radiation forms an output signal which emerges through at least one of the mirrors. The current guide includes a lateral injection structure disposed between one of the mirrors and the current aperture. The lateral injection structure comprises at least one relatively thin, highly doped semiconductor layer, each of the highly doped layer(s) being located at a node of the standing wave of the intracavity radiation, at least one lower doped semiconductor layer disposed adjacent each of the highly doped layers (e.g.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: March 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: William Scott Hobson, Daryoosh Vakhshoori
  • Patent number: 6020605
    Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: February 1, 2000
    Assignee: Sony Corporation
    Inventor: Ryuichi Ugajin
  • Patent number: 5939729
    Abstract: The present invention relates to a semiconductor photoelectric device including a InAs layer formed to monoatomic thickness sandwiched between spacer layers adjacent to an emitter to maximize a difference in energy between two quantum states in accumulation layer of a resonant tunneling diode having a double barrier structure, resulting in separating the resonant tunneling current determined by two quantum states of the triangular well in accumulation layer of resonant tunneling diode, even when light of a low intensity is irradiated to the surface of the resonant tunneling diode. Thus, there is provided an optical controlled resonant tunneling diode, making it possible to manufacturing a switching device for controlling an electric signal using light source by adjusting, using light, the resonant tunneling determined by an excited state of the triangular well.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 17, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hye Yong Chu, Kyu-Suk Lee, Byueng-Su Yoo, Hyo-Hoon Park
  • Patent number: 5903010
    Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: May 11, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Curt A. Flory, R. Stanley Williams
  • Patent number: 5886385
    Abstract: A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Akira Nishiyama, Makoto Yoshimi
  • Patent number: 5831294
    Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: November 3, 1998
    Assignee: Sony Corporation
    Inventor: Ryuichi Ugajin
  • Patent number: 5828090
    Abstract: A charge transfer device comprises a quantum wire and a one-dimensional quantum dots array extending helically, for example, and including quantum dots which are aligned in close relation to couple with each other and to surround the quantum wire. By applying an external field within a plane normal to the quantum wire and by rotating the direction of the application of the external field, charges are transferred along the quantum wire.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventor: Ryuichi Ugajin
  • Patent number: 5767526
    Abstract: A solid-state frequency multiplier circuit (10) is provided which includes a bipolar quantum-well resonant tunneling transistor (12), a resistive load (14), and an A.C. output coupling capacitor (16), all which may be formed in a single integrated circuit or as discrete components. The value of the resistive load (14) determines the frequency multiplication factor of the circuit (10), and can produce frequencies in a range from about 2 GHz to over 20 GHz. A different embodiment of the present invention provides a frequency multiplication circuit (20) which generates a sinusoidal output waveform, without using an output A.C. coupling capacitor.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: June 16, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Alan C. Seabaugh