Quantum Well Patents (Class 257/14)
  • Patent number: 11522125
    Abstract: A semiconductor stack for a Hall effect device, which comprises: a bottom barrier comprising AlxGa1-xAs, a channel comprising InyGa1-yAs, on the bottom barrier, a channel barrier with a thickness which is at least 2 nm and which is smaller than or equal to 15 nm, and which at least comprises a first layer comprising AlzGa1-zAs with 0.1?z?0.22, wherein the first layer has a thickness of at least 2 nm, wherein a conduction band edge of the bottom barrier and the first layer is higher than a conduction band edge of the channel, a doping layer comprising a composition of Al, Ga and As and doped with n-type material, a top barrier comprising a composition of Al, Ga and As.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 6, 2022
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Kuan-Ting Ho, Lucian Barbut
  • Patent number: 11512252
    Abstract: A semiconductor nanocrystal particle including: a core including a first semiconductor material; and a shell disposed on the core, wherein the shell includes a second semiconductor material, wherein the shell is free of cadmium, wherein the shell has at least two branches and at least one valley portion connecting the at least two branches, and wherein the first semiconductor material is different from the second semiconductor material.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Garam Park, Eun Joo Jang, Yongwook Kim, Jihyun Min, Hyo Sook Jang, Shin Ae Jun, Taekhoon Kim, Yuho Won
  • Patent number: 11515684
    Abstract: There is provided a device to generate an output light. The device comprises a substrate, a quantum well structure (QWS) disposed on the substrate, and a waveguide disposed on the substrate and in contact with the QWS. The QWS has a first layer, a second layer, and a third layer. The second layer is disposed and quantum-confined between the first layer and the third layer. In addition, the second layer is to emit an input light when electrically biased. The input light has an optical field extending outside the QWS and into the waveguide, to optically couple the waveguide with the QWS. The waveguide is to provide an optical resonance cavity for the input light. Moreover, the waveguide has an optical outlet to transmit at least some of the input light out of the waveguide to generate the output light.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 29, 2022
    Assignee: GOOGLE LLC
    Inventor: Douglas Raymond Dykaar
  • Patent number: 11501045
    Abstract: A method for analyzing a simulation of the execution of a quantum circuit includes: a step of post-selecting one or more particular values of one or more qubits at one or more steps of the simulation; a step of setting filtration that sets the value of one or more quantum states of the quantum state vector(s) derived from the post-selection(s) of qubits; a step of analyzing the part of the simulation that corresponds to the post-selection(s) of qubits and to the quantum state vector(s) filtered.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 15, 2022
    Assignee: BULL SAS
    Inventor: Jean Noël Quintin
  • Patent number: 11489315
    Abstract: An on-chip integrated semiconductor laser structure and a method for preparing the same. The structure includes: an epitaxial structure including a first N contact layer, a first N confinement layer, a first active region, a first P confinement layer, a first P contact layer, an isolation layer, a second N contact layer, a second N confinement layer, a second active region, a second P confinement layer, and a second P contact layer sequentially deposited on a substrate; a first waveguide and a second waveguide; a first optical grating and a second optical grating; and current injection windows.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 1, 2022
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Chengao Yang, Zhichuan Niu, Yu Zhang, Yingqiang Xu, Shengwen Xie, Yi Zhang, Jinming Shang
  • Patent number: 11472094
    Abstract: The invention relates to a method for controlling confined preforms which are stopped in a heating station during a production interruption, the heating station comprising a device for conveying preforms comprising individual supports which move in a closed circuit and a heating cavity which is bordered by at least one row of transmitters of monochromatic electromagnetic radiation. The method includes a step of heating, by the transmitters of the heating cavity, the confined preforms referred to as “cold” preforms which have been stopped before being exposed to the electromagnetic radiation emitted by the transmitters.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 18, 2022
    Assignee: SIDEL PARTICIPATIONS
    Inventors: Yoann Lahogue, Guy Feuilloley
  • Patent number: 11476285
    Abstract: A light-receiving device includes at least one pixel. The at least one pixel includes a first electrode; a second electrode; and a photoelectric conversion layer between the first electrode and the second electrode. The photoelectric conversion layer is configured to convert incident infrared light into electric charge. The photoelectric conversion layer has a first section and a second section. The first section is closer to the first electrode than the second section, and the second section is closer to the second electrode than the first section. At least one of the first section and the second section have a plurality of surfaces.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 18, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shuji Manda, Tomoyuki Hirano
  • Patent number: 11469237
    Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
  • Patent number: 11462705
    Abstract: A photodetector is provided, including an active layer configured to generate charge carriers of a first type and of a second type by absorption of electromagnetic radiation; a first electrode configured to collect the charge carriers of the first type; and a second electrode configured to collect the charge carriers of the second type, the first electrode including a layer configured to collect the charge carriers of the first type, the layer including self-assembled monolayers, and nanowires comprising metal and functionalized by the self-assembled monolayers, the self-assembled monolayers of the layer are configured to functionalize the nanowires and to modify a work function of a material forming the nanowires. A method for manufacturing a photodetector and an electrode for a photodetector are also provided.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 4, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mohammed Benwadih, Olivier Haon
  • Patent number: 11454833
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 27, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11449384
    Abstract: Techniques for providing hardware-efficient fault-tolerant quantum operations are provided. In some aspects a cavity and an ancilla transmon are used to implement a quantum operation by encoding a logical qubit using more than two energy levels of the cavity, encoding information using more than two energy levels of the ancilla transmon, and creating an interaction between the cavity and the ancilla transmon that decouples at least one error type in the ancilla transmon from the cavity.
    Type: Grant
    Filed: January 5, 2019
    Date of Patent: September 20, 2022
    Assignee: Yale University
    Inventors: Serge Rosenblum, Philip Reinhold, Liang Jiang, Steven M. Girvin, Luigi Frunzio, Michel Devoret, Robert J. Schoelkopf, III
  • Patent number: 11421843
    Abstract: The present disclosure provides an apparatus for generating fiber delivered laser-induced dynamically controlled white light emission. The apparatus includes a laser diode unit for generating a laser electromagnetic radiation with a blue emission in a range from 395 nm to 490 nm that is delivered by an optical fiber. The apparatus further includes a dynamic phosphor unit configured to receive the laser exited from the optical fiber and controllably deflect a beam focused by a first optics sub-unit to a surface spot on a phosphor plate to produce a white light emission. Additionally, and the dynamic phosphor unit includes a second optics sub-unit configured to collect the white light emission and to project to a far field. Furthermore, the apparatus includes an electronics control unit comprising a laser diode driver and a MEMS driver for respectively control the laser diode unit and the dynamic phosphor unit in mutually synchronized manner.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 23, 2022
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: Jim Harrison, Lj Ristic, Oscar Romero, Eric Goutain, Paul Rudy, James W. Raring, Vlad Novotny
  • Patent number: 11415819
    Abstract: A beam steering apparatus includes a substrate; at least one light source provided on the substrate; a first waveguide configured to transmit a first light beam radiated from the at least one light source; at least one beam splitter configured to split the first light beam transmitted by the first waveguide to obtain a second light beam; a second waveguide configured to receive the second light beam; and a quantum dot optical amplifier provided on the second waveguide and comprising a barrier layer, a quantum dot layer, and a wetting layer, the quantum dot optical amplifier being configured to modulate a phase of the second light beam, and to amplify an intensity of the second light beam.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duhyun Lee, Bochul Park, Sunil Kim, Junghyun Park, Byunggil Jeong
  • Patent number: 11404612
    Abstract: A light-emitting device includes a plurality of light-emitting diodes, a first cured composition over a first subset of the light-emitting diodes, and a second cured composition over a second subset of light-emitting diodes. The first cured composition includes a first photopolymer and a blue photoluminescent material that is an organic, organometallic, or polymeric material, embedded in the first photopolymer. The second cured composition includes a second photopolymer and a nanomaterial embedded in the second photopolymer. The nanomaterial is selected to emit red or green light in response.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yingdong Luo, Lisong Xu, Sivapackia Ganapathiappan, Hou T. Ng, Byung Sung Kwak, Mingwei Zhu, Nag B. Patibandla
  • Patent number: 11387399
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Van H. Le
  • Patent number: 11387324
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; and a plurality of gates above the quantum well stack, wherein the gates are arranged in a ladder arrangement including two rails having at least N gates each and at least one active rung, and a number of active rungs in the ladder arrangement is less than N.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Adam Holmes, Sonika Johri, Anne Y. Matsuura, Ravi Pillarisetty, Thomas Francis Watson, James S. Clarke
  • Patent number: 11372511
    Abstract: A conducting thin film and preparation method therefor, a touch panel, and a display device are provided by the present disclosure. The conducting thin film includes a substrate, a conducting layer arranged on the substrate, a protecting layer arranged on the conducting layer, and an electricity conducting adhesive. The conducting layer includes a conducting net formed of conducting material. The protecting layer defines a plurality of openings for exposing the conducting material. The electricity conducting adhesive is formed on the protecting layer such that the electricity conducting adhesive passes through the plurality of openings in contact with the conducting material, and is filled in the plurality of openings. The protecting layer formed before the electricity conducting adhesive, thus reducing the problem of the conducting net breaking caused by the exposed conducting material being oxidized and vulmayized, and the thereby improving the conductivity of the conducting thin film.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: June 28, 2022
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Xin Chen, Yao Zhang
  • Patent number: 11366345
    Abstract: Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 21, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11355624
    Abstract: Embodiments are directed to electrically confined ballistic devices, circuits, and networks. One such device includes a heterostructure that has a first semiconductor layer, a second semiconductor layer, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. The device further includes an input electrode electrically coupled to the 2DEG layer and an output electrode electrically coupled to the 2DEG layer. A first confinement electrode is positioned on the heterostructure. The first confinement electrode, in use, generates first space charge regions which at least partially define a boundary of the ballistic device within the 2DEG layer between the input electrode and the output electrode in response to a first voltage.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 7, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Paolo Bramanti, Alberto Pagani
  • Patent number: 11355686
    Abstract: A unit pixel including a transparent substrate, a plurality of light emitting devices arranged on the transparent substrate, an adhesive layer bonding the light emitting devices to the transparent substrate, a step adjusting layer covering the light emitting device and bonded to the adhesive layer, a plurality of connection layers disposed on the step adjustment layer and electrically connected to the light emitting devices, in which the step adjustment layer has a concave-convex pattern along an edge thereof.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Seung Sik Hong
  • Patent number: 11352557
    Abstract: The present invention relates to a method for preparing a nanosized light emitting semiconductor material.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 7, 2022
    Assignee: Merck Patent GmbH
    Inventors: Artyom Semyonov, Ehud Shaviv
  • Patent number: 11355672
    Abstract: One embodiment comprises: a semiconductor substrate; a pattern layer disposed on the semiconductor substrate and comprising a plurality of patterns that are spaced apart from each other; a nitride semiconductor layer disposed on the pattern layer; and a semiconductor substrate disposed on the nitride semiconductor layer and comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, wherein the thermal conductivity of the pattern layer is higher than the thermal conductivity of the semiconductor substrate and the thermal conductivity of the semiconductor structure.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 7, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventor: Youn Joon Sung
  • Patent number: 11348026
    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 31, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Murray C. Thom, Aidan P. Roy, Fabian A. Chudak, Zhengbing Bian, William G. Macready, Robert B. Israel, Kelly T. R. Boothby, Sheir Yarkoni, Yanbo Xue, Dmytro Korenkevych
  • Patent number: 11342017
    Abstract: A memory is capable of storing coupled qubits. The memory includes a plurality of memory cells, wherein each of the memory cells is for storing values of one of the qubits. The memory also includes an electronic controller electrically connected to operate said memory cells. The controller is able to selectively store a qubit value to any of the memory cells in either a first state or a second state. The controller is configured to read any one of the memory cells in a manner dependent on whether the first state or the second state was previously used to store a qubit value in the same one of the memory cells.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 24, 2022
    Assignee: Nokia Technologies Oy
    Inventor: Robert L. Willett
  • Patent number: 11322652
    Abstract: A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 3, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Anna Volkova, Vladimir Ivantsov, Alexander Syrkin, Benjamin A. Haskell, Hussein S. El-Ghoroury
  • Patent number: 11283002
    Abstract: A primary single photon optoelectronic neuron includes a photonic synaptic input waveguide; an optoelectronic synapse; a synapto-dendritic electrical connection in communication with the optoelectronic synapse; an electronic dendrite in communication with the synapto-dendritic electrical connection; a dendrite-neuronal electrical interface in communication with the electronic dendrite; an integrator in communication with the dendrite-neuronal electrical interface; a superconducting wire in communication with the integrator; an axon hillock electronic-to-photonic transducer in communication with the superconducting wire; and an axonic waveguide in communication with the axon hillock electronic-to-photonic transducer and that receives the axonic photonic signal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 22, 2022
    Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Jeffrey M. Shainline, Manuel A. Castellanos-Beltran, Adam N. McCaughan, Sae Woo Nam
  • Patent number: 11282873
    Abstract: A photodetector includes: a photoelectric conversion layer including a first principal surface from which light enters and a second principal surface on the opposite side from the first principal surface and configured to perform photoelectric conversion on the light; a first diffraction grating formed on a side of the second principal surface and including a configuration where first surfaces which extend in a stripe state in a first direction and second surfaces which extend in a stripe state in the first direction and have a height difference with respect to the first surfaces are alternately arranged; metal wires provided at intervals over the first surfaces and the second surfaces and which extend in the first direction or a second direction perpendicular to the first direction; and a second diffraction grating formed over the first diffraction grating and including grooves which are formed at intervals and extend in the second direction.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 22, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Hiroyasu Yamashita
  • Patent number: 11258415
    Abstract: A neuromimetic circuit includes: a primary single photon optoelectronic neuron; a synapse in optical communication with the primary single photon optoelectronic neuron; and an axonic waveguide in optical communication with the primary single photon optoelectronic neuron and the synapse such that the axonic waveguide optically interconnects the primary single photon optoelectronic neuron and the synapse.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 22, 2022
    Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Jeffrey Shainline, Sae Woo Nam, Sonia Buckley
  • Patent number: 11258232
    Abstract: A light emitter includes a substrate, a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type different from the first conductivity type, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer and capable of emitting light when current is injected into the light emitting layer, and a third semiconductor layer provided between the substrate and the first semiconductor layer and having the second conductivity type, in which the first semiconductor layer is provided between the third semiconductor layer and the light emitting layer, and the third semiconductor layer has a protruding/recessed structure.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: February 22, 2022
    Inventors: Takafumi Noda, Yoji Kitano
  • Patent number: 11247914
    Abstract: Methods of synthesizing colloidal ternary Group III-V nanocrystals are provided. Also provided are the colloidal ternary Group III-V nanocrystals made using the methods. In the methods, molten inorganic salts are used as high temperature solvents to carry out cation exchange reactions that convert binary nanocrystals into ternary nanocrystals.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 15, 2022
    Assignee: The University of Chicago
    Inventors: Dmitri V. Talapin, Vishwas Srivastava
  • Patent number: 11227765
    Abstract: The invention provides a quantum dot manufacturing method and related quantum dot semiconductor structure. The quantum dot semiconductor structure includes: a conductive ridge on a substrate; an insulative layer covering the substrate and the conductive ridge, wherein the insulative layer includes a top portion and two sidewalls over the conductive ridge; a plurality of quantum dots respectively embedded within a plurality of silicon dioxide spacer islands, which are adhered to the sidewalls of the insulative layer; and a plurality of conductive ledges adhered to the silicon dioxide spacer islands, wherein each of the conductive ledges is a portion of an electrode with alignment to the corresponding quantum dot.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 18, 2022
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pei-Wen Li, Kang-Ping Peng, Ching-Lun Chen, Tsung-Lin Huang
  • Patent number: 11214484
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 4, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11210603
    Abstract: Techniques for automating quantum circuit debugging are provided that simulate standard debugging behaviors. The technology includes rewriting a source quantum circuit into instrumented circuits based on instrumentation instruction information inserted into software code that corresponds to the source quantum circuit. The instrumented circuits can executed to obtain measurement data corresponding to different state data of qubits within the source quantum circuit. The measurement data can be processed to output generated information corresponding to one or more internal states or processes of a quantum computer associated with the source quantum circuit.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lev Samuel Bishop, Andrew Cross, Jay Gambetta
  • Patent number: 11196233
    Abstract: A quantum cascade laser has a core region including a first injection layer, an active region, and a second injection layer. The active region includes a first well layer, a second well layer, a third well layer, a first barrier layer, and a second barrier layer. The first barrier layer is disposed between the first well layer and the second well layer and separates the first well layer from the second well layer. The second barrier layer is disposed between the second well layer and the third well layer and separates the second well layer from the third well layer. The first barrier layer has a thickness of 1.2 nm or less, and the second barrier layer has a thickness of 1.2 nm or less.
    Type: Grant
    Filed: January 26, 2020
    Date of Patent: December 7, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takashi Kato
  • Patent number: 11184555
    Abstract: An image sensor includes a plurality of pixels, where each of the plurality of pixels includes a photodiode. The image sensor is configured to capture images of a scene exposed with a flickering light source by for each of the plurality of pixels, acquiring a value representative of a light level at a corresponding pixel by gradually varying a value of sensitivity of the corresponding pixel.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 23, 2021
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS SA
    Inventors: Arnaud Bourge, Tarek Lule, Gregory Roffet
  • Patent number: 11181467
    Abstract: An all-glass optical atom-chamber with a vacuum higher than 1×10?8 Pa and a manufacturing method thereof are provided. The all-glass optical atom-chamber includes an optical vacuum chamber, at least one conduit, optical window sheets, at least one vacuum adapter, and pressing sheets. The optical vacuum chamber is a polyhedron with a plane of any shape; the plane of the polyhedron is provided with an optical window therein. Holes of the optical windows extending into the polyhedron form a same inner chamber. Each of the optical window sheets is fixed on respective optical windows. One end of each of the at least one conduit is fixedly connected to the optical vacuum chamber. The other end of the at least one conduit is connected to one end of the at least one vacuum adapter in one-to-one correspondence through a respective pressing sheet of the pressing sheets.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: November 23, 2021
    Assignees: EAST CHINA NORMAL UNIVERSITY BEIJING, XINNAN ZHIKE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yuelong Wu, Haibin Wu, Xin Li, Caiyin Pang, Rui Li, Kun Li, Yang Rui
  • Patent number: 11171242
    Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type formed over a substrate; a plurality of semiconductor nanowires formed of a compound semiconductor of the first conductivity type extending above the semiconductor layer; and a gate electrode formed around the semiconductor nanowires in a connection portion between the semiconductor layer and the semiconductor nanowires.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 9, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kenichi Kawaguchi, Naoya Okamoto, Yusuke Kumazaki, Tsuyoshi Takahashi
  • Patent number: 11171168
    Abstract: An optical detector that is sensitive in at least two infrared wavelength ranges: first spectral band and second spectral band; and having a set of pixels, comprising: an absorbent structure disposed on a lower face of a substrate and comprising a stack of at least one absorbent layer made of semi-conductor material; the detector further comprising a plurality of dielectric resonators on the upper surface of said substrate forming an upper surface metasurface, the metasurface configured to diffuse, deflect and focus in the pixels of the detector in a resonant manner, when illuminated by the incident light, a first beam having at least one first wavelength included in the first spectral band and a second beam having at least one second wavelength included in the second band, the metasurface also being configured so that said first and second beams are focused on different pixels of the detector.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 9, 2021
    Assignees: THALES, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alexandre Delga, Jean-Luc Reverchon
  • Patent number: 11133388
    Abstract: Semiconductor heterostructures, methods of making the heterostructures, and quantum dots and quantum computation devices based on the heterostructures are provided. The heterostructures include a quantum well of strained silicon seeded with a relatively low concentration of germanium impurities disposed between two quantum barriers of germanium or a silicon-germanium alloy. The quantum wells are characterized in that the germanium concentration in the wells has an oscillating profile that increases the valley splitting in the conduction band of the silicon quantum well.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert J. Joynt, Mark G. Friesen, Mark A. Eriksson, Susan Nan Coppersmith, Donald E. Savage
  • Patent number: 11133409
    Abstract: A semiconductor device includes a source, a drain, and a channel electrically connected to the source and the drain. The channel has a channel length from the drain to the source which is less than or equal to an electron mean free path of the channel material. A first gate has two arms, each extending between the drain and the source (i.e., at least a portion of the distance between the source and the drain). Each arm of the first gate is disposed proximate to a corresponding first and second edge of the channel. Each arm of the first gate has a periodic profile along an inner boundary, wherein the periodic profiles of each arm are offset from each other such that a distance between the arms is constant. A Bloch voltage applied to the first gate will reduce the effective channel with such that Bloch resonance conditions are met.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 28, 2021
    Assignee: The Research Foundation for The State University of New York
    Inventors: Victor Pogrebnyak, Jonathan Bird
  • Patent number: 11127879
    Abstract: Disclosed herein is a light emitting diode (LED), which includes a first-type semiconductor unit, an active layer formed on the first-type semiconductor unit, and a second-type semiconductor unit formed on the active layer oppositely of the first-type semiconductor unit. The second-type semiconductor unit includes a hole storage structure that has a polarization field having a direction pointing toward the active layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Daqian Ye, Dongyan Zhang, Chaoyu Wu, Duxiang Wang
  • Patent number: 11121158
    Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 14, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Ammo, Hirokazu Ejiri, Akiko Honjo
  • Patent number: 11112442
    Abstract: A quantum power sensor has a two-level quantum system strongly coupled to a transmission line that supports a propagating wave. A method of measuring power in a transmission line includes coupling a two-level quantum system to the transmission line; and determining the coupling and the Rabi frequency of the two-level system.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 7, 2021
    Assignee: NPL MANAGEMENT LIMITED
    Inventors: Oleg Vladimirovich Astafiev, Rais Shaikhaidarov, Vladimir Nikolaevich Antonov, Teresa Clare Hoenigl-Decrinis, Sebastian Erik De Graaf
  • Patent number: 11094860
    Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Odnoblyudov
  • Patent number: 11069798
    Abstract: A device includes a particle propagation channel, a particle deflector, a particle source, and a particle sink. The particle deflector facilitates ballistic transport of particles from a particle inflow portion through a particle flow deflection portion to a particle outflow portion. The particle deflector is arranged at the particle flow deflection portion and is activatable to deflect particles in the flow deflection portion and is configured to selectively prevent the particles from reaching the particle outflow portion. The particle source and particle sink are configured to cause a current path of the particles through the device.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: July 20, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Paolo Bramanti, Alberto Pagani
  • Patent number: 11070031
    Abstract: A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 20, 2021
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: James W. Raring, Mathew Schmidt, Christiane Poblenz
  • Patent number: 11069835
    Abstract: An optoelectronic semiconductor chip and a method for manufacturing a semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a plurality of fins and a current expansion layer for common contacting of at least some of the fins, wherein each fin includes two side surfaces arranged opposite one another and an active region arranged on each of the side surfaces, wherein the plurality of fins include inner fins and outer fins having an adjacent fin only on one side, and wherein the current expansion layer is in direct contact with the inner fins on their outside.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 20, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Adrian Stefan Avramescu, Tansen Varghese, Martin Straßburg, Hans-Jürgen Lugauer, Sönke Fündling, Jana Hartmann, Frederik Steib, Andreas Waag
  • Patent number: 11062903
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Neena Avinash Gilda, Lien-Yao Tsai, Baohua Niu
  • Patent number: 11063138
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11049995
    Abstract: A long-wavelength light emitting device is disclosed. The long-wavelength light emitting device comprises: a first conductive semi-conductor layer; an active layer that is located on the first conductive semi-conductor layer and that has a quantum well structure; and a second conductive semi-conductor layer that is located on the active layer. The active layer comprises: one or more well layers including a nitride-based semi-conductor having 21% or more In; two barrier layers located in upper and lower parts of the well layers, and located between the well layers and the barrier layers, wherein the upper capping layers have a bigger band-gap energy relative to the barrier layers, and the upper capping layers and the well layers are in contact.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 29, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Hong Jae Yoo, Hyo Shik Choi, Hyung Ju Lee