Quantum Well Patents (Class 257/14)
  • Patent number: 11948896
    Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11903225
    Abstract: A photodetector includes a first electrode; an interlayer disposed on the first electrode; a photoabsorbing layer disposed on the interlayer, the photoabsorbing layer having one or more charge transport materials, and a plurality of two-dimensional quantum dots (2D QDs) dispersed in the one or more charge transport material; and a second electrode disposed on the photoabsorbing layer. A heterostructure photodetector includes a first electrode; a first photoabsorbing layer disposed on the first electrode, the first photoabsorbing layer having a first photoabsorbing material; a second photoabsorbing layer disposed on the first photoabsorbing layer, the second photoabsorbing layer having a second photoabsorbing material; and a second electrode disposed on the second photoabsorbing layer.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 13, 2024
    Inventors: Nigel Pickett, Stuart Stubbs, Nathalie Gresty
  • Patent number: 11876150
    Abstract: The disclosure describes various aspects of strain management layers for light emitting elements such as light-emitting diodes (LEDs). The present disclosure describes an LED structure formed on a substrate and having a strain management region supported on the substrate, and an active region configured to provide a light emission associated with the LED structure. The strain management region includes a first layer including a superlattice having a plurality of repeated first and second sublayers, and a second layer including a bulk layer. In an embodiment, at least one of the first and second sublayers and the bulk layer includes a composition of InxAlyGa1-x-yN. A device having multiple LED structures and a method of making the LED structure are also described.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 16, 2024
    Assignee: GOOGLE LLC
    Inventors: Miao-Chan Tsai, Benjamin Leung, Richard Peter Schneider
  • Patent number: 11870005
    Abstract: An optoelectronic device comprising at least one quantum well (QW) and at least one quantum dot (QD) incorporated in the quantum well with the band gap of the quantum well being larger than the band gap of the quantum dot. The QDs and QD arrays are embedded in various QW, thus providing higher yields in optoelectronic devices, such as light emitting diodes, lasers, and photodetectors. This is achieved by a nearly complete suppression of the nonradiative Auger recombination and enhancement of the light extraction efficiency.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 9, 2024
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Alexander L. Efros, Michael Shur
  • Patent number: 11869794
    Abstract: A substrate support for a plasma chamber includes a base plate arranged along a plane, a first layer of an electrically insulating material arranged on the base plate along the plane, a plurality of heating elements arranged in the first layer along the plane, and a plurality of diodes arranged in respective cavities in the first layer. The plurality of diodes are connected in series to the plurality of heating elements, respectively. Each of the plurality of diodes includes a die of a semiconductor material arranged in a respective one of the cavities. The semiconductor material has a first coefficient of thermal expansion. A first side of the die is arranged on the first layer along the plane. A first terminal of the die is connected to a first electrical contact on the first layer.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 9, 2024
    Assignee: Lam Research Corporation
    Inventor: Siyuan Tian
  • Patent number: 11863989
    Abstract: A system and method for resisting quantum perturbation threats to quantum communication devices, especially to a quantum cyber security technology for sensing external perturbations to a quantum communication device and for performing perturbation-bias correction in a non-Hermitian system. Through observing and analyzing on a resonant model, such technology not only senses suspicious potential variation which may make potential energy related to a quantum computing device be changed, but also enhances to implement a correction policy coupling to an information-correction sub-system. Meanwhile it patterns the detected perturbation threats with relative permeability so as to provide early protection on a quantum communication device for resisting a risky perturbation threat.
    Type: Grant
    Filed: June 6, 2021
    Date of Patent: January 2, 2024
    Assignee: AhP-Tech Inc.
    Inventor: Chao-Huang Chen
  • Patent number: 11862743
    Abstract: An opto-electronic device includes a base portion, a first electrode and a second electrode formed on an upper surface of the base portion apart from each other, a quantum dot layer, and a bank structure. The quantum dot layer is between the first electrode and the second electrode on the base portion and includes a plurality of quantum dots. The bank structure covers at least partial regions of the first electrode and the second electrode, defines a region where the quantum dot layer is formed, and is formed of an inorganic material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanwook Baik, Kyungsang Cho, Hojung Kim, Yooseong Yang
  • Patent number: 11848400
    Abstract: A device having a layered structure that includes a layer of phase change material and a matrix material layer having embedding quantum emitters is tuned. An electric field is applied through the matrix material layer and the layer of phase change material to change the emission wavelengths of the quantum emitters. A phase of the phase change material is changed, in a non-volatile manner, in each of one or more of local areas of the phase change material, to form local alterations that are opposite to respective ones of the quantum emitters in the matrix material layer, to locally modify the electric field at the respective quantum emitters.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Thilo Hermann Curt Stoeferle, Michael A. Becker, Rainer F. Mahrt, Darius Urbonas, Fabio Scafirimuto
  • Patent number: 11848401
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: December 19, 2023
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Patent number: 11822163
    Abstract: A novel and useful quantum computing machine includes classic computing and quantum computing cores. A programmable pattern generator executes instructions that control the quantum core. A pulse generator generates the control signals input to the quantum core to perform quantum operations. A partial readout of the quantum state is re-injected into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the readout before being re-injected into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or retrieved from classic memory where sequences of commands are stored in memory. A cryostat unit functions to cool the quantum computing core to approximately 4 Kelvin.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 21, 2023
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11817492
    Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang
  • Patent number: 11809179
    Abstract: Many different types of systems are utilized and tasks are performed in a marine environment. The present invention provides various configurations of castable devices that can be operated and/or controlled for such systems or tasks. One or more castable devices can be integrated with a transducer assembly, such as a phased array, that emits sonar beams and receives sonar returns from the underwater environment. Processing circuitry may receive the sonar returns, process the sonar returns, generate an image, and transmit the image to a display.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: November 7, 2023
    Assignee: Navico, Inc.
    Inventors: Jeremiah Clark, Matthew Laster, William B. Newberry, Jr., Kristopher C. Snyder
  • Patent number: 11791788
    Abstract: The present disclosure relates to parametric amplifiers that can be used in the presence of a magnetic field. In particular the present disclosure relates to an integrated signal amplifier that comprises: a quantum dot; a first conductive electrode arranged in a manner such that tunnelling of electrons to the quantum dot is prevented; and a second conductive electrode arranged in a manner such tunnelling of electrons to the quantum dot is permitted. When an oscillating signal is applied across the first and second electrodes, the equivalent capacitance across the first and the second electrodes oscillates at the frequency of the oscillating signal.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 17, 2023
    Assignee: NEWSOUTH INNOVATIONS PTY LTD
    Inventor: Matthew G. House
  • Patent number: 11788699
    Abstract: The present disclosure provides an apparatus for generating fiber delivered laser-induced dynamically controlled white light emission. The apparatus includes a laser diode unit for generating a laser electromagnetic radiation with a blue emission in a range from 395 nm to 490 nm that is delivered by an optical fiber. The apparatus further includes a dynamic phosphor unit configured to receive the laser exited from the optical fiber and controllably deflect a beam focused by a first optics sub-unit to a surface spot on a phosphor plate to produce a white light emission. Additionally, and the dynamic phosphor unit includes a second optics sub-unit configured to collect the white light emission and to project to a far field. Furthermore, the apparatus includes an electronics control unit comprising a laser diode driver and a MEMS driver for respectively control the laser diode unit and the dynamic phosphor unit in mutually synchronized manner.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 17, 2023
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: Jim Harrison, Lj Ristic, Oscar Romero, Eric Goutain, Paul Rudy, James W. Raring, Vlad Novotny
  • Patent number: 11764064
    Abstract: Provided are a monitoring device and method. A monitoring device includes a laser processor configured to emit a processing laser beam to perform a melting annealing process on a wafer; a laser monitor configured to emit a monitoring laser beam onto the wafer while the laser processor performs the melting annealing process, the laser monitor configured to measure reflectivity of the wafer; and a data processor configured to process data on the reflectivity measured by the laser monitor, and monitor one or more characteristics of the wafer based on the data on the reflectivity.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Hoon Lee, Ill Hyun Park, Tae Hee Han, Jin Won Ma, Byung Joo Oh, Bong Ju Lee, Jae Hee Lee, Joo Yong Lee, Nam Ki Cho, Chang Seong Hong
  • Patent number: 11764327
    Abstract: A light-emitting diode includes an n-type aluminum nitride layer formed on a substrate, a multiple quantum well formed on the n-type aluminum nitride layer, and a p-type aluminum nitride hole-injection layer formed adjacent to the multiple quantum well. The multiple quantum well includes a first aluminum nitride quantum well layer having a fixed composition and surrounded by first and second aluminum nitride quantum barrier layers, and a second aluminum nitride quantum well layer having a fixed composition and surrounded by the second aluminum nitride quantum barrier layer and a third aluminum nitride quantum barrier layer. At least one of the first, second, and third aluminum nitride quantum barrier layers has a graded aluminum composition. The first aluminum nitride quantum barrier layer is adjacent to the n-type aluminum nitride layer and the third aluminum nitride quantum barrier layer is adjacent to the p-type aluminum nitride hole-injection layer.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 19, 2023
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Xiaohang Li
  • Patent number: 11760640
    Abstract: This disclosure provides a nano-graphitic sponge (NGS) and methods for preparing the nano-graphitic sponge. The disclosed nano-graphitic sponge possesses many excellent properties, including large surface areas and pore volumes, low-mass densities, good electrical conductivities and mechanical properties. These excellent properties make the nano-graphitic sponge an ideal material for many applications, such as electrodes for batteries and supercapacitors, fuel cells and solar cells, catalysts and catalyst supports, and sensors.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 19, 2023
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Thomas J. Nosker, Bernard H. Kear, Nofel Z. Whieb, Jennifer K. Lynch-Branzoi, Arya S. Tewatia
  • Patent number: 11764339
    Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 19, 2023
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Biebersdorf, Laura Kreiner, Stefan Illek, Ines Pietzonka, Petrus Sundgren, Christoph Klemp, Felix Feix, Christian Berger, Ana Kanevce
  • Patent number: 11742472
    Abstract: A displaying apparatus including a panel substrate and pixel modules arranged thereon, each pixel module including a circuit board and unit pixels on the circuit board, in which each unit pixel includes light emitting devices longitudinally extending along a first direction on the circuit board and including a substrate, a light emitting structure including first and second conductivity type semiconductor layers and an active layer therebetween, a first connection layer electrically connected to the first conductivity type semiconductor layer, a second connection layer electrically connected to the second conductivity type semiconductor layer, a step adjustment layer disposed between the first connection layer and the second connection layer and covering a portion of the light emitting device, in which the light emitting devices in the unit pixel are arranged in a second direction crossing the first direction.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 29, 2023
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Seung Sik Hong
  • Patent number: 11728448
    Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes steps of providing a cavity structure, the cavity structure including a seed area including a seed material. The method further includes growing, within the cavity structure, a first embedding layer in a first growth direction from a seed surface of the seed material. The method includes further steps of removing the seed material, growing, in a second growth direction, from a seed surface of the first embedding layer, a quantum dot structure and growing, within the cavity structure, on a surface of the quantum dot structure, a second embedding layer in the second growth direction. The second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: August 15, 2023
    Assignee: International Business Machines Corporation
    Inventors: Markus Scherrer, Kirsten Emilie Moselund, Preksha Tiwari, Noelia Vico Trivino
  • Patent number: 11721748
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11721723
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11706936
    Abstract: A light emitting device including a first electrode and a second electrode spaced from each other, and, a light emitting film between the first electrode and the second electrode, wherein the light emitting film has a first surface facing the second electrode and a second surface opposite thereto, the light emitting film includes a quantum dot layer including a plurality of quantum dots and a matrix including a metal chalcogenide, the plurality of quantum dots includes selenium, the matrix covers at least a portion of the quantum dot layer, the metal chalcogenide comprises zinc and sulfur, and in an X-ray photoelectron spectroscopic analysis of the first surface of the light emitting film, a mole ratio of zinc with respect to selenium is greater than or equal to about 2:1 and a mole ratio of sulfur with respect to selenium is greater than or equal to about 1.1:1.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanghee Kim, Moon Gyu Han, Eun Joo Jang, Hyo Sook Jang
  • Patent number: 11700776
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Van H. Le
  • Patent number: 11698341
    Abstract: Building blocks are provided for on-chip chemical sensors and other highly-compact photonic integrated circuits combining interband or quantum cascade lasers and detectors with passive waveguides and other components integrated on a III-V or silicon. A MWIR or LWIR laser source is evanescently coupled into a passive extended or resonant-cavity waveguide that provides evanescent coupling to a sample gas (or liquid) for spectroscopic chemical sensing. In the case of an ICL, the uppermost layer of this passive waveguide has a relatively high index of refraction that enables it to form the core of the waveguide, while the ambient air, consisting of the sample gas, functions as the top cladding layer. A fraction of the propagating light beam is absorbed by the sample gas if it contains a chemical species having a fingerprint absorption feature within the spectral linewidth of the laser emission.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: July 11, 2023
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Igor Vurgaftman, Chadwick Lawrence Canedy, William W. Bewley, Chul Soo Kim, Charles D. Merritt, Michael V. Warren, R. Joseph Weiblen, Mijin Kim
  • Patent number: 11699747
    Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Sarah Atanasov, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts, Stephanie A. Bojarski
  • Patent number: 11695254
    Abstract: An optical apparatus comprises a semiconductor substrate and a slab-coupled optical waveguide (SCOW) emitter disposed on the semiconductor substrate. The SCOW emitter comprises an optical waveguide comprising: a first region doped with a first conductivity type; a second region doped with a different, second conductivity type; and an optically active region disposed between the first region and the second region. The optically active region comprises a plurality of quantum dots.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: July 4, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Dominic F. Siriani, Jock T. Bovington, Matthew J. Traverso
  • Patent number: 11681598
    Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: June 20, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Rajat Sagar, Niraj Nandan, Kedar Chitnis, Brijesh Jadav, Mihir Mody
  • Patent number: 11677045
    Abstract: A light-emitting diode includes a semiconductor body and electrical connection points for contacting the semiconductor body, the semiconductor body including an active region including a quantum well that generates electromagnetic radiation, a first region and a second region that impede passage of charge carriers from the active region, wherein the semiconductor body is based on a nitride compound semiconductor material, the first region is directly adjacent to the active region on a p-side, the second region is arranged on a side of the first region facing away from the active region, the first region has an electronic band gap larger than the electronic band gap of the quantum well and less than or equal to an electronic band gap of the second region, the first region and the second region contain aluminum, and the active region emits electromagnetic radiation having a peak wavelength of less than 480 nm.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: June 13, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Werner Bergbauer, Joachim Hertkorn, Alexander Walter
  • Patent number: 11664446
    Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Hubert C. George, James S. Clarke
  • Patent number: 11658267
    Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: May 23, 2023
    Assignee: Ohio State Innovation Foundation
    Inventors: Siddharth Rajan, Yuewei Zhang, Zane Jamal-Eddine, Fatih Akyol
  • Patent number: 11641000
    Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 2, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhaoyao Zhan, Qianwei Ding, Xiaohong Jiang, Ching Hwa Tey
  • Patent number: 11631768
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Patent number: 11630334
    Abstract: Examples described herein relate to an optical coupler. The optical coupler may include a first optical waveguide base layer, a second optical waveguide base layer, an insulating layer disposed over at least a portion of both the first optical waveguide base layer and the second optical waveguide base layer, and a semiconductor material layer disposed over the insulating layer. Overlapping portions of the first optical waveguide base layer, the insulating layer, and the semiconductor material layer form a first optical waveguide, and overlapping portions of the second optical waveguide base layer, the insulating layer, and the semiconductor material layer form a second optical waveguide. Moreover, the optical coupler may include a plurality of metal contacts to receive one or more first biasing voltages to operate one of the first optical waveguide base layer and the second optical waveguide base layer in an accumulation mode.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: April 18, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Stanley Cheung, Di Liang, Sudharsanan Srinivasan
  • Patent number: 11631783
    Abstract: In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in p
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 18, 2023
    Assignee: OSRAM OLED GMBH
    Inventors: Fabian Kopp, Attila Molnar, Bjoern Muermann, Franz Eberhard
  • Patent number: 11624027
    Abstract: A quantum dot according to an embodiment includes a core including a first semiconductor nanocrystal including zinc, selenium, and tellurium and a semiconductor nanocrystal shell on the core, the semiconductor nanocrystal shell including a zinc chalcogenide, wherein the quantum dot does not include cadmium, the zinc chalcogenide includes zinc and selenium, the quantum dot further includes gallium and a primary amine having 5 or more carbon atoms, and the quantum dot is configured to emit light having a maximum emission peak in a range of greater than about 450 nanometers (nm) and less than or equal to about 480 nm by excitation light. A method of producing the quantum dot and an electronic device including the same are also disclosed.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Woo Kim, Eun Joo Jang, Hyo Sook Jang, Hwea Yoon Kim, Yuho Won
  • Patent number: 11604371
    Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: March 14, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Charles Baudot
  • Patent number: 11605753
    Abstract: A semiconductor light-emitting element includes: an n-type contact layer; an n-side inserted layer provided on a first upper surface of the n-type contact layer, made of an AlGaN-based semiconductor material, and having a thickness equal to or smaller than 5 nm; an n-type clad layer provided on the n-side inserted layer; an active layer provided on the n-type clad layer and including a well layer and a barrier layer made of an AlGaN-based semiconductor material; a p-type clad layer provided on the active layer; a p-side inserted layer provided on the p-type clad layer, made of an AlGaN-based semiconductor material, and having a thickness equal to or smaller than 5 nm; and a p-type contact layer provided on the p-side inserted layer. An AlN composition of each of the n-side and p-side inserted layers is higher than an AlN composition of the barrier layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 14, 2023
    Assignee: NIKKISO CO., LTD.
    Inventor: Tetsu Hiko Inazu
  • Patent number: 11594623
    Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 28, 2023
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Feng Xu, Bin Gao, Xinyi Li, Huaqiang Wu, He Qian
  • Patent number: 11588062
    Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector includes a photodetector pad coupled to a waveguide core and a light-absorbing layer coupled to the photodetector pad. The light-absorbing layer has a body, a first taper that projects laterally from the body toward the waveguide core, and a second taper that projects laterally from the body toward the waveguide core. The photodetector pad includes a tapered section that is laterally positioned between the first taper and the second taper of the light-absorbing layer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 21, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Abdelsalam Aboketaf, Yusheng Bian
  • Patent number: 11557693
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 17, 2023
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Patent number: 11557686
    Abstract: A quantum dot structure, a radiation conversion element and a light emitting device are disclosed. In an embodiment a quantum dot structure includes an active region configured to emit radiation, a barrier region surrounding the active region and a trap region spaced apart from the active region, wherein a band edge of the trap region forms a trap configuration with respect to the barrier region for at least one type of charge carrier.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 17, 2023
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: David O'Brien, Joseph Treadway
  • Patent number: 11548202
    Abstract: The invention concerns a method for managing captive preforms immobilized in a heating station during an interruption of production, the preforms following a production stream, the heating station including a device for conveying preforms and a heating cavity bordered by at least one row of emitters of monochromatic electromagnetic radiation. The method consists in ejecting from the production stream the cold captive preforms that have been immobilized before they have been exposed to the electromagnetic radiation emitted by the emitters to a recycling stream and rejecting from the production stream the hot captive preforms that have been at least partly exposed to the electromagnetic radiation emitted by the emitters to a reject stream separate from the recycling stream.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 10, 2023
    Assignee: SIDEL PARTICIPATIONS
    Inventors: Yoann Lahogue, Guy Feuilloley
  • Patent number: 11545351
    Abstract: An electrospray apparatus including a plurality of emitters, disposed on a substrate, wherein the plurality of emitters can have a narrow parameter distribution.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: January 3, 2023
    Assignee: Accion Systems, Inc.
    Inventors: Louis Perna, Christy Petruczok, Alexander Bost
  • Patent number: 11544438
    Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 3, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Paul Accisano, Kenneth Reneris
  • Patent number: 11539189
    Abstract: An optical apparatus comprises a semiconductor substrate and a slab-coupled optical waveguide (SCOW) emitter disposed on the semiconductor substrate. The SCOW emitter comprises an optical waveguide comprising: a first region doped with a first conductivity type; a second region doped with a different, second conductivity type; and an optically active region disposed between the first region and the second region. The optically active region comprises a plurality of quantum dots.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 27, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Dominic F. Siriani, Jock T. Bovington, Matthew J. Traverso
  • Patent number: 11531922
    Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventor: Xiang Zou
  • Patent number: 11527446
    Abstract: Embodiments of the invention are directed to a fabrication method that includes forming a first-region channel over a first region of a substrate, wherein the first-region channel further includes lateral sidewalls having a length (L), a first end sidewall having a first width (W1), and a second end sidewall having a second width (W2). L is greater than W1, and L is greater than W2. A first stress anchor is formed on the first end sidewall of the first-region channel, and a second stress anchor is formed on the second end sidewall of the first-region channel. The first stress anchor is configured to impart strain through the first end sidewalls to the first-region channel. The second stress anchor is configured to impart strain through the second end sidewalls to the first-region channel.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Julien Frougier, Ruilong Xie
  • Patent number: 11522125
    Abstract: A semiconductor stack for a Hall effect device, which comprises: a bottom barrier comprising AlxGa1-xAs, a channel comprising InyGa1-yAs, on the bottom barrier, a channel barrier with a thickness which is at least 2 nm and which is smaller than or equal to 15 nm, and which at least comprises a first layer comprising AlzGa1-zAs with 0.1?z?0.22, wherein the first layer has a thickness of at least 2 nm, wherein a conduction band edge of the bottom barrier and the first layer is higher than a conduction band edge of the channel, a doping layer comprising a composition of Al, Ga and As and doped with n-type material, a top barrier comprising a composition of Al, Ga and As.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 6, 2022
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Kuan-Ting Ho, Lucian Barbut
  • Patent number: 11515684
    Abstract: There is provided a device to generate an output light. The device comprises a substrate, a quantum well structure (QWS) disposed on the substrate, and a waveguide disposed on the substrate and in contact with the QWS. The QWS has a first layer, a second layer, and a third layer. The second layer is disposed and quantum-confined between the first layer and the third layer. In addition, the second layer is to emit an input light when electrically biased. The input light has an optical field extending outside the QWS and into the waveguide, to optically couple the waveguide with the QWS. The waveguide is to provide an optical resonance cavity for the input light. Moreover, the waveguide has an optical outlet to transmit at least some of the input light out of the waveguide to generate the output light.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 29, 2022
    Assignee: GOOGLE LLC
    Inventor: Douglas Raymond Dykaar