Quantum Well Patents (Class 257/14)
  • Patent number: 11133409
    Abstract: A semiconductor device includes a source, a drain, and a channel electrically connected to the source and the drain. The channel has a channel length from the drain to the source which is less than or equal to an electron mean free path of the channel material. A first gate has two arms, each extending between the drain and the source (i.e., at least a portion of the distance between the source and the drain). Each arm of the first gate is disposed proximate to a corresponding first and second edge of the channel. Each arm of the first gate has a periodic profile along an inner boundary, wherein the periodic profiles of each arm are offset from each other such that a distance between the arms is constant. A Bloch voltage applied to the first gate will reduce the effective channel with such that Bloch resonance conditions are met.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 28, 2021
    Assignee: The Research Foundation for The State University of New York
    Inventors: Victor Pogrebnyak, Jonathan Bird
  • Patent number: 11133388
    Abstract: Semiconductor heterostructures, methods of making the heterostructures, and quantum dots and quantum computation devices based on the heterostructures are provided. The heterostructures include a quantum well of strained silicon seeded with a relatively low concentration of germanium impurities disposed between two quantum barriers of germanium or a silicon-germanium alloy. The quantum wells are characterized in that the germanium concentration in the wells has an oscillating profile that increases the valley splitting in the conduction band of the silicon quantum well.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert J. Joynt, Mark G. Friesen, Mark A. Eriksson, Susan Nan Coppersmith, Donald E. Savage
  • Patent number: 11127879
    Abstract: Disclosed herein is a light emitting diode (LED), which includes a first-type semiconductor unit, an active layer formed on the first-type semiconductor unit, and a second-type semiconductor unit formed on the active layer oppositely of the first-type semiconductor unit. The second-type semiconductor unit includes a hole storage structure that has a polarization field having a direction pointing toward the active layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Daqian Ye, Dongyan Zhang, Chaoyu Wu, Duxiang Wang
  • Patent number: 11121158
    Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 14, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Ammo, Hirokazu Ejiri, Akiko Honjo
  • Patent number: 11112442
    Abstract: A quantum power sensor has a two-level quantum system strongly coupled to a transmission line that supports a propagating wave. A method of measuring power in a transmission line includes coupling a two-level quantum system to the transmission line; and determining the coupling and the Rabi frequency of the two-level system.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 7, 2021
    Assignee: NPL MANAGEMENT LIMITED
    Inventors: Oleg Vladimirovich Astafiev, Rais Shaikhaidarov, Vladimir Nikolaevich Antonov, Teresa Clare Hoenigl-Decrinis, Sebastian Erik De Graaf
  • Patent number: 11094860
    Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Odnoblyudov
  • Patent number: 11070031
    Abstract: A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 20, 2021
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: James W. Raring, Mathew Schmidt, Christiane Poblenz
  • Patent number: 11069835
    Abstract: An optoelectronic semiconductor chip and a method for manufacturing a semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a plurality of fins and a current expansion layer for common contacting of at least some of the fins, wherein each fin includes two side surfaces arranged opposite one another and an active region arranged on each of the side surfaces, wherein the plurality of fins include inner fins and outer fins having an adjacent fin only on one side, and wherein the current expansion layer is in direct contact with the inner fins on their outside.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 20, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Adrian Stefan Avramescu, Tansen Varghese, Martin Straßburg, Hans-Jürgen Lugauer, Sönke Fündling, Jana Hartmann, Frederik Steib, Andreas Waag
  • Patent number: 11069798
    Abstract: A device includes a particle propagation channel, a particle deflector, a particle source, and a particle sink. The particle deflector facilitates ballistic transport of particles from a particle inflow portion through a particle flow deflection portion to a particle outflow portion. The particle deflector is arranged at the particle flow deflection portion and is activatable to deflect particles in the flow deflection portion and is configured to selectively prevent the particles from reaching the particle outflow portion. The particle source and particle sink are configured to cause a current path of the particles through the device.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: July 20, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Paolo Bramanti, Alberto Pagani
  • Patent number: 11063138
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11062903
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Neena Avinash Gilda, Lien-Yao Tsai, Baohua Niu
  • Patent number: 11049995
    Abstract: A long-wavelength light emitting device is disclosed. The long-wavelength light emitting device comprises: a first conductive semi-conductor layer; an active layer that is located on the first conductive semi-conductor layer and that has a quantum well structure; and a second conductive semi-conductor layer that is located on the active layer. The active layer comprises: one or more well layers including a nitride-based semi-conductor having 21% or more In; two barrier layers located in upper and lower parts of the well layers, and located between the well layers and the barrier layers, wherein the upper capping layers have a bigger band-gap energy relative to the barrier layers, and the upper capping layers and the well layers are in contact.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 29, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Hong Jae Yoo, Hyo Shik Choi, Hyung Ju Lee
  • Patent number: 11043517
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 22, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 11024775
    Abstract: A device, system and method for producing enhanced external quantum efficiency (EQE) LED emission are disclosed. The device, system and method include a patterned layer configured to transform surface modes into directional radiation, a semiconductor layer formed as a III/V direct bandgap semiconductor to produce radiation, and a metal back reflector layer configured to reflect incident radiation. The patterned layer may be one-dimensional, two-dimensional or three-dimensional. The patterned layer may be submerged within the semiconductor layer or within the dielectric layer. The semiconductor layer is p-type gallium nitride (GaN). The patterned layer may be a hyperbolic metamaterials (HMM) layer and may include Photonic Hypercrystal (PhHc), or may be a low or high refractive index material or may be a metal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 1, 2021
    Assignee: Lumileds LLC
    Inventors: Venkata Ananth Tamma, Toni Lopez
  • Patent number: 11018277
    Abstract: A semiconductor layer sequence and a method for producing a semiconductor layer sequence are disclosed. In an embodiment a semiconductor layer sequence includes a first nitridic compound semiconductor layer, an intermediate layer, a second nitridic compound semiconductor layer and an active layer, wherein the intermediate layer comprises an AlGaN layer with an Al content of at least 5%, wherein the second nitridic compound semiconductor layer has a lower proportion of Al than the AlGaN layer such that relaxed lattice constants of the AlGaN layer of the intermediate layer and of the second nitridic compound semiconductor layer differ, wherein the second nitridic compound semiconductor layer and the active layer are grown on the intermediate layer in a lattice-matched manner, wherein the active layer comprises one or more layers of AlInGaN, and wherein an In content in each of the layers of AlInGaN is at most 12%.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 25, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Werner Bergbauer, Lise Lahourcade, Jürgen Off
  • Patent number: 11016315
    Abstract: A photonic computing system, preferably including an input module, a computation module, and/or control module. The photonic computing system can include one or more optical filter banks, such as in the computation module and/or any other suitable modules. Each optical filter bank preferably includes a plurality of photonic bandgap phase modulators. Each photonic bandgap phase modulator preferably includes a set of photonic crystal segments. The photonic crystal segments can preferably be controlled to transition light propagation between two or more photonic bands.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 25, 2021
    Assignee: Luminous Computing, Inc.
    Inventors: Mitchell A. Nahmias, Michael Gao
  • Patent number: 11004888
    Abstract: A photoelectric conversion element and an optical sensor including the same are disclosed. The photoelectric conversion element may include a plurality of lattice stacks repeatedly stacked on top of each other on a substrate and configured to have an effective band gap. The plurality of lattice stacks may each include a first active layer and a second active layer on the first active layer. The first active layer may include a first two-dimensional material having a first band gap. The second active layer may include a second two-dimensional material having a second band gap not overlapping the first band gap. An effective band gap may be adjusted based on the first two-dimensional materials and thicknesses of the first active layer and the second active layer and a number of times of plurality of lattice stacks.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeryong Kim, Jaeho Lee, Sanghyun Jo, Hyeonjin Shin
  • Patent number: 11001606
    Abstract: Compositions and methods of the present disclosure provide for staged assembly of nucleic acid microstructures made of an array of x number of polynucleotide tiles, where each of the polynucleotide tiles is a polygon configuration and is made from a single-stranded helical polynucleotide scaffold and a plurality of single-stranded polynucleotide staple strands of y number of unique staple sequences corresponding to the selected tile configuration, the y number of unique staple sequences capable of being constant for any value of x.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 11, 2021
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Grigory Tikhomirov, Philip F. Petersen, Lulu Qian
  • Patent number: 10978578
    Abstract: Scalable quantum dot devices and methods are described. An example quantum dot device may comprise one or more repeated cells of a repeating quantum dot structure. The repeated cells may be arranged as a linear array of quantum dots. A single repeated cell may comprise a plurality of quantum dots. The repeated cells may be configured to cause movement of a single electron between adjacent quantum dots. A repeated cell may also comprise a charge sensor for readout of the plurality of quantum dots.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 13, 2021
    Assignee: The Trustees of Princeton University
    Inventors: Jason Petta, David Zajac, Thomas Hazard
  • Patent number: 10972190
    Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 6, 2021
    Assignee: Omnisent, LLC
    Inventors: Joseph Eric Henningsen, Clifford Tureman Lewis
  • Patent number: 10962703
    Abstract: Provided herein are compositions comprising functionalized gallium-based semiconductor nanoparticles for use in nanoprint resins and high-index overcoat materials. Also provided are methods of manufacturing functionalized gallium-based semiconductor nanoparticles and nanoprint resins and high-index overcoat materials using gallium-based semiconductor nanoparticles.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 30, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Austin Lane, Matthew E. Colburn, Giuseppe Calafiore
  • Patent number: 10964837
    Abstract: According to embodiments of the present disclosure, a dynamic photodiode may include a substrate including a major surface; a hedge formation extruding perpendicularly from the major surface; a first resettable region disposed on a top surface the hedge formation; a second resettable region disposed on the top surface of the hedge formation; a first doped region disposed on the top surface of the hedge formation between the first resettable region and the second resettable region, the first doped region including a first contact configured to receive a first voltage; and a second doped region disposed on a top surface of the hedge formation, the second doped region including a second contact configured to receive a second voltage. Exposed portions of the substrate form light absorbing regions configured to generate electron-hole pairs in the substrate.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 30, 2021
    Assignee: ACTLIGHT SA
    Inventors: Denis Sallin, Maxim Gureev, Serguei Okhonin
  • Patent number: 10950750
    Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 16, 2021
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ying Gao, Ling Zhou
  • Patent number: 10923349
    Abstract: According to one embodiment, a semiconductor element includes a first nitride semiconductor region, a second nitride semiconductor region, and an intermediate region provided between the first nitride semiconductor region and the second nitride semiconductor region. A Si concentration in the intermediate region is not less than 1×1018/cm3 and not more than 1×1019/cm3. A charge density in the intermediate region is 3×1017/cm3 or less.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 16, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Hikosaka, Jumpei Tajima, Shinya Nunoue
  • Patent number: 10916680
    Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: February 9, 2021
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ying Gao, Ling Zhou
  • Patent number: 10916918
    Abstract: An integrated photonic structure and a method of fabrication includes a substrate having at least one opening disposed therein; a semiconductor stack disposed above the substrate, the semiconductor stack being, at least in part, isolated from the substrate by an opening to define a suspended semiconductor membrane; and a first doped region and a second doped region located within the suspended semiconductor membrane. The first doped region is laterally separated from the second doped region by an optically active region disposed therein that defines a waveguiding region of the integrated photonic structure.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 9, 2021
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH Foundation, Inc.
    Inventors: Jeffrey Chiles, Sasan Fathpour
  • Patent number: 10892326
    Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
  • Patent number: 10879383
    Abstract: A high-electron-mobility field-effect transistor includes a superposition of first and second layers of semiconductor materials so as to form an electron gas layer and includes a gate stack arranged on the superposition. The gate stack includes a conductive electrode and an element made of p-doped semiconductor material, arranged between the conductive electrode and the superposition. The gate stack includes a first dielectric layer arranged between the conductive electrode and the element made of semiconductor material. The element made of semiconductor material, the first dielectric layer, and the conductive electrode have aligned lateral flanks.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Julien Buckley, Matthew Charles, Alphonse Torres
  • Patent number: 10877168
    Abstract: A radiation detector array (112) of an imaging system (100) comprises a plurality of detector modules (114). Each of the plurality of detector modules includes a plurality of detector pixel (116). Each of the plurality of detector pixels includes an integral pixel border (202, 204, 206, 208) and a direct conversion active area within the integral pixel border. A method comprises receiving radiation with a nano-material detector pixel that includes an integral pixel border, generating, with the detector pixel, a signal indicative of an energy of the received radiation, while reducing pixel signal crosstalk, and reconstructing the signal to construct an image.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: December 29, 2020
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventor: Marc Anthony Chappo
  • Patent number: 10878331
    Abstract: This invention concerns a method to switch on and off the exchange interaction J between electron spins bound to donor atoms. The electron spins have the role of ‘qubits’ to carry quantum information, and the exchange interaction J has the role of mediator for two-qubit quantum logic operations. The invention aims at exploiting the existence of a further magnetic interaction, the hyperfine interaction A, between each electron spin and the nuclear spin of the donor atom (301, 302) that binds the electron. The hyperfine interaction A, together with the ability to read out (504) and control the state of the nuclear spins, is used to suppress the effect of the exchange interaction J at all times, except while a quantum logic operation is being performed. In this way, the result of the quantum logic operation is not distorted after the operation has taken place.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 29, 2020
    Assignee: NewSouth Innovations Pty Limited
    Inventors: Andrea Morello, Rachpon Kalra, Arne Laucht
  • Patent number: 10862679
    Abstract: According to a first aspect of the present invention, therein is provided a method of determining or generating a unique identifier for a device, the device exhibiting quantum mechanical confinement, the method comprising: measuring a unique quantum mechanical effect of the device that results from the quantum mechanical confinement; and using the measurement to determine or generate the unique identifier.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 8, 2020
    Assignee: QUANTUM BASE LIMITED
    Inventors: Robert Young, Utz Roedig, Jonathan Roberts
  • Patent number: 10825947
    Abstract: A radiation detector comprises an antenna structure; and a field effect transistor structure having a source region, a gate region, and a drain region, arranged on a substrate and forming mutually independent electrically conductive electrode structures through metallization, wherein the gate electrode structure completely encloses the source electrode structure or the drain electrode structure in a first plane; the enclosed electrode structure extends up to above the gate electrode structure and there overlaps the enclosure in a second plane above the first plane at least in sections in a planar manner; wherein an electrically insulating region for forming a capacitor with a metal-insulator-metal structure is arranged between the regions of the gate electrode structure overlapped by the enclosed electrode structure.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: November 3, 2020
    Assignee: FORSCHUNGSVERBUND BERLIN E.V.
    Inventors: Adam Rämer, Sergey Shevchenko
  • Patent number: 10804383
    Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes disposed on a side face of a first insulating support and on a side face of a second insulating support, respectively; an island disposed between the first and second S/D electrodes and extending into an area between the first and second insulating supports. In some embodiments, a SET device may include: first and second S/D electrodes disposed on a substrate; an island disposed in an area between the first and second S/D electrodes; first and second portions of dielectric disposed between the island and the first and second S/D electrodes, respectively; and a third portion of dielectric disposed between the substrate and the island.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventor: Hubert C. George
  • Patent number: 10804399
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, Hubert C. George, James S. Clarke
  • Patent number: 10796965
    Abstract: A method for forming a nanodevice sensing chip includes forming nanodevices having a sensing region capable of producing localized Joule heating. Individual nanodevice is electrical-biased in a chemical vapor deposition (CVD) system or an atomic layer deposition (ALD) system enabling the sensing region of the nanodevice produce localized Joule heating and depositing sensing material only on this sensing region. A sensing chip is formed via nanodevices with sensing region of each nanodevice deposited various materials separately. The sensing chip is also functioned under device Joule self-heating to interact and detect the specific molecules.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 6, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ru-Zheng Lin, Jeng-Tzong Sheu
  • Patent number: 10790413
    Abstract: One embodiment comprises: a substrate; a first conductive semiconductor layer disposed on the substrate; a second conductive semiconductor layer disposed on the first conductive semiconductor layer; and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the first conductive semiconductor layer comprises a first area where a partial area of the first conductive semiconductor layer is exposed, and comprises an inclination part which is disposed between the upper surface of the first area and the upper surface of the second conductive semiconductor layer, wherein the inclination part comprises a first edge making contact with the upper surface of the second conductive semiconductor layer, and a second edge making contact with the upper surface of the first area of the first conductive semiconductor layer, wherein the ratio of a first length to a second length is 1:0.87 to 1:4.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 29, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Youn Joon Sung, Yong Gyeong Lee, Kwang Yong Choi
  • Patent number: 10790913
    Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 29, 2020
    Assignee: Omnisent, LLC
    Inventors: Joseph Eric Henningsen, Clifford Tureman Lewis
  • Patent number: 10784388
    Abstract: Photovoltaic cells are fabricated in which the compositions of the light-absorbing layer and the electron-accepting layer are selected such that at least one side of the junction between these two layers is substantially depleted of charge carriers, i.e., both free electrons and free holes, in the absence of solar illumination. In further aspects of the invention, the light-absorbing layer is comprised of dual-shell passivated quantum dots, each having a quantum dot core with surface anions, an inner shell containing cations to passivate the core surface anions, and an outer shell to passivate the inner shell anions and anions on the core surface.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 22, 2020
    Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Jiang Tang, Andras Pattantyus-Abraham, Illan Kramer, Aaron Barkhouse, Xihua Wang, Gerasimos Konstantatos, Ratan Debnath, Edward H. Sargent
  • Patent number: 10768485
    Abstract: Organically capped quantum dots are made by functionalizing the surfaces of QDs of various architectures with a combination of 6-mercaptohexanol (MCH) and 2-[2-(2-methoxyethoxy)-ethoxy]-acetic acid (MEEAA). Such MCH/MEEAA-capped QDs exhibit improved compatibility with solvents used in the fabrication of QD-containing films of light emitting devices, such as liquid crystal displays.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 8, 2020
    Assignee: Nanoco Technologies Ltd.
    Inventors: Nigel L. Pickett, James Harris, Margaret Hines, Joseph Taylor
  • Patent number: 10761266
    Abstract: A silicon-photonic integrated circuit comprising a direct-bandgap-semiconductor-based active optical device that is epitaxially grown on an indirect-bandgap SOI substrate (108) is disclosed. The structure of the active optical device includes an active region (120) having quantum dots (206) made of InGaAs that are embedded in one or more confinement layers (n-InP, p-InP), where the bandgap of the confinement layers is higher than that of the quantum dots. Further the confinement-layer material is preferably lattice matched to the quantum dot material in order to suppress associated crystalline defects within the material are located away from the center of its bandgap such that they suppress recombination-enhanced defect-reaction-driven degradation of the active optical device.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 1, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Alan Young Liu, Justin Norman, Arthur Gossard, John Bowers
  • Patent number: 10727370
    Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byunghoon Na, Changyoung Park, Yonghwa Park
  • Patent number: 10718491
    Abstract: A light source system or apparatus configured with an infrared illumination source includes a gallium and nitrogen containing laser diode based white light source. The light source system includes a first pathway configured to direct directional electromagnetic radiation from the gallium and nitrogen containing laser diode to a first wavelength converter and to output a white light emission. In some embodiments infrared emitting laser diodes are included to generate the infrared illumination. In some embodiments infrared emitting wavelength converter members are included to generate the infrared illumination. In some embodiments a second wavelength converter is optically excited by a UV or blue emitting gallium and nitrogen containing laser diode, a laser diode operating in the long wavelength visible spectrum such as a green laser diode or a red laser diode, by a near infrared emitting laser diode, by the white light emission produced by the first wavelength converter, or by some combination thereof.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 21, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Paul Rudy, Melvin McLaurin, Troy Trottier, Steven DenBaars
  • Patent number: 10714640
    Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 14, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Susumu Yoshimoto, Katsushi Akita
  • Patent number: 10697828
    Abstract: A multispectral optical sensor is disclosed. In one embodiment, the multispectral optical sensor includes a piezoelectric material, a first sensing layer and a second sensing layer spaced apart from each other on the piezoelectric material and configured to change the propagation speed of the acoustic wave propagated through the piezoelectric material by receiving ultraviolet light and visible light, respectively. The multiple optical sensor further includes a first acoustic wave output part and a second acoustic wave output part disposed on the piezoelectric material respectively corresponding to the first and second sensing layers and configured to generate an electrical signal based on the changed acoustic wave. The multiple optical sensor measures the intensity of ultraviolet and visible light using a single sensor by detecting the change in frequency, and measures the frequency change in the acoustic wave using zinc oxide, gallium nitride), or cadmium sulfide nanoparticles.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: June 30, 2020
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Kunnyun Kim, Yeon Hwa Kwak, Hae Kwan Oh
  • Patent number: 10692924
    Abstract: The present disclosure provides a scalable architecture for an advanced processing apparatus for performing quantum processing. The architecture is based on an all-silicon CMOS fabrication technology. Transistor-based control circuits, together with floating gates, are used to operate a two-dimensional array of qubits. The qubits are defined by the spin states of a single electron confined in a quantum dot.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: June 23, 2020
    Assignee: NewSouth Innovations Pty Limited
    Inventors: Andrew Dzurak, Menno Veldhorst, Chih-Hwan Henry Yang
  • Patent number: 10684497
    Abstract: An electro-optic modulator includes an input waveguide, a beam splitter connected to the input waveguide, a modulation arm that is disposed on each branch of the beam splitter and modulates a signal. Each modulation arm is correspondingly disposed with a first layer electrode and a second layer electrode. The first layer electrode is a high-frequency traveling wave electrode and is configured to change carrier concentration in the modulation arm, the second layer electrode is a direct current electrode having an inductor function, and an inductor formed in the second layer electrode is connected to the first layer electrode. The electro-optic modulator has functions of a bias tee, so that integration of the electro-optic modulator can be improved without affecting its performance. High-density packaging layout difficulty and cabling pressure can be effectively reduced, and cabling and packaging of a multi-channel high-speed signal on a base board can be implemented.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 16, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yanbo Li, Xiaolu Song, Zhen Dong, Ruiqiang Ji, Shengmeng Fu, Li Zeng
  • Patent number: 10671937
    Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 2, 2020
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Sheir Yarkoni, Trevor Michael Lanting, Kelly T. R. Boothby, Andrew Douglas King, Evgeny A. Andriyash, Mohammad H. Amin
  • Patent number: 10640703
    Abstract: An object of the present invention is to provide a semiconductor nanoparticle having high emission efficiency and excellent durability; a method of producing the same; and a dispersion liquid and a film obtained by using a semiconductor nanoparticle. The semiconductor nanoparticle of the present invention is a semiconductor nanoparticle in which oxygen, zinc, and sulfur are detected by X-ray photoelectron spectroscopy analysis and a peak (ICH3) which is derived from a hydrocarbon group and present in a range of 2800 cm?1 to 3000 cm?1 and a peak (ICOO) which is derived from COO? and present in a range of 1400 cm?1 to 1600 cm?1 are detected by Fourier transform infrared spectroscopy analysis.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 5, 2020
    Assignee: FUJIFILM Corporation
    Inventor: Tsutomu Sasaki
  • Patent number: 10637583
    Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: April 28, 2020
    Assignee: Omnisent, LLC
    Inventors: Joseph Eric Henningsen, Clifford Tureman Lewis
  • Patent number: 10614372
    Abstract: Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterization of the quantum by the coupler characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 7, 2020
    Assignee: Google LLC
    Inventors: Masoud Mohseni, Hartmut Neven