Abstract: The invention relates to a microelectronics and more particularly to a bipolar static induction transistor.

Abstract: A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors in the second basic cell has a second gate length larger than the first gate length. The transistors in the first basic cell are connected to each other, to construct a circuit which is operable at high speed and can be increased in integration density. The transistors in the second basic cell are connected to each other, to construct a circuit which can be reduced in power consumption and is hardly affected by process variations.

Abstract: In forming a photodiode by forming a burying layer on a charge accumulation region, the readout gate channel for the photodiode is separated from a high impurity concentration region of the burying layer of the photodiode, and at least a partial area of the high impurity concentration region is separated from the channel stopper region of the photodiode. Noises of a solid-state image pickup device using buried type photodiodes can be reduced.

Abstract: A CCD solid-state image sensing device has power supply lines formed from a poly-silicon layer and a silicide layer formed on the poly-silicon layer. The silicide layer has a reduced optical reflectivity that inhibits reflections of light on a surface of the power supply line. The silicide layer is silicon combined with a refractory metal, such as tungsten, molybdenum, titanium, or the like. Further, a surface protective film is formed on the power supply lines. The surface protective film includes silicon nitride having an increased quantity of hydrogen that is supplied to an interface between a channel layer and a diffusion layer in order to promote bonding.

Abstract: In a connection part of vertical transfer registers with respect to a horizontal transfer register, transfer electrodes to which clocks &phgr;V1, &phgr;V2A, &phgr;V3A, &phgr;V2B, &phgr;V3B, and &phgr;V1A are applied are arranged in the cited order. In a horizontal transfer register 6, transfer is conducted by 3-phase clocks &phgr;H1A, ØH1B, and &phgr;H2. By activating clocks, signal charges of a channel denoted by A-A′ and channels equivalent thereto are first transferred to undersides of electrodes of &phgr;H1A of the horizontal transfer register. The signal charges are transferred in the rightward direction to underside of electrodes of &phgr;H1B. Subsequently, signal charges of a channel denoted by B-B′ and channels equivalent thereto are transferred to undersides of electrodes of &phgr;H1B of the horizontal transfer register, and mixed with the signal charges previously transferred.

Abstract: A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port.

Abstract: A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.

Abstract: A bi-directional multi-tapped CCD sensor readout structure includes a well formed in a substrate, a channel formed in the well defining a channel direction, and a clocking structure disposed over the channel and oriented transversely to the channel direction. The clocking structure includes a plurality of register element sets. A first register element set includes a first floating sensing conductor and a plurality of clock signal conductors. The plurality of clock signal conductors includes a first clock signal conductor under which is defined a first junction at the electrical semiconductor junction between the well and the substrate and a second junction at the electrical semiconductor junction between the channel and the well. The first and second junctions define an inter-junction separation. The well is formed in the substrate and the channel is formed in the well so that a length of the inter-junction separation is controllable by a first clock signal applied to the first clock signal electrode.

Abstract: The invention relates to a charge-coupled device. Such devices comprise at least one insulated conducting gate (3) connecting two semiconductor zones. According to the invention, each insulated conducting gate (3) has a width progressively increasing from the first semiconductor zone (1) to the second semiconductor zone (2). The width of each gate (3) is sufficiently narrow for the potential well created by the application of a voltage V to the gate to have a depth increasing progressively from the first zone (1) to the second zone (2), thus enabling the charges to be driven away. The invention applies to any type of charge-coupled device and particularly to photodiodes.

Abstract: A color linear CCD for a pickup apparatus comprises a photodiode array including a blue-sensing photodiode array formed between a red-sensing photodiode array and a green-sensing photodiode array. A storage area is located beside of the red-sensing photodiode array for storing the signal charges produced by the red-sensing and blue-sensing photodiode arrays. A first HCCD shift register area is located beside of the green-sensing photodiode array for moving the signal charges produced by the green-sensing photodiode array. A second HCCD shift register area is formed beside of the storage area for alternately receiving the signal charges produced by the red-sensing and blue-sensing photodiode arrays. In another embodiment the red-sensing photodiode array is placed between the blue and green sensing photodiode arrays.

Abstract: A CCD area sensor comprising two horizontal transfer registers and a charge discharging section comprising a sweep-out electrode adjacent to the side of a horizontal register opposite to an image section and drain section, wherein the horizontal transfer register has a multi-channel structure comprising two transfer channels and a distribution electrode.

Abstract: The present invention intends to improve a difference between signal levels of odd-numbered pixels and even-numbered pixels in a CCD (charge coupled device) linear sensor. In a CCD linear sensor comprising a sensor region (1) having an array of a plurality of sensor elements (pixels) (S.sub.1), (S.sub.2), . . . and first and second horizontal transfer registers (4) and (5) disposed on the respective sides of the sensor region (1) through read-out gate sections (2) and (3) wherein signal charges of every other sensor elements (S.sub.1), (S.sub.3), (S.sub.5), . . . are transferred by the first horizontal transfer register (4) while signal charges of remaining every other sensor elements (S.sub.2), (S.sub.4), (S.sub.6) are transferred by the second horizontal transfer register (5), the first and second horizontal transfer registers (4) and (5) include first and second transfer electrodes (22R.sub.1), (22R.sub.2) to which two-phase drive pulses (.phi.H.sub.1) and (.phi.H.sub.

Abstract: A CCD sensor includes a readout register formed in substrate, the readout register including a channel, a bus structure and a connection structure. The bus structure includes plural spaced element sets, each element set including a first clock conductor. The first clock conductor of a first element set is a dual function conductor. The connection structure isolates the dual function conductor while coupling together the first clock conductor of each other set of the element sets. Alternatively, the sensor includes vertical and readout registers formed in a well in a substrate. The vertical register includes a vertical channel, a vertical bus structure and a vertical connection structure, and the readout register includes a readout channel, a readout bus structure and a readout connection structure. The readout bus structure includes plural spaced readout element sets, each readout element set including a first readout clock conductor.

Abstract: The present invention is directed to an improved CCD utilizing a potential gradient along the lengths of the various channels of the CCD during charge transfer to cause generated electrical charge to migrate along the length of the channel to a summing well. The potential gradient is formed by biasing the opposing ends of the electrodes overlying the lengths of the various channels with different voltages.

Abstract: A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: In a solid-state image pickup device having photoelectric converting sections, vertical charge transfer sections, and a horizontal charge transfer section, the vertical charge transfer sections include first, second, and third vertical charge transfer electrodes The third (final) vertical charge transfer electrode, which is adjacent to the horizontal charge transfer section, is electrically connected to a shunt wire (a first shading film) via lining contacts. A second shading film is formed electrically separated from the shunt wire, for light-shielding areas between photoelectric converting sections in a vertical direction.

Abstract: A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.

Abstract: A solid-state CCD image pick-up device includes optoelectric transducing elements corresponding to pixels vertically and horizontally arrayed in a matrix forming column linear arrays defining a column direction and at least one vertical charge transfer path associated with a corresponding adjacent column linear array. Pixel signals are vertically transferred from the column linear arrays to the vertical charge transfer paths such that gate signals occurring at predetermined times are applied to gate electrodes of the vertical charge transfer paths to permit the pixel signals to be scan read by a horizontal charge transfer path. Switching elements are provided for transfer gate electrodes and a drive circuit sequentially generates drive signals for groups of gate electrodes during periods in which the switching elements are rendered conductive to allow a full frame scan read to be performed by supplying a predetermined number of timing signals to the gate electrodes.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: This invention provides a method for manufacturing a this film transistor which comprised the steps of providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, the first channel layer, the second polysilicon laye

Abstract: An optical detector includes a charge-coupled device (CCD). The CCD comprises an active cell for receiving a narrow beam of incident illumination and generating photoelectrons in response thereto, and a first stage readout register comprising a row of N transfer cells, where N>1. A first stage gate structure transfers charge packets consecutively from the active cell into the first stage readout register, whereby N successive charge packets are read into the N cells respectively of the first stage readout register. N second stage readout registers each comprise M transfer cells, where M>1, and a second stage gate structure transfers N charge packets from the N cells of the first stage readout register into respective first cells of the second stage readout registers and subsequently shifts the N charge packets from the respective first cells of the second stage readout registers to respective Mth cells thereof.

Abstract: A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.

Abstract: A solid-state imaging device used as a linear sensor of the TDI mode in which resolution is improved and moire phenomenon takes place to less degree. This solid-state imaging device comprises first pixel trains comprised of plural pixels, second pixel trains comprised of plural pixels disposed in the state respectively shifted by half pitches in the horizontal and vertical directions with respect to the first pixel trains, a charge storage section for storing signal charges transferred to a signal processing section, first shift electrodes disposed between respective corresponding pixels of the first and second pixel trains and adapted for sequentially transferring signal charges, and second shift electrodes for transferring signal charges of the pixels of the final transfer stage of the first and second pixel trains to the charge transfer section through a shift register and an output circuit.

Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combinet for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: A fast-timing bi-directional charge coupled device ("CCD") is disclosed. The CCD operates at a much faster overall rate than conventional CCD's, while paradoxically slowing down the readout rate of the pixels. Lower power consumption is required, less heat is generated, thermal noise is lower, and digital noise is lower. The novel CCD is capable of 10-25 .mu.sec timing resolution (or even faster). The configuration entirely eliminates the (formerly) rate-determining step of transferring data "horizontally" from the "top" of the CCD columns. Instead, the charges on columns are transferred either "up" or "down" in an alternating manner. For example, the charges in odd-numbered columns might be transferred one row "up" with each clock cycle, and charges in even-numbered columns might be transferred "down." This alternating charge transfer architecture is termed "bi-directional.

Abstract: A charge transfer device has trapezoidal shape impurity-implanted regions (1, 51, . . . ) in n-type regions (271, 371) at least in the through-paths between a first HCCD (27) and a second HCCD (28), and its isolation regions (41) under the transfer gate (29) are trapezoidal shaped, and thereby charge transfer loss and hence FPN is minimized and the transfer efficiency is much improved.

Abstract: A solid-state image-sensor comprises a sensor, a charge transfer part, a plurality of charge/voltage converters, a comparator and a detector. The sensor has a plurality of arrayed light-receiving portions, with each light-receiving portion converting incident light into a signal charge corresponding to the amount of incident light and accumulating the signal charges. The charge transfer part distributes between at least two systems the signal charge stored at one light-receiving portion part of the sensor and transferring the signal charge using different numbers of stages. The plurality of charge/voltage converters detect and convert into voltages the signal charges of the at least two systems transferred by the charge transfer part. The comparator carries out a level conversion on each of the outputs of the plurality of charge/voltage converters and the detector detects the level transition point of the comparator output signal and generates a binary signal.

Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, congelated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g AI 17).

Abstract: A charge transfer device of two-line read structure is formed with a first charge transfer path for transferring first-group charges, a second charge transfer path for transferring second-group charges, and a transfer gate portion (106). To complete the transfer operation of all the second-group charges outputted at a time, the transfer operation of the charges from the first transfer path to the second charge transfer path by the transfer gate portion is divided into a plurality of times. In addition, the second-group charges outputted at time are transferred for each divided set of pixels in each divided transfer operation.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: A field effect transistor is disclosed. The field effect transistor includes: a semiconductor substrate having at least an upper face; a semiconductor layered structure, formed on the upper face of the semiconductor substrate, the semiconductor layered structure including a channel layer; a source electric formed on the semiconductor layered structure; a drain electrode formed on the semiconductor layered structure at a position apart from the source electrode in a first direction by a prescribed distance; and a gate electrode, formed on the semiconductor layered structure between the source electrode and the drain electrode.

Abstract: A single-output CCD image sensor selectively transfers a normal or a mirror image without changing the combination of clock signals needed by the HCCD. The CCD image sensor comprises VCCD's arrayed in each row, photodiodes connected to the VCCD's through transfer gates, and an upper HCCD connected to one end of the VCCD's. A rotating part for connecting one end of the upper and lower HCCD's as used for one of the normal or mirror image serial transfers. A control gate formed in parallel between the upper and the lower HCCD is used for the other of the normal or mirror image serial transfers, and operates in parallel. An output circuit is connected to the other end of the lower HCCD.

Abstract: A CCD comprises a sensing array and a readout register extending adjacent an edge of the sensing array. The readout register has first and second rows of transfer cells. The first row of transfer cells is between the sensing array and the second row. The transfer cells of the first row are of lower capacity than the transfer cells of the second row and are separated from the transfer cells of the second row by a potential barrier.

Abstract: The charge transfer device according to the present invention includes: a plurality of vertical transfer channels; a first transfer gate electrode placed at the ends of the plurality of vertical transfer channels for receiving signal charge from the plurality of vertical transfer channels and for outputting the signal charge; a plurality of horizontal transfer channels having a plurality of layers of gate electrodes for transferring the signal charge from the first transfer gate electrode in a horizontal direction; at least one second transfer gate electrode disposed between the plurality of horizontal transfer channels for transferring the signal charge from one of the horizontal transfer channels to another horizontal transfer channel; a conductive portion for supplying a transfer control signal to the plurality of horizontal transfer channels; at least one output section for converting the signal charge transferred from the plurality of horizontal transfer channels into a voltage signal and for outputting

Abstract: A MOS transistor for protection against electrostatic discharge includes a semiconductor substrate; an island including a source region and a drain region provided in the semiconductor substrate; an isolation region provided in the semiconductor substrate so as to surround the island; a gate insulating layer provided on the semiconductor substrate; a gate electrode provided on the gate insulating layer; and a distributing device for distributing an electric current generated by an electrostatic voltage applied to the drain region into the drain region.

Abstract: A charge transfer device is provided, which includes: a semiconductor substrate having transfer regions for transferring a signal charge; an insulating film formed on the semiconductor substrate; an electrode layer formed above the transfer regions with the insulating film sandwiched therebetween, the electrode layer having high-resistant portions and low-resistant portions alternately provided; and voltage application means for applying a voltage for changing a surface potential of the transfer regions to the low-resistant portions of the electrode layer.

Abstract: In charge coupled imaging devices, a major portion of the photosensitive surface area is covered by electrodes with which the charge storage and the charge transport in the semiconductor body are controlled. These electrodes are preferably made of polycrystalline silicon. This material, however, like other conductive materials known per se, has a comparatively high absorption coefficient, in particular in the short-wave portion of the visible spectrum (blue), which adversely affects the sensitivity. According to the invention, the electrodes are manufactured partly from a very thin poly layer, preferably not thicker than 50 nm, and partly from a less transparent but higher conductivity layer, for example, poly of much greater thickness.

Abstract: A convolver includes first and second buried channels, with each of the channels comprised of a piezoelectric semiconductor. The input of one channel is associated with the output of the other channel. An acoustic transducer is positioned adjacent each input for generating an acoustic wave which propagates through the associated channels and thereby transports charge from the input to the output thereof. A non-destructive sensing array overlies the channels and samples the charge transported thereunder. The array includes an assembly for summing the sampled charge and for generating a product. An electrode is operably associated with the summing assembly for integrating the products and generating a convolution signal.

Abstract: A solid-state imaging device comprises a plurality of photoelectric conversion accumulation sections arranged two-dimensionally on a semiconductor substrate, a plurality of vertical CCDs for vertically transferring signal charges read out from the photoelectric conversion accumulation sections, and a horizontal CCD for receiving and horizontally transferring the signal charges transferred by the vertical CCDs. A gap between transfer electrodes of the horizontal CCD is less than a gap between transfer electrodes of the vertical CCDs. The transfer electrodes of the vertical CCDs have a single-layer electrode structure formed by patterning a first polysilicon film. The transfer electrodes of the horizontal CCD have an overlapping double-layer electrode structure comprising alternately arranged electrodes formed by patterning the first polysilicon film and electrodes intervening between the alternately arranged electrodes which are formed by patterning a second polysilicon film.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: A complementary acoustic charge transport circuit element comprises first and second buried channels. Each of the channels is comprised of a piezoelectric semiconductor and each channel has a source through which charge is injected and a drain through which charge is extracted. A transducer propagates an acoustic wave through each channel and the propagated waves transport the charge between the sources and the drains. A source and/or a drain of one channel is connected in parallel with the corresponding souce and/or drain of the other channel. The waves are complementary at the interconnected ones of the sources and/or the drains.

Abstract: A solid-state imaging device includes a semiconductor substrate, an array of cells on the substrate, a plurality of vertical charge transfer sections extending in a first direction on the substrate, and a horizontal charge transfer section extending in a second direction transverse to the first direction on the substrate and being coupled to the vertical charge transfer section. The cell array includes a plurality of columns of cells that are associated with a corresponding one of the vertical transfer sections. The cell columns include a predetermined number of spaced-part cells that are series-connected along the second direction to constitute a NAND type cell structure. At least one cell-to-cell charge transfer electrode overlies a channel region as defined between adjacent ones of the NAND cells in the substrate.

Abstract: Solid-state image sensing device is provided with a synthesizing section for synthesizing odd-field signal charges and even-field signal charges. The synthesizing section is a transfer path formed outside of the photosensitive region or vertical transfer paths formed in the photosensitive region. For the signal charge synthesis through vertical transfer path, after the integration, the signal charges are read simultaneously from the odd-line pixel group and the even-line pixel group. Further, it is possible to select either the method of outputting the odd-field signal charges and the even-field signal charges separately or the method of outputting the synthesized odd- and even-field signal charges.

Abstract: A solid state imager device comprises a plurality of pixels arranged in rows and columns, each of the pixels consisting of a light sensing element and a vertical transfer portion adjacent to the light sensing element, the vertical transfer portion having three gate portions such as a first, a second and a third gate portions insulated each other, the third gate portion located in the center of the three gate portions, a plurality of rows of base portions disposed in the horizontal direction and connecting the respective gate portions, a vertical wiring device disposed over the gate portions through an insulating layer, the vertical wiring device including, a first wiring film connecting the first gate portions, a second wiring film connecting the second gate portions, a third wiring film connecting the third gate portions which is connected to the odd row of the base portions, a fourth wiring film connecting the third gate portions which is connected to the even rows of the base portions, a read out pulse dev

Abstract: A solid-state imaging device which can generate finite difference data of images at different times. There are provided with photoelectrical converting sections each of which includes photodiodes disposed in a matrix array and receives incident light to generate signal charges. A signal charge difference generating section generates a signal charge difference at different times from the signal charges generated in the photoelectrical converting section. A signal charge difference transfer section transfers the signal charge difference generated as an output of the device.

Abstract: A CCD filter according to the present invention can provide good comb-shaped characteristics with no adjustments, and can be produced at low cost. The input section 15 of a first CCD 11 is constructed so that it can linearly reduce transferred charges when an input voltage increases. The input section 17 of a second CCD 12 is constructed so that it can linearly increase transferred charges when the input voltage increases. The transferred charges of the first and second CCDs 11 and 12 are added to each other by means of charge adder section 13, and the addition result is output from an output section 14.

Abstract: A charge-coupled device has a series register (A) having charge storage electrodes (3a) for defining charge storage wells and charge transfer electrodes (3b) for transporting charge between the charge storage wells and a parallel section (C) having channels (1a,1b) extending transversely of the series register (A). The parallel section (C) has charge storage electrodes (11a,12a,13a . . . Na) spaced apart along the channels, (1a,1b) to define a respective charge storage well with each channel to provide a respective row of charge storage wells extending transversely of the channels and has charge transfer electrodes (12b . . . Nb) for transferring charge between adjacent rows of charge storage wells, and a transfer gate (T1) for transferring charge between the series register (A) and an adjacent row of charge storage wells defined by the channels (1a,1b) and a first charge storage electrode (11a) of the parallel section.

Abstract: A CCD which is designed and processed so that most of each pixel is covered only with an ultra-thin gate electrode so that the CCD can be frontside illuminated and still achieve good sensitivity in the ultra-violet and soft x-ray spectral range. More specifically, in the present invention, the usual three gate structure and corresponding polysilicon layers 1, 2 and 3 of conventional thickness are reduced in width and supplemented by a fourth ultra-thin layer of polysilicon dubbed herein, poly 4, that is deposited over the entire array. This fourth layer, poly 4, makes contact with poly 3, so that when poly 3 is driven, it also drives poly 4, thus allowing charge to collect and transfer as in a normal three phase CCD. However, because the deposition thickness of the poly 4 layer is on the order of 400 Angsttoms, as opposed to conventional thicknesses of 2000 to 5000 Angsttoms, poly 4 is essentially transparent to photons and thereby allows achievement of high quantum efficiency.