Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

Abstract: A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a second spacer simultaneously formed with a first spacer upon the sidewalls of a gate structure. The second spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the second spacer limits source and drain punch through to the SRB layer underneath a channel. An etch partially removes a SRB layer portion 24 within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The second spacer is formed by depositing spacer material with the fin void.

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract: In a solid-state imaging device 1, an overflow gate (OFG) 5 has a predetermined electric resistance value, while voltage application units 161 to 165 are electrically connected to the OFG 5 at connecting parts 171 to 175. Therefore, when voltage values V1 to V5 applied to the connecting parts 171 to 175 by the voltage application units 161 to 165 are adjusted, the OFG 5 can yield higher and lower voltage values in its earlier and later stage parts, respectively. As a result, the barrier level (potential) becomes lower and higher in the earlier and later stage parts, so that all the electric charges generated in an earlier stage side region of photoelectric conversion units 2 can be caused to flow out to an overflow drain (OFD) 4, whereby only the electric charges generated in a later stage side region of the photoelectric conversion units 2 can be TDI-transferred.

Abstract: A method for manufacturing an array substrate for producing an amorphous silicon (a-Si) array substrate of a low-definition OLED display is provided. The method includes: patterning a gate metal and a pixel electrode on a glass substrate by using a first mask which is a first half tone mask; patterning a gate insulation layer and a semiconductor layer on the glass substrate with a second mask which is a second half tone mask; forming source/drain metallic layers and a channel with a third mask; and forming a bank layer with a fourth mask. The a-Si array substrates of low-definition OLED display panels undertake less manufacturing processes, which means that mask plates are used less and cost is reduced.

Abstract: Methods for forming a magnetic tunnel junction (MTJ) storage element and MTJ storage elements formed are disclosed. The MTJ storage element includes a MTJ stack having a pinned layer stack, a barrier layer and a free layer. An adjusting layer is formed on the free layer, such that the free layer is protected from process related damages. A top electrode is formed on the adjusting layer and the adjusting layer and the free layer are etched utilizing the top electrode as a mask. A spacer layer is then formed, encapsulating the top electrode, the adjusting layer and the free layer. The spacer layer and the remaining portions of the MTJ stack are etched. A protective covering layer is deposited over the spacer layer and the MTJ stack.

Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.

Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.

Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

Abstract: A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts. In the semiconductor device, the first oxide semiconductor film, the second oxide semiconductor film, and the oxide film are each formed using a IGZO film, where the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film, the first oxide semiconductor film has a higher indium content than the oxide film, the oxide film has a higher gallium content than the first oxide semiconductor film, and the first oxide semiconductor film has a higher gallium content than the second oxide semiconductor film.

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.

Abstract: A phase change memory device includes a silicon substrate including a plurality of active regions which extend in a first direction and are arranged at regular intervals in a second direction perpendicular to the first direction. Switching elements are formed in each active region of the silicon substrate and are spaced apart from one another. Phase change patterns are formed in the second direction and have the shape of lines in such that the phase change patterns connect side surfaces of pairs of switching elements which are placed adjacent to each other in a direction diagonal to the first direction.

Abstract: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.

Abstract: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

Abstract: To eliminate uneven distribution of electrons caused by variation in threshold voltages of gates for distributing electrons and to have sensitivity in a long wavelength in a pixel structure of a solid-state image sensor of a charge sorting method, the structure has: a photodiode that generates electrons by photoelectric conversion; a plurality of charge-storage sections that store electrons generated in the photodiode; and a gate structure that is arranged between the photodiode and the charge-storage sections and controls transfer of electrons generated in the photodiode to the plurality of charge-storage sections, in which the gate structure is made up of plural stages of gates, and the plural stages of gates at least have: a front stage gate that is arranged adjacent to the photodiode and controls readout of electrons generated in the photodiode; and a rear stage gate that is arranged adjacent to the plurality of charge-storage sections on the rear stage of the front stage gate and performs control of dist

Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.

Abstract: A phase-changeable memory device includes a substrate having a field effect transistor therein and a phase-changeable material electrically coupled to a source region of the field effect transistor. The phase-changeable material includes a chalcogenide composition containing at least germanium, bismuth and tellurium and at least one dopant selected from a group consisting of nitrogen and silicon.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.

Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

Abstract: An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process. Each pixel is formed of at least one charge well of minority carriers and a gate oxide layer overlaying the at least one charge well. At least two spaced gate electrodes corresponding in position to the at least two charge wells overlays the gate oxide layer. The space between adjacent electrodes defines a gap to transfer charge between adjacent ones of at the least two spaced gate electrodes and the gap is stabilized. A back-illuminated imager is also described in which photocarriers are diverted from devices integrated with the pixel by a PN junction formed in the pixel structure.

Abstract: An imaging device capable of multiplying carriers and miniaturizing the device is obtained. The imaging device includes a carrier storage portion for storing carriers generated by photoelectric conversion, having a photoelectric conversion function, a multiplier section including a multiplier electrode applying an electric field for multiplying carriers due to impact ionization by an electric field, one first transfer electrode so provided between the carrier storage portion and the multiplier electrode as to be adjacent to the carrier storage portion and the multiplier electrode.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that includes nitrogen atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystalline structure.

Abstract: A charge-coupled device capable of attaining excellent performance with a single-layer gate electrode structure is obtained. This charge-coupled device, having a single-layer gate electrode structure, comprises a gate insulator film formed on a semiconductor substrate, a plurality of partitions, consisting of an insulator, formed on the gate insulator film, and concave gate electrodes, arranged between adjacent ones of the partitions, having side surfaces formed along side portions of the partitions. Thus, when the partitions are formed with a width of not more than the minimum critical dimension of lithography, the interval between the adjacent gate electrodes is not more than the minimum critical dimension of lithography.

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract: There is provided a semiconductor device comprising a gate electrode which is formed on a semiconductor substrate through a gate insulating film and in which a plurality hexagonal rings are mutually connected so as to form a honeycomb structure, drain diffusion layers each formed in the semiconductor substrate on the inside of one hexagonal ring, source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein, and, insulating layers formed between respective source diffusion layers in the semiconductor substrate.

Abstract: A method of fabricating an X-ray detecting device that is capable of preventing breakage of a transparent electrode. In the method, patterning of first and second insulating films occurs at different etching rates, with an etching ratio of the second insulating material to the first insulating material being greater than 1. Accordingly, undercut of the first and second insulating materials can be prevented. This stabilizes the step coverage of a subsequently formed transparent electrode.

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh

Abstract: A charge carrier multiplier is disclosed in which a carrier that passes through a high-field region lying entirely within the depleted semiconductor volume causes a single-step impact ionization without avalanching. By spacing the high-field region sufficiently away from any substrate region that is not depleted of carriers of opposite polarity than the ionizing carrier, generation of unwanted spurious charge is minimized. Preferably the cell includes a depleted channel formed in a substrate, a gate structure insulatively disposed over and transverse to the channel having an aperture formed therein, and a charge multiplication gate electrode insulatively disposed over the aperture. In one embodiment, the gate electrode structure includes a first aperture gate electrode having the aperture formed therethrough, and in another embodiment, the gate electrode structure includes first and second aperture gate electrodes having respective first and second reticulations therein so as to frame the aperture.

Abstract: The image sensing device includes an image sensing area 22 having an antiblooming drain structure; and a frame memory area 24 coupled to the image sensing area 22 for storing charge from the image sensing area, wherein during charge integration, the antiblooming drain is biased at a first level, and during charge transfer to memory, the antiblooming drain is biased at a second level such that the image sensing area 22 will have a higher charge capacity than during the charge integration.

Abstract: A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.

Abstract: A bidirectional horizontal charge transfer device and method includes a charge transfer area formed within a substrate, a plurality of first, second, third and fourth poly gates formed over the charge transfer area,an insulating layer formed between the first, second, third and fourth poly gates, a first clock signal applied to the first and second poly gates, a second clock signal applied to the third and fourth poly gates, and a biasing circuit for selectively applying a bias signal to the first and second clock signals so as to selectively change a charge transfer direction.

Abstract: A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.

Abstract: The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.

Abstract: An interline sensor is constructed using photocapacitors. The vertical shift register of the interline sensor is operated in a uniphase mode, i.e., holding one of the two phase (.O slashed.2) at a D.C. potential while fluctuating the other phase (.O slashed.1) between a voltage that is sufficiently above and below that D.C. potential to facilitate transfer of charge from one phase to the next. The uniphase mode is facilitated by a single electrode that covers both the phase that is held at a constant D.C. potential and the photodetector having photocapacitor charges. The single electrode in the preferred embodiment is an indium tin oxide electrode. The charges are transferred from the photocapacitors to the vertical shift register by a third level clock into .O slashed.1 adjacent the photodetectors.It is also proposed that the same ITO electrode be utilized to for phase 2 of both the vertical and horizontal CCD shift registers.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: The process tracking bias generator for antiblooming structures includes a lateral overflow antiblooming drain and bias circuitry coupled to the antiblooming drain for automatically adjusting a bias for the antiblooming drain independent of process variations.

Abstract: Disclosed is a charge transfer device which has charge transfer registers, a floating diffusion layer for receiving a signal charge transferred from the charge transfer registers, a reset circuit for extracting a signal charge transferred from the floating diffusion layer and resetting a potential of the floating diffusion layer periodically to a predetermined potential, and an output circuit of a source follower formed by a MOSFET having a gate connected to the floating diffusion layer and a load resistance connected to a source of the MOSFET. The load resistance includes a substrate of a first conductivity type, a diffusion layer of a second conductivity type which is provided on the substrate, and a carrier accumulation layer of the first conductivity type which is provided at the top surface of the diffusion layer.

Abstract: The lateral overflow drain for virtual phase devices includes: a semiconductor region 72 of a first conductivity type; a drain region 24 of the first conductivity type formed in the semiconductor region 72; a threshold adjust region 22 formed in the semiconductor region 72 and surrounding the drain region 24; an electrode 20 overlying and connected to the drain region 24, the electrode 20 overlying and separated from at least a portion of the threshold adjust region 22; and virtual gates 30 and 32 of the second conductivity type in the semiconductor region 72 spaced apart from the drain region 24 and partially surrounding the drain region 24.

Abstract: In charge coupled imaging devices, a major portion of the photosensitive surface area is covered by electrodes with which the charge storage and the charge transport in the semiconductor body are controlled. These electrodes are preferably made of polycrystalline silicon. This material, however, like other conductive materials known per se, has a comparatively high absorption coefficient, in particular in the short-wave portion of the visible spectrum (blue), which adversely affects the sensitivity. According to the invention, the electrodes are manufactured partly from a very thin poly layer, preferably not thicker than 50 nm, and partly from a less transparent but higher conductivity layer, for example, poly of much greater thickness.

Abstract: A solid state imaging device which reduces the occurrence of crosstalk between a plurality of picture elements arranged in a linear or matrix form. The solid state imaging device includes a plurality of photosensitive cells formed on a first principal surface of a semiconductor substrate, a transfer electrode formed in a gap area among the cells on the first principal surface to read out charges produced in the cells, a drive metal wiring formed on the transfer electrode within the gap area, a first insulating film covering the cells with a predetermined thickness, and a plurality of metal reflecting films formed on the first insulating film in such a manner that the whole surface of each of the metal reflecting films forms a reflecting surface substantially parallel to a surface of each of the cells on the side of the first principal surface whereby light passed through the photosensitive cells from a side opposite to the first principal surface is reflected back to each of the photosensitive cells.

Abstract: An image sensing device with electronic shutter having a semiconductor substrate of a first conductivity type and a buried channel layer of a second conductivity type disposed on the substrate. Virtual phase electrodes in the buried channel layer having the first conductivity type form virtual gate potential areas in the substrate below the virtual phase electrodes. An insulating layer is formed on the substrate. Conductive electrodes disposed on the insulating layer and located over portions of the substrate between the virtual phase electrodes form clocked gate potential areas in the substrate below the conductive electrodes. The virtual gate potential areas and the clocked gate potential areas form charge transfer columns along which charge can be transferred to an end of the charge transfer column.

Abstract: Logically and thermodynamically reversible charge transfer (RCT) devices and logic are provided for conditionally transferring individually identifiable charge packets from one or more sources to one or more destinations under the control of one or more additional charge packets that indicate by their presence or absence whether the condition or conditions have been satisfied or not. The individual identities of all of these charge packets are substantially preserved while logic operations are being performed by this logic.

Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.

Abstract: A virtual phase image sensor has majority carriers supplied to a virtual gate 24 by a conductor 32 overlying the image sensor, the virtual gate 24 and the conductor 32 each in contact with a conductive channel stop region 30.

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh