Abstract: A variable resistance nonvolatile storage device includes: a variable resistance element having a state reversibly changeable between a high resistance state and a low resistance state; and a current supply circuit that supplies the variable resistance element with a low-resistance changing current for changing the state from the high resistance state to the low resistance state. The low-resistance changing current has a waveform that includes a first period and a second period along a time axis, the second period being subsequent to the first period. The current supply circuit applies to the variable resistance element: a first current during the first period; and a second current during the second period, the second current being smaller than the first current. The first current is not zero at an end of the first period, and the second current is not zero at a start of the second period.

Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: In some embodiments, the present disclosure relates a phase change random access memory device that includes a phase change material (PCM) layer disposed between bottom and top electrodes. A controller circuit is coupled to the bottom and top electrodes and is configured to perform a first reset operation by applying a signal at a first amplitude across the PCM layer for a first time period and decreasing the signal from the first amplitude to a second amplitude for a second time period; and to perform a second reset operation by applying the signal at a third amplitude across the PCM layer for a third time period and decreasing the signal from the third amplitude to a fourth amplitude for a fourth time period greater than the second time period. After the fourth time period, the PCM layer has a percent crystallinity greater than the PCM layer after the second time period.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a first fin and a second fin over a substrate, and conformally forming a silicon oxide layer over the first fin using a first atomic layer deposition (ALD) process. The method also includes conformally forming a silicon nitride layer over the silicon oxide layer using a second ALD process, and forming an insulating layer to fill the trench between the first fin and the second fin over the substrate. The method further includes recessing the insulating layer, the silicon oxide layer, and the silicon nitride layer to form an isolation structure with a liner. In addition, the method includes forming a gate structure over the first fin, and forming a source region and a drain region in the first fin and on opposite sides of the gate structure.

Abstract: An electro-mechanical miniaturized device for pressure measurements is described, the device comprising at least one first electro-mechanical miniaturized pressure sensor member, configured to detect a respective first pressure value P1 and to generate a first electrical signal S1 representative of the first pressure value P1, and further comprising at least one second electro-mechanical miniaturized pressure sensor member, configured to detect a respective second pressure value P2 and to generate a second electrical signal S2 representative of said second pressure value P2. The second sensor member is arranged within a casing suitable to seal it. The device further comprises electronic processing means, operatively connected to the first and the second sensor members, and configured to determine a measured pressure value P based on said first S1 and second S2 electrical signals.

Abstract: A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.

Abstract: According to an embodiment, a noise removing device includes a first difference detector and a second difference detector. The first difference detector detects a difference between a first reset signal at a first timing and a second reset signal at a second timing after a predetermined period of time has elapsed from the first timing. The second difference detector subtracts the difference detected by the first difference detector from a main signal between the first reset signal and the second reset signal, and outputs a subtraction result.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: Provided is a device adapted for detecting chemical and physical phenomena and suitable for high integration, and a method for controlling the detection device. When a plurality of pH-detecting devices are used, a variation in sensitivity occurs in each of the sensing units. The variation in sensitivity can be calibrated using a simple method. The amount of charge (output signal) delivered by each of the sensing units to a standard solution is determined, and the difference between the delivered charge amount and a standard charge amount (standard output signal) delivered by a standard sensing unit is determined. The capacity of the potential well of the sensing unit is changed, or the potential of a TG unit when a charge is delivered is changed, so as to cancel out the difference.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, a top electrode layer disposed on the phase-change material layer, and a barrier film comprising a group IV transition metal, a group VI transition metal, carbon (C) and nitrogen (N), the barrier film being disposed between the bottom electrode layer and the top electrode layer. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

Abstract: Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.

Abstract: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A charge-coupled unit formed in a semiconductor substrate and including an array of identical electrodes forming rows and columns, wherein: each electrode extends in a cavity with insulated walls formed of a groove, oriented along a row, dug into the substrate thickness, and including, at one of its ends, a protrusion extending towards at least one adjacent row.

Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.

Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes forming rows and columns, wherein: the electrodes extend, in rows, in successive grooves with insulated walls, disposed in the substrate thickness and parallel to the charge transfer direction.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row.

Abstract: A new photovoltaic (PV) cell structure, prepared on transparent substrate with transparent conductive oxide (TCO) layer and having nanorod zinc oxide layer. The cell has a thin conductive layer of doped zinc oxide deposited on the nanorod zinc oxide layer, an extremely thin blocking layer of titanium oxide or indium sulfide on the thin conductive layer, a buffer layer of indium sulfide on the extremely thin blocking layer, an absorber layer, comprising copper indium disulfide on said buffer layer and one electrode attached to the transparent conductive oxide layer and a second electrode attached to the absorber layer. Also, a method of preparing a zinc oxide nanorod PV cell entirely by chemical spray pyrolysis is disclosed. Efficiency up to 3.9% is achieved by simple continuous non-vacuum process.

Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.

Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Abstract: A solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area ratio higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.

Abstract: A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.

Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

Abstract: The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.

Abstract: A solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, and a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion. The solid-state image pickup element also includes a first-conductive type high-concentration impurity-doped element isolation region, a second-conductive type photoelectric conversion region, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region.

Abstract: A phase change memory device includes a silicon substrate including a plurality of active regions which extend in a first direction and are arranged at regular intervals in a second direction perpendicular to the first direction. Switching elements are formed in each active region of the silicon substrate and are spaced apart from one another. Phase change patterns are formed in the second direction and have the shape of lines in such that the phase change patterns connect side surfaces of pairs of switching elements which are placed adjacent to each other in a direction diagonal to the first direction.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a light-receiving area. The solid-state image pickup element comprises a p-type planar semiconductor, a hole formed in the p-type planar semiconductor, a p+-type region formed in a bottom of the hole, a p+-type isolation region formed in a part of a sidewall of the hole and connected to the p+-type region, an n-type photoelectric conversion region formed beneath the p+-type region, a transfer electrode formed on the entire sidewall of the hole through a gate dielectric film, a CCD channel region formed in a top of the p-type planar semiconductor, and a read channel formed in a region of the p-type planar semiconductor between the n-type photoelectric conversion region and the CCD channel region.

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract: A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.

Abstract: A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater includes a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.

Abstract: An electro-optic device includes a semiconducting layer in which is formed a waveguide, a modulator formed across the waveguide comprising a p-doped region to one side and an n-doped region to the other side of the waveguide, wherein at least one of the doped regions extends from the base of a recess formed in the semiconducting layer. In this way, the doped regions can extend further into the semiconducting layer and further hinder escape of charge carriers without the need to increase the diffusion distance of the dopant and incur an additional thermal burden on the device. In an SOI device, the doped region can extend to the insulating layer. Ideally, both the p and n-doped regions extend from the base of a recess, but this may be unnecessary in some designs. Insulating layers can be used to ensure that dopant extends from the base of the recess only, giving a more clearly defined doped region.

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract: A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.

Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.

Abstract: A phase-changeable memory device includes a substrate having a field effect transistor therein and a phase-changeable material electrically coupled to a source region of the field effect transistor. The phase-changeable material includes a chalcogenide composition containing at least germanium, bismuth and tellurium and at least one dopant selected from a group consisting of nitrogen and silicon.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.

Abstract: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5?x?1.5, 0.5?y?2.5 and 1.5?z?4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

Abstract: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings connecting bit lines to the read/write circuit; and third vertical wirings connecting word lines to the read/write circuit, wherein the memory cell includes a variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.

Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.