Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.

Abstract: A physical layout of a symmetric FET is described which provides symmetry in voltages coupled to structures of the FET so to reduce OFF state asymmetry in capacitances generated by the structures when the FET is used as a switch. According to one aspect, the symmetric FET is divided into two halves that are electrically coupled in parallel. Gate structures of the two half FETs are arranged in the middle region of the layout, each gate structure having gate fingers that project towards opposite directions. Interdigitated source and drain structures run along the gate fingers and include crossover structures that cross source and drain structures in the middle region of the layout. The gate structures share a body contact region that is arranged in the middle of the layout between the two gate structures.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: A lateral junction field-effect transistor includes a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a third dopant concentration, the third semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the thi

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: An apparatus includes a package, a wall and a lid. The package may be configured to mount two chips configured to generate one or more signals in a millimeter-wave frequency range. The wall may be formed between the two chips. The wall generally has a plurality of conductive arches that attenuate an electromagnetic coupling between the two chips in the millimeter-wave frequency range. The lid may be configured to enclose the chips to form a cavity.

Abstract: An apparatus having a package, a wall and a lid is disclosed. The package may be configured to mount a plurality of chips. Two of the chips may generate a plurality of signals in a millimeter-wave frequency range. A metal is exposed at a surface of the package between the two chips. The metal is generally connected to an electrical ground. The wall may be formed on the metal and between the two chips. The wall generally has a plurality of arches that (i) are conductive, (ii) are wire bonded to the metal and (iii) attenuate an electromagnetic coupling between the two chips at the millimeter-wave frequency. The lid may be configured to enclose the chips to form a millimeter-wave cavity.

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract: A semiconductor device includes an oxide semiconductor layer provided over a substrate having an insulating surface; a gate insulating film covering the oxide semiconductor layer; a first conductive layer and a second conductive layer laminated in this order over the gate insulating film; an insulating film covering the oxide semiconductor layer and a gate wiring including a gate electrode (the first and second conductive layers); and a third conductive layer and a fourth conductive layer laminated in this order over the insulating film and electrically connected to the oxide semiconductor layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. A source electrode is formed using the third conductive layer. A source wiring is formed using the third conductive layer and the fourth conductive layer.

Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.

Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).

Abstract: A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.

Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.

Abstract: An integrated circuit connection comprises a substrate, first and second transmission lines, a die, and a conductive ribbon. The first transmission line has a first end and is arranged on the substrate. The die is spaced from the first end. The die has a first surface, which is arranged on the substrate, and a second surface, which is opposite to the first surface and which has the second transmission line arranged thereon. The second transmission line has a second end. The conductive ribbon electrically couples the first and the second ends.

Abstract: Apparatuses capable of and techniques for detecting long wavelength radiation are provided.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.

Abstract: Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

Abstract: A switch device using a frequency control device having an improved isolation feature is provided. The switch device may include a transmission line comprising an input terminal and an output terminal, and a frequency control device to switch a frequency input to the input terminal so that the frequency is selectively transferred to the output terminal. The transmission line may be formed in the form of an air bridge, in an upper portion of the frequency control device.

Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts.

Abstract: A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.

Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.

Abstract: An image sensor and a method for manufacturing the same are disclosed. The image sensor can include a semiconductor substrate that includes photodiodes arranged for each unit pixel; an interlayer dielectric layer and metal wirings disposed on the semiconductor substrate; and a photorefractive unit that is formed on the periphery of an optical path incident on the photodiodes. The photorefractive unit has a lower refractive index than the interlayer dielectric layer. The slantly incident light can be incident on the photodiodes, while maintaining the slanted optical path as it is. The light sensitivity of the photodiodes can be improved, thereby improving image quality.

Abstract: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

Abstract: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.

Abstract: A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic, state and a low resistance when in a ferromagnetic state. The tunnel barrier is switchable between the non-ferromagnetic and the ferromagnetic states.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: An object of the present invention is to provide a small solid-state image sensor which realizes significant improvement in sensitivity. The solid-state image sensor of the present invention includes a semiconductor substrate in which photoelectric conversion units are formed, a light-blocking film which is formed above the semiconductor substrate and has apertures formed so as to be positioned above respective photoelectric conversion units, and a high refractive index layer formed in the apertures. Here, each aperture has a smaller aperture width than a maximum wavelength in a wavelength of light in a vacuum converted from a wavelength of the light entering the photoelectric conversion unit through the apertures, and the high refractive index is made of a high refractive index material having a refractive index which allows transmission of light having the maximum wavelength through the aperture.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.

Abstract: In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on an uppermost surface of the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on and uppermost surface of the drain toward the gate foot along the substrate.

Abstract: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region.

Abstract: An image pickup device is characterized by including a plurality of pixels having a plurality of photoelectric conversion units, convex interlayer lenses with respect to incident light, the convex interlayer lenses being arranged correspondingly to a photoelectric conversion devices and color filters being arranged for each color on the interlayer lenses correspondingly to the photoelectric conversion devices, wherein the color filter is formed to match the shape of the interlayer lens and the top surface thereof is substantially flat. This configuration reduces the amount of light which is incident on the gaps between adjacent microlenses and passes through the color filters at the boundary of pixels, decreasing color mixture of camera image.

Abstract: A circuit element for protecting a load circuit includes a signal input for applying a signal, a signal output, a signal path connecting the signal input to the signal output, and an interruption means for irreversibly interrupting the signal path upon the reception of a control signal at the same.

Abstract: A solid-state image pickup element comprises: a semiconductor substrate; an imaging section comprising a photoelectric converting portion, formed on the semiconductor substrate; an intralayer lens formed in an upper layer of the imaging section; and a peripheral circuit section that processes an output of the imaging section, formed on the semiconductor substrate, wherein at least part of the intralayer lens is formed in a lower layer of a wiring portion in the peripheral circuit section.

Abstract: A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband.

Abstract: A light detecting element 1 including an element formation layer 22 which contains a well region 31. A surface electrode 25 is formed on the layer 22 through an insulating layer 24. The region 31 contains an electron holding region 32. The region 32 contains a hole holding region 33. The layer 24 contains a control electrode 26 facing the region 33 through the layer 24. Electrons and holes are generated at the layer 22. There are two selected states. In one state, by controlling each electric potential applied to the electrodes 25, 26, electrons are gathered at the region 32, while holes are held at the region 33. In another state, recombination is stimulated between the electrons and the holes. After the recombination, the remaining electrons are picked out as received light output.

Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.