Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

Abstract: Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.

Abstract: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area.

Abstract: A multi-finger transistor includes gate fingers disposed on a substrate, at least one gate wiring connected to end portions of the gate fingers, source regions and drain regions disposed between the gate fingers, a conductive line partially enclosing the gate fingers and the gate wiring, and substrate plugs electrically connecting the conductive line to the substrate. The conductive line is separated from the gate fingers and the gate wiring. Since the conductive line and the substrate plugs may partially, but not fully, enclose a portion of the substrate where the gate fingers and the gate wiring are positioned, parasitic capacitances caused by the conductive line and the substrate plugs may be considerably reduced to thereby allow high RF frequency characteristics of the multi-finger transistor.

Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.

Abstract: An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry. The removal of interconnecting diffusion region portions and gate electrode portions can be performed sequentially, at substantially the same time, and before or after forming source/drain contacts.

Abstract: A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The transmission line circuit includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: A data transmission system in which normal transmission can be performed irrespectively of the inserting orientation of a connector is provided. A transmitting device transmits to a receiving device a differential transmission signal including polarity decision data for deciding the polarity of the connector. Based on the polarity decision data included in the differential transmission signal transmitted from the transmitting device, the receiving device decides whether the polarity of the connector has been reversed or not. When it is decided that the polarity has not been reversed, the receiving device reads data from the differential transmission signal. When it is decided that the polarity has been reversed, the polarity of the differential transmission signal is reversed for data reading.

Abstract: Techniques that enable the transitioning of high frequency signals on a printed wiring board processed in accordance with industry standards (such as the IPC specifications) are disclosed. One embodiment provides a high frequency via structure for a printed wiring board, where the via structure includes a via pad configured in accordance with IPC standards. A printed microwave transmission line having an inductive section is connected to the via pad, wherein the inductive section has dimensions to compensate for transition discontinuity.

Abstract: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal 1 and the second input-output terminal.

Abstract: The present invention relates to a fuse-relay including a first pole (1, 11, 21, 31, 81) and a second pole (2, 12, 22, 32, 82). According to the invention the fuse-relay includes a resilient device (5, 18, 27, 37, 87) that is held in an elastically deformed position by a fuse (6, 16, 26, 36, 86) when the fuse (6, 16, 26, 36, 86) is whole; and in that the resilient device (5, 18, 27, 37, 87) is arranged to make or break a connection between the first pole (1, 11, 21, 31, 81) and the second pole (2, 12, 22, 32, 82) when the fuse (6, 16, 26, 36, 86) is blown. The invention also relates to a cross-connect with such fuse-relays, to a telecommunication system with such cross-connects and to a connection method.

Abstract: A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.

Abstract: The present invention relates to a semiconductor memory device including a fuse box wherein the layout of a fuse box used to control a memory cell array is improved, a fuse box is divided into a plurality of blocks, and an index mark is applied to every fuse box or to every block so that a user may recognize each fuse box. In an embodiment, there is provided a semiconductor memory device including a fuse box comprising a plurality of cell matrices and a fuse box. The plurality of cell matrices are arranged adjacently each other. The fuse box is defined by a fuse barrier layer formed at a side of the plurality of cell matrices, wherein the fuse box comprises a plurality of cell matrices, wherein the fuse box comprises a plurality of fuses shared by the plurality of cell matrices, and the fuse barrier layer is configured to have a length long enough to be shared by the plurality of cell matrices.

Abstract: A manufacturing method for fabricating flash memory semiconductor devices is disclosed.

Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

Abstract: A monolithically formed ferromagnetic thin-film memory is disclosed that has local shielding on at least two sides of selected magnetic storage elements. The local shielding preferably extends along the back and side surfaces of a word line and/or digital lines of a conventional magnetic memory. In this configuration, the local shielding not only may help reduce externally generated EMI, internally generated cross-talk and other unwanted fields in the magnetic bit region, but may also help enhance the desired magnetic fields in the bit region.

Abstract: The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor memory cells are located in an active region formed in annular fashion and are driven via associated word lines. In this case, the source regions of the one-transistor memory cells are connected via a source line, while the drain regions are connected via corresponding drain lines. A reduced space requirement for the two-transistor semiconductor memory cell is obtained in particular on account of the annular structure of the active regions.

Abstract: A semiconductor integrated circuit device having an input buffer connected to an input terminal, includes: a transfer gate one node of which is connected to the input terminal and the other node to an internal circuit, the transfer gate being on in an ordinary state; a transmission line connected to the other node of the transfer gate; and a control circuit configured to detect level transition of an input signal on the input terminal and drive to turn off the transfer gate after the input signal is transferred through the transfer gate and before a lapse of while the input signal makes a round trip on the transmission line.

Abstract: A method of forming an active plate for a liquid crystal display is disclosed in which the source and drain conductors (28, 30), pixel electrodes (38) and column conductors (32) are formed by depositing and patterning a transparent conductor layer. There is selective plating of areas (52; 60) of the transparent conductor layer to form a metallic layer for reducing the resistivity of the transparent conductor layer. The plated areas include the column conductors (32) but exclude the source and drain conductors and the pixel electrodes. This enables the column conductors to be treated to reduce the resistivity, but without altering the channel length of the transistor because the source and drain parts of the layer are shielded from the plating process.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: An electronic package component includes a flip-chip device mounted to a BGA substrate. The BGA substrate includes conductive traces formed on its upper surface and configured in a coplanar waveguide structure. The package includes a dielectric coating applied over the conductive traces and over the upper surface of the substrate. The coating is formed from a material having a dielectric constant that is equal to or approximately equal to the dielectric constant of the BGA substrate material. The dielectric coating reduces the adverse effects caused by phase velocity dispersion of the signal propagated by the coplanar waveguide.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: In a high frequency semiconductor device, a shield plate which is connected to the ground potential is provided above an MMIC structure including line conductors, with an insulating interlayer provided therebetween. By using the shield plate to shield the MMIC, interference caused by external electromagnetic waves or leakage of electromagnetic waves to the exterior can be reduced in a chip alone.

Abstract: An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Abstract: An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.

Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A traveling wave FET in which increasing distances between electrodes and the design of semiconductor regions associated with the various electrodes act to increase maximum gain parameters of the device. The relationship of the electrode series resistance is also considered in the design as it affects these gain parameters.

Abstract: A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: In a semiconductor storage device, a line of lower-side backing wiring is provided on a line of gate wiring via an insulation layer, and a line of upper-side backing wiring is provided further on the top layer thereof via another insulation layer. Contacts between the gate wiring and upper-side backing wiring are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the gate wiring extends, and any contacts adjacent to each other of the contacts are arranged on different lines. The lower-side backing wiring passes through between the adjacent contacts.

Abstract: A semiconductor integrated circuit device includes a plurality of internal circuits formed in a circuit forming region; a plurality of power lines separately connected to the internal circuits; a signal wire routed between the internal circuits; and a protection circuit connected to the power lines, the protection circuit including a parallel circuit having a first rectifying element formed in a p-type semiconductor region and a second rectifying element formed in an n-type semiconductor region.

Abstract: A microwave device, including a substrate having a first surface and a second surface, a plurality of electrically conductive vias extending through the substrate from the first surface to the second surface, a first interconnect trace connected to the first surface of the substrate and electrically connected to a first of the plurality of vias, a second interconnect trace connected to the first surface of the substrate and electrically connected to a second of the plurality of vias, and a microwave circuit chip connected to the second surface of the substrate and electrically connected to the first and second conductive vias.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: An integrated circuit is composed of a substrate, a first conductor formed on the substrate, an insulating film formed on the first conductor and the substrate, a second conductor formed on the insulating film, a first interconnection formed in the insulating film and a second interconnection formed on the insulating film. The first conductor and the second conductor constitute a pair of transmission lines. The first interconnection and the second interconnection constitute a circuit. The pair of transmission lines and the circuit are separated such that the circuit does not substantially interfere electrically with the pair of transmission lines.

Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.

Abstract: A high frequency wiring substrate comprises surface transmission line conductors formed on upper and lower surfaces of a dielectric substrate and surrounded by respective surface ground conductors, and a transmission line interconnect structure for transmitting a high frequency signal between the surface transmission line conductors via an interlayer transmission line conductor surrounded by an interlayer ground conductor and connected at both ends thereof to the respective ends of the surface transmission line conductors by signal conducting through-hole conductors. The surface ground conductors are connected together by two arrays of top-to-bottom through-hole ground conductors, while the interlayer ground conductor is connected to the surface ground conductors by interlayer through-hole ground conductors.

Abstract: A lateral silicon carbide junction field effect transistor has p-conductive and n-conductive silicon carbide layers. The layers are provided in pairs in lateral direction in a silicon carbide body. Trenches for a source, a drain and a gate extend from a principal surface of the silicon carbide body and penetrate the layers. The source and drain trenches are filled with silicon carbide of one conductivity type, whereas the trench for the gate is filled with silicon carbide of a conductivity type that is different from the source and the drain.

Abstract: To form a driver circuit to be mounted to a liquid crystal display device or the like on a glass substrate, a quartz substrate, etc., and to provide a display device mounting driver circuits formed from different TFTs suited for their respective operational characteristics. A stick driver circuit on the scanning line side and a stick driver circuit on the data line side are different in structure, and have different TFTs in which the thickness of a gate insulating film, the channel length and other parameters are varied depending on required circuit characteristics. In the stick driver on the scanning line side, which is composed of a shift register circuit, a level shifter circuit, and a buffer circuit, the buffer circuit has a TFT with a thick gate insulating film because it is required to have a withstand voltage of 30 V.

Abstract: A drive transistor for an ink jet print head includes a semiconductor substrate having a serpentine channel of a first type doping, the channel comprising substantially parallel first and second serpentine channel portions, the first and second serpentine channel portions defining an inner region disposed between the first and second serpentine channel portions and an outer region disposed outside the first and second serpentine channel portions. A drain of a second type doping which is disposed within the inner region. A source of a second type doping which is disposed within the outer region. The transistor has a serpentine gate that overlies the serpentine channel. An elongate drain conductor, which tapers from a wide drain conductor end to a narrow drain conductor end, at least partially overlies a portion of the drain and the serpentine channel. An elongate source conductor has two tapered source conductor portions that at least partially overly the source and the serpentine channel.

Abstract: Comparing with, for example, a semiconductor device having the configuration in which the logic circuit and the DRAM cell circuit are consolidated, a semiconductor device in which an analog capacity element is installed without substantially increasing the number of the steps is provided.

Abstract: A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.

Abstract: A semiconductor device that has a structure wherein plural incremental circuits each of which is structured by a combination of a field effect transistor and a transmission line are connected and arranged in serial, in the arrangement of the above incremental circuits, the total length of the transmission lines of respective incremental circuits is longer than at least 1/16 of a wavelength of used microwave or millimeter-wave, and the number of arranged incremental circuits is numerous, as a result, the above transmission lines have a function as a distributed-constant line.

Abstract: On two active areas formed in a semiconductor substrate, source electrodes, gate electrodes, and drain electrodes are disposed symmetrically to each other. A gate pad section electrically connected to both gate electrodes is disposed at one side of the active areas, and a drain pad section electrically connected to both drain electrodes is disposed at the other side of the active areas. A source pad section electrically connected to one source electrode is disposed at one side of the gate pad section and the drain pad section, and a source pad section electrically connected to the other source electrode is disposed at the other side of the gate pad section and the drain pad section. An input slot line is formed between the gate pad section and the source pad sections, and an output slot line is formed between the drain pad section and the source pad sections.

Abstract: A method of improving the performance of a traveling wave field-effect transistor operated at frequencies in the microwave range or above the microwave range comprising the steps of forming a depletion region beneath a gate electrode wherein, in a plane transverse to the direction of signal propagation, a depletion region edge has a first end portion located between the gate electrode and a drain electrode and a second end portion located between the gate electrode and a source electrode; and separating the depletion region edge from the drain electrode. Further improvements in the operation of the TWFET include adjusting the first end portion of the depletion region edge to be closer to the gate electrode relative to the distance between the second end portion of the depletion region edge and the gate electrode, controlling an effective conductivity of a semiconductor of the traveling-wave field effect transistor, and setting the length of the gate electode at about one micron.

Abstract: Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.

Abstract: Solid state image sensor which can improve photic sensitivity of photodiodes by providing only one transmission line between the photodiodes, leading to reduction of width of the transmission line passing between the photodiodes, including a substrate, photodiodes formed on the substrate, a first to a fourth transmission gates arranged in sequence by four for every two photodiodes on a part of the substrate on one side of each of the photodiode, a first, and a second transmission lines arranged one by one alternatively extended at length on the substrate between adjacent photodiodes connected to the first, and the second transmission gates respectively for applying a first, and a second driving clock signals, respectively, a first contact formed at the third transmission gate, a second contact formed at the fourth transmission gate, and a third, and a fourth transmission lines formed over the transmission gates in parallel at length connected through the third, and the fourth transmission gates and the first,

Abstract: A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.

Abstract: A Concentric MESFET (CMESFET) is a small-signal traveling-wave transistor having a grounded source electrode which concentrically surrounds and shields the gate and drain electrodes from electromagnetic fields generated by other nearby circuit elements. S-parameters for the transistor are computed to obtain gain curves for design configurations. For a gate length of 2 um, maximum gain occurs with a gate width of 3.0 mm. The CMESFET has calculated bandwidth of 17 GHz for a 2 um gate length and a gate width of 300 m. Coupling capacitance between device electrodes and a nearby transmission line are calculated and used to verify improved source electrode shielding isolation of the device from interference and crosstalk originating in surrounding circuits.