Abstract: In the field of photoelectric devices, a visible light detector is provided with high-photoresponse based on a TiO2/MoS2 heterojunction and a preparation method thereof. The detector, based on a back-gated field-effect transistor based on MoS2, includes a MoS2 channel, a TiO2 modification layer, a SiO2 dielectric layer, Au source/drain electrodes and a Si gate electrode, The TiO2 modification layer is modified on the surface of the MoS2 channel. By employing micromechanical exfoliation and site-specific transfer of electrodes, the method is intended to prepare a detector by constructing a back-gated few-layer field-effect transistor based on MoS2, depositing Ti on the channel surface, and natural oxidation.

Abstract: A quantum cascade laser includes light-emitting quantum well layers configured to emit infrared laser light by an intersubband transition; and injection quantum well layers configured to relax carrier energy. The light-emitting quantum well layers and the injection quantum well layers are stacked alternately. The injection quantum well layers relax the energy of carriers injected from the light-emitting quantum well layers, respectively. The light-emitting quantum well layers and the injection quantum well layers including barrier layers. At least one barrier layer includes first and second regions of a first ternary compound semiconductor, and a binary compound semiconductor thin film. The binary compound semiconductor thin film is provided between the first and second regions. The first ternary compound semiconductor includes Group III atoms and a Group V atom. The binary compound semiconductor thin film includes one Group III atom of the first ternary compound semiconductor and the Group V atom.

Abstract: Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

Abstract: Methods and apparatus for quantum assisted optimization. In one aspect, a method includes obtaining a set of initial input states, applying one or more of (i) dynamical thermal fluctuations and (ii) cluster update algorithms to the set of input states and subsequent input states when the states evolve within the classical information processors, applying dynamical quantum fluctuations to the set of input states and subsequent states when the states evolve within the quantum systems and repeating the application steps until a desirable output state is obtained.

Abstract: A display structure and a manufacturing method thereof are provided. The manufacturing method including steps of: (a) providing a carrier sequentially including a rigid substrate, a sacrificial layer, and a graphene layer; (b) forming a flexible substrate on the carrier; (c) forming a display component layer on the flexible substrate; and (d) removing the rigid substrate and the sacrificial layer. By using the sacrificial layer and the graphene layer to prevent display structures from being damaged by a laser peeling off step and protect the flexible substrate during the manufacturing process, and increase the bendability of the flexible substrate.

Abstract: Computer architecture methods and system for providing novel inhomogeneous computer interconnects and interconnect topology framework for both classical and quantum computers are provided that result in enhanced computer functionality and efficiency. The architecture and methodologies include random small world (SW) interconnects or bonds and/or SW interconnects or bonds with constrained randomness.

Abstract: The present invention discloses a method for growing gallium nitride based on graphene and magnetron sputtered aluminum nitride, and a gallium nitride thin film. The method according to an embodiment comprises: spreading graphene over a substrate; magnetron sputtering an aluminum nitrite onto the graphene-coated substrate to obtain a substrate sputtered with aluminum nitrite; placing the substrate sputtered with aluminum nitride into a MOCVD reaction chamber and heat treating the substrate to obtain a heat treated substrate; growing an aluminum nitride transition layer on the heat treated substrate and a first and a second gallium nitride layer having different V-III ratios, respectively.

Abstract: A method of forming a high-conductivity electrical interconnect on a substrate may include forming a graphene film with a plurality of graphene members, depositing a metal over the graphene film, and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film.

Abstract: The subject disclosure relates generally to an automated testing tool for quantum software development kits (SDKs). A system in accordance with an embodiment comprises a memory that stores computer-executable components. A processor is operably coupled to the memory and executes the computer-executable components stored in the memory. The computer-executed components comprises: a transformation component that receives a qasm program and transforms the qasm program; a testing component that tests the transformed qasm program on the SDK; and a reporting component that reports whether a quantum SDK has functioned properly or failed for the transformed qasm program.

Abstract: The disclosure is directed at a method and system for three-dimensional (3D) printing of flexible graphene electronic devices and deposition of graphene on non-planar surfaces. By using a printer ink that includes a stabilized graphene powder and a pair of solvents, the printer ink provides for a material that overcomes disadvantages of current systems. In one embodiment, the pair of solvents are cyclohexanone and terpineol. The stabilized graphene powder preferably includes a polymer such as, but not limited to ethyl cellulose.

Abstract: A device emitting mid-infrared light that comprises a semiconductor substrate of GaSb or closely related material. The device can also comprise epitaxial heterostructures of InAs, GaAs, AISb, and related alloys forming light emitting structures cascaded by tunnel junctions. Further, the device can comprise light emission from the front, epitaxial side of the substrate.

Abstract: An apparatus for use in determining the relative vapor pressure of a fluid in an environment in which the apparatus is located, the apparatus comprising a first layer (512) configured to enable a flow of charge carriers from a source electrode (505) to a drain electrode (506), a second layer (513) configured to control the conductance of the first layer (512) using an electric field formed between the first (512) and second layers (513) and a third layer (514) positioned between the first and second layers to prevent a flow of charge carriers therebetween to enable formation of the electric field, wherein the second layer (513) is configured to exhibit a charge distribution on interaction with the fluid, the charge distribution giving rise to the electric field between the first (512) and second (513) layers, and wherein the second layer (513) is configured such that the charge distribution and electric field strength are dependent upon the relative vapor pressure of the fluid in the environment (516), thereb

Abstract: A LED lamp includes an at least partially optically transmissive enclosure and a base connected to the enclosure. A plurality of LEDs are located in the enclosure and are operable to emit light when energized through an electrical path from the base. An optical interface is positioned in the enclosure for electrically isolating a live electrical component and for receiving at least a portion of the light. The optical interface includes a light modifying property for modifying a characteristic of the portion of the light.

Abstract: A sensor device includes a semiconductor chip. The semiconductor chip has a sensing region sensitive to mechanical loading. A pillar is mechanically coupled to the sensing region.

Abstract: A nanoscale solid state terahertz emitter employs a layered half-cylinder associated with a substrate. The half-cylinder is configured with a channel having a pre-determined channel length. The emitter is defined in a three-dimensional frame of reference. The layered half-cylinder includes a conductor layer bonded to the substrate. An insulator layer is bonded to the conductor layer. An arcuate-shaped graphene layer is bonded to the insulator layer along a pre-determined contact length.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing doped graphene sheets about the object to be shielded. The doped graphene sheets have a dopant concentration that is effective to reflect and/or absorb the electromagnetic radiation.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer and a second device layer formed on a first device layer. The first device layer is formed on a substrate and includes a first channel structure configured to conduct a first current, the first channel structure including a first material capable of sustaining a first processing temperature. The second device layer includes a second channel structure configured to conduct a second current, the second channel structure including a second material capable of sustaining a second processing temperature, the second processing temperature being equal to or lower than the first processing temperature.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer.

Abstract: According to example embodiments, a two-dimensional (2D) material element may include a first 2D material and a second 2D material chemically bonded to each other. The first 2D material may include a first metal chalcogenide-based material. The second 2D material may include a second metal chalcogenide-based material. The second 2D material may be bonded to a side of the first 2D material. The 2D material element may have a PN junction structure. The 2D material element may include a plurality of 2D materials with different band gaps.

Abstract: Two- and three-terminal molecular electronic devices with ballistic electron transport are described. For example, a two-terminal molecular electronic device includes a conductor 1 layer/molecule 1 layer/conductor2 layer junction, wherein the total thickness of the molecule 1 layer and the conductor2 layer is less than or approximately equal to the mean free path of a charge carrier traveling in the two layers, and wherein ballistic transport can occur for some fraction of a plurality of charge carriers in the two layers.

Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.

Abstract: The presently claimed invention provides a highly conductive composite used for electric charge transport, and a method for fabricating said composite. The composite comprises a plurality of one-dimensional semiconductor nanocomposites and highly conductive nanostructures, and the highly conductive nanostructures are incorporated into each of the one-dimensional semiconductor nanocomposite. The composite is able to provide fast electric charge transport, and reduce the rate of electron-hole recombination, ultimately increasing the power conversion efficiency for use in solar cell; provide fast electrons transport, storage of electrons and large surface area for adsorption and reaction sites of active molecular species taking part in photocatalytic reaction; enhance the sensitivity of a surface for biological and chemical sensing purposes for use in biological and chemical sensors; and lower the impedance and increase the charge storage capacity of a lithium-ion battery.

Abstract: A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.

Abstract: One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.

Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.

Abstract: The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.

Abstract: A method for forming a graphite-based device on a substrate having a plurality of zones is provided where the substrate is carbon doped in zones. Each such zone comprises a plurality of dopant profiles. One or more graphene stacks are generated in the doped zones. A graphene stack so generated comprises a non-planar graphene layer characterized by a bending angle, curvature, characteristic dimension, graphene orientation, graphene type, or combinations thereof. A method for forming a graphite-based device on a substrate is provided, the substrate comprising a graphene foundation material and a plurality of zones. The substrate is patterned to form features in the zones. One feature comprises a non-planar surface or at least two adjacent surfaces that are not coplanar. One or more graphene stacks are concurrently generated, at least one of which comprises a non-planar graphene layer overlaying the non-planar surface or the at least two adjacent surfaces.

Abstract: A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

Abstract: A nanostructured device according to the invention comprises a first group of nanowires protruding from a substrate where each nanowire of the first group of nanowires comprises at least one pn- or p-i-n-junction. A first contact, at least partially encloses and is electrically connected to a first side of the pn- or p-i-n- junction of each nanowire in the first group of nanowires. A second contacting means comprises a second group of nanowires that protrudes from the substrate, and is arranged to provide an electrical connection to a second side of the pn- or p-i-n-junction.

Abstract: A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer is on the epitaxial growth layer of the substrate. The active layer is between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, and a reflection layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate in sequence. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. The reflection layer covers the second semiconductor layer.

Abstract: Disclosed is a semiconductor component, including: a drift zone arranged between a first and a second connection zone; a channel control layer of an amorphous semi-insulating material arranged adjacent to the drift zone.

Abstract: A first thin film diode (100A) has a first semiconductor layer (10A) and a first light blocking layer (12A) disposed on the substrate side of the first semiconductor layer. A second thin film diode (100B) has a second semiconductor layer (10B) and a second light blocking layer (12B) disposed on the substrate side of the second semiconductor layer. An insulating film (14) is formed between the first semiconductor layer (10A) and the first light blocking layer (12A) and between the second semiconductor layer (10B) and the second light blocking layer (12B). A thickness D1 of a portion of the insulating film (14) positioned between the first semiconductor layer (10A) and the first light blocking layer (12A) is different from a thickness D2 of a portion of the insulating film (14) positioned between the second semiconductor layer (10B) and the second light blocking layer (12B).

Abstract: The presently claimed invention provides a highly conductive composite used for electric charge transport, and a method for fabricating said composite. The composite comprises a plurality of one-dimensional semiconductor nanocomposites and highly conductive nanostructures, and the highly conductive nanostructures are incorporated into each of the one-dimensional semiconductor nanocomposite. The composite is able to provide fast electric charge transport, and reduce the rate of electron-hole recombination, ultimately increasing the power conversion efficiency for use in solar cell; provide fast electrons transport, storage of electrons and large surface area for adsorption and reaction sites of active molecular species taking part in photocatalytic reaction; enhance the sensitivity of a surface for biological and chemical sensing purposes for use in biological and chemical sensors; and lower the impedance and increase the charge storage capacity of a lithium-ion battery.

Abstract: The electronic component comprises at least two superposed conducting or semiconducting layers. According to one aspect of the invention, it comprises at least graphene layer interposed between the conducting or semiconducting layers, the conducting or semiconducting layers being electronically coupled through the thickness of said or each graphene layer. Application notably to tunnel junctions either magnetic or not, to spin valves, to memristors.

Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?1 degree towards (000-1) and less than about +/?0.3 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. In a preferred embodiment, the laser stripe region is characterized by a cavity orientation that is substantially parallel to the c-direction, the laser stripe region having a first end and a second end. The device includes a first cleaved c-face facet, which is coated, provided on the first end of the laser stripe region. The device also has a second cleaved c-face facet, which is exposed, provided on the second end of the laser stripe region.

Abstract: A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.

Abstract: A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: An epitaxial structure is provided. The epitaxial structure includes a substrate, an epitaxial layer and a graphene layer. The epitaxial layer is located on the substrate. The graphene layer is located between the substrate and the epitaxial layer. The graphene layer can be a graphene film or graphene powder. The epitaxial structure can be made by: providing a substrate having an epitaxial growth surface, placing a graphene layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.

Abstract: A polymer photodetector has an inverted device structure that includes an indium-tin-oxide (ITO) cathode that is separated from an anode by an active layer. The active layer is formed as a composite of conjugated polymers, such as PDDTT and PCBM. IN addition, a cathode buffer layer formed as an matrix of ZnO nanowires is disposed upon the ITO cathode, while a MoO3 anode buffer layer is disposed between a high work-function metal anode and the active layer. During operation of the photodetector, the ZnO nanowires allows the effective extraction of electrons and the effective blocking of holes from the active layer to the cathode. Thus, allowing the polymer photodetector to achieve a spectral response and detectivity that is similar to that of inorganic photodetectors.

Abstract: Two- and three-terminal molecular electronic devices with ballistic electron transport are described. For example, a two-terminal molecular electronic device includes a conductor 1 layer/molecule 1 layer/conductor2 layer junction, wherein the total thickness of the molecule 1 layer and the conductor2 layer is less than or approximately equal to the mean free path of a charge carrier traveling in the two layers, and wherein ballistic transport can occur for some fraction of a plurality of charge carriers in the two layers.

Abstract: The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm?1.

Abstract: An optical device capable of emitting light having a wavelength ranging from about 490 to about 580 nanometers has a gallium nitride substrate with a semipolar crystalline surface region characterized by an orientation of greater than 3 degrees from (11-22) towards (0001) but less than about 50 degrees. A laser stripe formed on the substrate has a cavity orientation substantially parallel to the m-direction.