Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a bottom dielectric layer continuously disposed on the substrate. The semiconductor structure further includes a plurality of stacks disposed on the bottom dielectric layer. Each of the stacks includes gate electrodes and semiconductor layers disposed alternately. The semiconductor structure further includes a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks. The semiconductor structure further includes a plurality of conductors landed on highest gate electrodes of the stacks.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

Abstract: This disclosure discloses a fault tolerant and error correction decoding method and apparatus for a quantum circuit, and a chip. This disclosure relates to the field of artificial intelligence (AI) and quantum technologies. The method includes: obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit by using a quantum error correction (QEC) code; decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information that correspond to the actual error syndrome information; and determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.

Abstract: A semiconductor device includes a base, a first FET that includes at least two laminated channel structure portions, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: A semiconductor device includes a substrate, a gate structure, semimetallic source/drain structures, and source/drain contacts. The gate structure is over the substrate. The semimetallic source/drain structures are respectively on opposite sides of the gate structure, in which a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points. The source/drain contacts land on top surfaces of the semimetallic source/drain structures, respectively.

Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes first semiconductor sheets and two first source/drain structures. The first semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the first semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the first doped layers. The two first source/drain structures are disposed at two opposite sides of each of the first semiconductor sheets in a horizontal direction respectively, and the two first source/drain structures are connected with the first semiconductor sheets.

Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

Abstract: A nonvolatile memory device having multi-level resistance and capacitance values is provided. Such a nonvolatile memory device includes: a substrate; a first electrode that is provided on the substrate; a dielectric layer that is provided on the first electrode, has resistance and capacitance changed by a tunneling conduction phenomenon of charges according to an applied voltage, has rectifying characteristics, and includes a dielectric material; an active layer that is provided on the dielectric layer, has resistance and capacitance changed according to an applied voltage, and includes a graphene oxide complex; and a second electrode that is provided on the active layer. In addition, the nonvolatile memory device has multi-level resistance and capacitance values according to an applied voltage.

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

Abstract: Disclosed is a 2D-3D HJ-TFET made of a material, the band gap of which changes according to the thickness, such as black phosphorous or TMDC, in order to extend Moore's law. More particularly, disclosed are the structure of a 2D-3D HJ-TFET and a method for manufacturing the same, wherein the 2D-3D HJ-TFET is made of a material such as black phosphorous or TMDC such that the same consumes less power, has a high switching speed, can operate in a complementary manner so as to replace a conventional CMOS transistor, and can extend Moore's law.

Abstract: A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: Disclosed herein are a series of compounds based on Formula (I). These compounds comprise perylene core which has been extended with optionally functionalised imidazoles at the 3,4;9,10 positions. The compounds of Formula (I) can be functionalised at two positions on the perylene core, such as the 1,6 or 1,7 positions. Also disclosed herein are compositions comprising said compounds, methods of forming said compounds and potential applications of said compounds, such as applying the compounds as a dye whose absorbance and fluorescence spectrum are red-shifted.

Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: The present disclosure discloses a metamaterial based metal gate MOSFET detector with gate rasterized, comprising a metamaterial based metal gate MOSFET having a rasterized gate structure and various different grating pattern forms thereof, wherein a gate of the metal gate MOSFET is connected to a first bias resistor and a first bias voltage, a source of the metal gate MOSFET is grounded, a drain of the metal gate MOSFET is connected to a first DC blocking capacitor, the first DC blocking capacitor is connected to a low noise preamplifier, and a second bias resistor and a second bias voltage are connected between the low noise preamplifier and the first DC blocking capacitor. The technical solution according to the present disclosure can completely absorb terahertz waves of a specific frequency band and generate resonance.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.