Field Effect Transistor Patents (Class 257/27)
  • Patent number: 11450755
    Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 20, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 11437483
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
  • Patent number: 11430891
    Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11417766
    Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11398553
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ruei-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Patent number: 11380785
    Abstract: A semiconductor device includes a substrate, a gate structure, semimetallic source/drain structures, and source/drain contacts. The gate structure is over the substrate. The semimetallic source/drain structures are respectively on opposite sides of the gate structure, in which a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points. The source/drain contacts land on top surfaces of the semimetallic source/drain structures, respectively.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Sheng-Kai Su
  • Patent number: 11355621
    Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Sean Ma, Nicholas Minutillo, Tahir Ghani, Matthew V. Metz, Cheng-Ying Huang, Anand S. Murthy
  • Patent number: 11355494
    Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes first semiconductor sheets and two first source/drain structures. The first semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the first semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the first doped layers. The two first source/drain structures are disposed at two opposite sides of each of the first semiconductor sheets in a horizontal direction respectively, and the two first source/drain structures are connected with the first semiconductor sheets.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Yu-Wen Hung
  • Patent number: 11342446
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 24, 2022
    Assignee: Tessera, Inc.
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 11322493
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhi-Chang Lin, Huan-Chieh Su, Kuo-Cheng Chiang
  • Patent number: 11276612
    Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: March 15, 2022
    Assignee: Tessera, Inc.
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Wenyu Xu
  • Patent number: 11264381
    Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungryul Lee, Yongseung Kim, Jungtaek Kim, Pankwi Park, Dongchan Suh, Moonseung Yang, Seojin Jeong, Minhee Choi, Ryong Ha
  • Patent number: 11251371
    Abstract: A nonvolatile memory device having multi-level resistance and capacitance values is provided. Such a nonvolatile memory device includes: a substrate; a first electrode that is provided on the substrate; a dielectric layer that is provided on the first electrode, has resistance and capacitance changed by a tunneling conduction phenomenon of charges according to an applied voltage, has rectifying characteristics, and includes a dielectric material; an active layer that is provided on the dielectric layer, has resistance and capacitance changed according to an applied voltage, and includes a graphene oxide complex; and a second electrode that is provided on the active layer. In addition, the nonvolatile memory device has multi-level resistance and capacitance values according to an applied voltage.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: February 15, 2022
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Hyung Jang, Rani Anoop, Se I Oh
  • Patent number: 11152338
    Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Qiang Wu, Chun-Fu Cheng, Chung-Cheng Wu, Yi-Han Wang, Chia-Wen Liu
  • Patent number: 11121243
    Abstract: Disclosed is a 2D-3D HJ-TFET made of a material, the band gap of which changes according to the thickness, such as black phosphorous or TMDC, in order to extend Moore's law. More particularly, disclosed are the structure of a 2D-3D HJ-TFET and a method for manufacturing the same, wherein the 2D-3D HJ-TFET is made of a material such as black phosphorous or TMDC such that the same consumes less power, has a high switching speed, can operate in a complementary manner so as to replace a conventional CMOS transistor, and can extend Moore's law.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 14, 2021
    Assignee: Korea Advanced Institute of Science and Technology
    Inventor: Sungjae Cho
  • Patent number: 11043493
    Abstract: A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li
  • Patent number: 11024750
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhihong Chen, Shu-Jen Han, Siyuranga O. Koswatta, Alberto Valdes Garcia
  • Patent number: 10995217
    Abstract: Disclosed herein are a series of compounds based on Formula (I). These compounds comprise perylene core which has been extended with optionally functionalised imidazoles at the 3,4;9,10 positions. The compounds of Formula (I) can be functionalised at two positions on the perylene core, such as the 1,6 or 1,7 positions. Also disclosed herein are compositions comprising said compounds, methods of forming said compounds and potential applications of said compounds, such as applying the compounds as a dye whose absorbance and fluorescence spectrum are red-shifted.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 4, 2021
    Assignee: LLEAF PTY LTD
    Inventor: Alexander Falber
  • Patent number: 10998233
    Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Alexander Reznicek, Chun-Chen Yeh, Chen Zhang
  • Patent number: 10923567
    Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: February 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Luigi Colombo, Archana Venugopal
  • Patent number: 10833199
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Patent number: 10833216
    Abstract: The present disclosure discloses a metamaterial based metal gate MOSFET detector with gate rasterized, comprising a metamaterial based metal gate MOSFET having a rasterized gate structure and various different grating pattern forms thereof, wherein a gate of the metal gate MOSFET is connected to a first bias resistor and a first bias voltage, a source of the metal gate MOSFET is grounded, a drain of the metal gate MOSFET is connected to a first DC blocking capacitor, the first DC blocking capacitor is connected to a low noise preamplifier, and a second bias resistor and a second bias voltage are connected between the low noise preamplifier and the first DC blocking capacitor. The technical solution according to the present disclosure can completely absorb terahertz waves of a specific frequency band and generate resonance.
    Type: Grant
    Filed: March 10, 2019
    Date of Patent: November 10, 2020
    Assignee: Guangdong University of Technology
    Inventors: Jianguo Ma, Shaohua Zhou
  • Patent number: 10714392
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10593763
    Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Luigi Colombo, Archana Venugopal
  • Patent number: 10559670
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10505047
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 10, 2019
    Assignee: ACORN SEMI, LLC
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Patent number: 10497779
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Patent number: 10475908
    Abstract: A semiconductor device includes a channel region, a source region having a first type semiconductor and a drain region having a second type semiconductor on opposing sides of the channel region. A gate stack is disposed over the channel region. A low-k spacer is disposed over the source region and abreast the gate stack. The source region includes a first type dopant, and the drain region includes a second type dopant. A pocket is disposed between the channel region and the source region. The pocket has the first type semiconductor and a higher first type dopant concentration than a first type dopant concentration of the source region.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Aryan Afzalian
  • Patent number: 10468311
    Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by implantation of nitrogen into physically exposed surfaces of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The nitrogen doped semiconductor region that is created by the nitrogen implantation is subsequently converted into a semiconductor nitride region (i.e., an isolation region) prior to the epitaxial growth of a semiconductor material that provides S/D regions from physically exposed sidewalls of each semiconductor channel material stack. The presence of the semiconductor nitride region prevents bottom up growth of the semiconductor material that provides the S/D regions.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 10453967
    Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Szuya S. Liao, Stephen M. Cea
  • Patent number: 10431683
    Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10431585
    Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 10411135
    Abstract: Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Joanne Huang, Jamil Kawa
  • Patent number: 10249762
    Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10192971
    Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 29, 2019
    Assignee: NUtech Ventures
    Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
  • Patent number: 10181516
    Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Luigi Colombo, Archana Venugopal
  • Patent number: 10170584
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10170627
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Acorn Technologies, Inc.
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Patent number: 10153087
    Abstract: An electro-polarizable compound has the following general formula: Core1 is an aromatic polycyclic conjugated molecule having two-dimensional flat form and self-assembling by pi-pi stacking in a column-like supramolecule. R1 are electron donor groups connected to Core1 and R1? are electron acceptor groups connected to Core1, m is number of acceptor groups R1, m? is a number of donor groups R?. The numbers m and m? are equal to 0, 1, 2, 3, 4, 5 or 6, but both m and m? are not both equal to 0. R2 is a substituent comprising one or more ionic groups connected to Core1 directly or via a connecting group; a number p of ionic groups R2 is 0, 1, 2, 3 or 4. The fragment marked NLE has a nonlinear effect of polarization. Core2 is a self-assembling electro-conductive oligomer, a number n of the such oligomers is 0, 2, or 4. R3 is a substituent comprising one or more ionic groups connected to Core2; a number s of the ionic groups R3 is 0, 1, 2, 3 or 4.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: December 11, 2018
    Assignee: CAPACITOR SCIENCES INCORPORATED
    Inventors: Pavel Ivan Lazarev, Paul T. Furuta, Barry K. Sharp, Yan Li, Ian S. G. Kelly-Morgan
  • Patent number: 10141409
    Abstract: A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dacheng Zhang, Dianjie Hou, Wenchu Dong
  • Patent number: 10134849
    Abstract: The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 20, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ming Zhou
  • Patent number: 9947775
    Abstract: A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge. Stacked sacrificial material nanowires are first formed, then after masking and etching process to reveal a semiconductor seed layer, the sacrificial material nanowires are removed, and III-V compound semiconductor or germanium epitaxy is performed to fill the void previously occupied by the sacrificial material nanowires.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9941405
    Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Wei-E Wang, Mark S. Rodder
  • Patent number: 9941360
    Abstract: A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Seunghan Seo, Yeohyun Sung
  • Patent number: 9929160
    Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juri Lee, Yong-Suk Tak, Sung-Dae Suk, Seungmin Song
  • Patent number: 9917208
    Abstract: A TFT, a method for manufacturing the TFT, and an array substrate are disclosed. In the TFT according to the present disclosure, the nano conductive points that are independent from one another are formed in a channel area of the active layer, so that the channel area of the active layer can be divided into a plurality of sub channels that are independent from one another, and an equivalent electric field strength thereof can be increased. The larger the equivalent electric field strength is, the higher the carrier mobility ratio would be, and the larger the saturation current of the TFT would become. Therefore, the TFT with a higher definition and a higher aperture ratio can be manufactured.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 13, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Macai Lu
  • Patent number: 9911835
    Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios, Anurag Chaudhry, Thomas D. Linton, Jr., Ian A. Young, Kelin J. Kuhn
  • Patent number: 9900979
    Abstract: A conductor includes a substrate, a first conductive layer disposed on the substrate and including two or more islands including graphene, and a second conductive layer disposed on the first conductive layer and including a conductive metal nanowire, wherein at least one of an upper surface and a lower surface of the islands including graphene includes a P-type dopant.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hiesang Sohn, Chan Kwak, Mi Jeong Kim, Hyeon Cheol Park, Weonho Shin, Youngjin Cho
  • Patent number: 9882008
    Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Luigi Colombo, Archana Venugopal
  • Patent number: 9873102
    Abstract: This disclosure provides systems, methods, and apparatus related to catalytic devices. In one aspect, a device includes a substrate, an electrically insulating layer disposed on the substrate, a layer of material disposed on the electrically insulating layer, and a catalyst disposed on the layer of material. The substrate comprises an electrically conductive material. The substrate and the layer of material are electrically coupled to one another and configured to have a voltage applied across them.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: January 23, 2018
    Assignee: The Regents of the University of California
    Inventors: Ming Liu, Xiang Zhang