Abstract: An optical device capable of emitting light having a wavelength ranging from about 490 to about 580 nanometers has a gallium nitride substrate with a semipolar crystalline surface region characterized by an orientation of greater than 3 degrees from (11-22) towards (0001) but less than about 50 degrees. A laser stripe formed on the substrate has a cavity orientation substantially parallel to the m-direction.

Abstract: The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm?1.

Abstract: An apparatus including a first layer configured to enable a flow of charge carriers from a source electrode to a drain electrode, a second layer configured to control the density of charge carriers in the first layer using an electric field formed between the first and second layers, and a third layer positioned between the first and second layers to shield the first layer from the electric field, wherein the third layer includes a layer of electrically conducting nanoparticles and is configured such that when stress is applied to the third layer, the strength of the electric field experienced by the first layer is varied resulting in a change in the charge carrier density and a corresponding change in the conductance of the first layer.

Abstract: Embodiments of graphene channel transistors and methods for producing same are provided herein. In some embodiments, a graphene channel transistor may include a substrate a having a source region, a drain region, and a dielectric material disposed between the source and drain regions; a channel region comprising a graphene layer disposed atop the dielectric material and partially atop the source and drain regions; and a composite gate electrode comprising an insulator layer disposed atop the graphene layer and a conductive layer disposed atop the insulator layer.

Abstract: According to example embodiments, a semiconductor device includes a first electrode, a second electrode apart from the first electrode, and an active layer between the first and second electrodes. The active layer includes first and second layers, the first layer contacts the first and second electrodes, and the second layer is separated from at least one of the first and second electrodes.

Abstract: The present invention provides a graphene/oxide semiconductor Schottky junction device, a graphene/oxide semiconductor p-n heterojunction device, and fabrication methods thereof. The Schottky junction device comprises graphene vapor-deposited directly on thin films, nanowires, nanotubes, nanobelts or nanoparticles. The p-n heterojunction device is manufactured by doping the graphene of the Schottky junction device so as to convert the graphene into a semiconductor.

Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.

Abstract: A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer.

Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.

Abstract: A semiconductor device includes a substrate; a first conductive type semiconductor layer disposed on a main surface of the substrate; a second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; a plurality of light emitting elements; and a second conductive side wiring pattern for commonly connecting the second conductive type semiconductor layer in the light emitting elements arranged adjacently. The second conductive type semiconductor layer includes a first conductive type semiconductor connection surface and a second conductive type semiconductor connection surface between the first conductive type semiconductor layer.

Abstract: Provided are an electronic device and a light-receiving and light-emitting device which can control the electron configuration of a graphene sheet and the band gap thereof, and an electronic integrated circuit and an optical integrated circuit which use the devices. By shaping the graphene sheet into a curve, the electron configuration thereof is controlled. The graphene sheet can be shaped into a curve by forming the sheet on a base film having a convex structure or a concave structure. The local electron states in the curved part can be formed by bending the graphene sheet. Thus, the same electron states as the cylinder or cap part of a nanotube can be realized, and the band gaps at the K points in the reciprocal lattice space can be formed.

Abstract: Described is a scalable quantum computer that includes at least two classical to quantum interface devices, with each being connected to a distinct quantum processing unit (QPU). An Einstein-Podolsky-Rosen pair generator (EPRPG) is included for generating an entangled Einstein-Podolsky-Rosen pair that is sent to the QPUs. Each QPU is quantumly connected with the EPRPG and is configured to receive a mobile qubit from the EPRPG and perform a sequence of operations such that the mobile qubit interacts with a source qubit when a teleportation algorithm is initiated, leaving a second mobile qubit in the original quantum state of the source qubit.

Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.

Abstract: A fine vacuum tube element and other electronic elements are integrated and formed on a semiconductor substrate, and the fine vacuum tube element and the other electronic elements transmit signals to and from each other. When integrating the vacuum tube element with the other electronic elements, a quantum effect is realized in a room temperature environment by utilizing ballistic electrons (non-scattering electrons) traveling through the vacuum, and in the integrated circuit, an A/D converter is constructed by an interference system such as a Mach-Zehnder interferometer. Also an integrated circuit of an advanced function-integrated type is provided, comprising an interference system such as a Mach-Zehnder interferometer wherein weighting of the Mach-Zehnder interferometer is constituted for image processing and signal code conversion.

Abstract: Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.

Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

Abstract: The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that that exhibit no or reduced Schottky barriers. One aspect of the invention provides a solid nanowire having a core and a shell, both of which are essentially undoped. For example, in one embodiment, the core may consist essentially of undoped germanium and the shell may consist essentially of undoped silicon. Carriers are injected into the nanowire, which can be ballistically transported through the nanowire. In other embodiments, however, the invention is not limited to solid nanowires, and other configurations, involving other nanoscale wires, are also contemplated within the scope of the present invention. Yet another aspect of the invention provides a junction between a metal and a nanoscale wire that exhibit no or reduced Schottky barriers.

Abstract: Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism. The injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage region while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. The present invention further provides an energy band engineering method permitting the memory device be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Abstract: The speed at which optical networking devices operate is increased with the present invention with integrated circuits that provide both optical and electronic functions. The present invention provides highly integrated p-i-n or p-i-n-i-p photodetectors and heterojunction bipolar transistors for amplifying photodetector signals formed from a single semiconductor layer stack. The techniques are applicable for the integration of all InP-based and GaAs-based single-heterojunction bipolar transistors and double-heterojunction bipolar transistors. The photodetectors and transistors are formed from common layers, allowing them to be manufactured simultaneously during a processing of the stack. Integrating these components on a single circuit has the potential to greatly increase the speed (in excess of 40 Gb/s) and to decrease the cost of high-speed networking components through the development of compact optical circuits for optical networking.

Abstract: A heterojunction bipolar transferred electron tetrode has an anode region providing a first terminal, an active region in which Gunn-Hilsum oscillations are generated, a base region providing a second terminal, a cathode region providing a third terminal, and a fourth terminal which is operable independently of the three terminals. The fourth terminal can take the form of a second cathode-type structure, a second base region or a Schottky gate electrode. The cathode region and fourth terminal are in proximity enough to each other such that one of the cathode region and the fourth terminal is usable as an input terminal and that the other of the cathode region and the fourth terminal is usable as a terminal to which an electrical signal for disturbing an electric field profile or a current density in the active region is applied.

Abstract: A light-receiving device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and carrier accumulation layers C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an even number one fourth of wavelength of quantum-wave of carriers in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. As a result, when electrons are excited in the carrier accumulation layers C1 to C3, electrons are propagated through the quantum-wave interference layer from the n-layer to the p-layer as a wave, and electric current flows rapidly.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: A light-emitting device comprising an emission layer which has a single layer structure is formed. The emission layer is sandwiched by a first quantum-wave interference layer constituted by plural periods of a pair of a first layer and a second layer, the second layer having a wider band gap than the first layer, and a second quantum-wave interference layer constituted by plural periods of a pair of a third layer and a fourth layer, the fourth layer having a wider band gap than the third layer. The first quantum-wave interference layer functions as an electron reflection layer, and its thickness is determined by multiplying by an odd number one fourth of quantum-wave wavelength of the injected electrons. The second quantum-wave interference layer functions as an electron transmission layer, and its thickness is determined by multiplying by an odd number one fourth of quantum-wave wavelength of the injected electrons. As a result, luminous efficiency of the device is improved.

Abstract: A light-emitting diode comprising a quantum-wave reflection layer for electrons, a quantum-wave transmission layer for electrons, and an emission layer formed between the quantum-wave reflection layer and th e quantum-wave transmission layer is used as a photocoupler. Compared with a commercial product having a response velocity of 20 MHz, a response velocity of the light-emitting diode of the present invention is improved to be 100 MHz to 200 MHz. The quantum-wave reflection layer for electrons and the quantum-wave transmission layer for electrons are formed to have thicknesses of one fourth and a half of quantum wave of electrons, respectively.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer bandedge is at least kBT higher than the Fermi level of the semiconductor layer, which allows only selected, “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: The present invention relates to a heterojunction structure based upon the oxide/high-k dielectric barrier. In exemplary embodiment, a silicon layer has a silicon dioxide layer thereon, and a high-k dielectric material disposed on the oxide layer. Thereafter, a metal layer, serving as the gate metal for the device is disposed on the high-k dielectric. The silicon dioxide layer has a relatively high barrier height, but has a relatively small thickness, and relative to the high-k dielectric, the barrier height differential fosters real space transfer. In this structure, the high barrier height of the silicon dioxide layer results in higher mobility and thereby greater substrate current. By virtue of the relative thick layer of high-k dielectric, leakage current is significantly reduced.

Abstract: A silicon-germanium heterobipolar transistor has a silicon emitter 1, a silicon-germanium base 2 and a silicon collector 3 such that, starting from the emitter 1, the base 2 includes a change in the Ge content in the form of a step-wise increase, and a likewise step-wise, but opposing, change in the doping concentration, with a step height that is larger, seen in terms of energy, than the energy of the optical phonon energy of the semiconductor material.

Abstract: A quantum transistor (10) includes an emitter (38), an injector structure (36), a base (20) and a collector (16) coupled to the base. The injector (36) is interposed between the emitter (38) and the base (20). The injector structure (36) includes a quantum well (60) having a general conductance band minimum energy level. A notch (28) in the well (60) has a conductance band minimum energy level that is lower than the general level. This notch (28) is operable to lower the energy of electrons disposed in the quantum well (60). Therefore, the electrons resident in the well are injected through a barrier (24) into the base (20) at an energy level at or slightly above the base/collector barrier &phgr;BC, but below the X or L energies such that intervalley scattering is reduced.

Abstract: A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.

Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO.sub.2 type quantum device can be manufactured with ease at a low cost.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow "hot" electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: The present invention is to solve the problems caused in various methods used to improve the performance of the device by improvement of conventional base layer. The present invention discloses a hot electron device which can improve the performance of the device such as the improvement in the current density and decrease in transition time by reducing the dispersion phenomenon by introducing indium arsenide layer having v-shape conduction band due to the graded composition as the base layer of hetero structure hot electron device (HET).In addition, the present invention discloses a resonant tunneling hot electron device which is constructed by adding an emitter electron projection layer to the hot electron device of the present invention so that the Fermi energy and alignment can occur due to the stark shift and the projection of hot electron to the base region can occur through the Fermi energy and alignment.

Abstract: A resonant-tunnelling hot transistor includes buffer layers undoped with impurities on either side of a collector or an emitter potential barrier having a quantum well structure. When a voltage is applied to the transistor, most of the potential drop occurs at the first buffer layer and the second buffer layer due to their thickness. This enables the inclination of the energy band of the collector barrier layer or the emitter barrier layer to be diminished, whereby the energy of the confined energy state E.sub.QW of the quantum well and the energy change of the confined state is diminished. In addition, the NDR region of I-V characteristics curve can be moved by controlling the biasing voltage, and the wave form of the curve maintains its original form.

Abstract: A lateral THETA device formed of a sandwich of first and second layers of semiconductor material forming a heterojunction therebetween and a two dimensional carrier gas in the second layer. First and second spaced electrodes are disposed on the surface of the first layer for inducing first and second potential barriers to the flow of charge carriers in the carrier gas. Ohmic contacts are deposited in the base region defined between the electrodes and in the emitter and collector regions defined on opposing sides of the electrodes. The width of the first electrode is formed narrow enough so that the first potential barrier beneath the electrode permits tunnelling of charge carriers into the base region. The width of the second electrode is wide enough so that the second potential barrier prevents tunnelling. Electrons tunnelling through the first barrier are hot and ballistically move through the base region to the collector.

Abstract: A semiconductor body (2) has an active region (6) of n conductivity type formed of a material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum and an injector region (9) defining a potential barrier (P) to the flow of electrons into the active region (6) of a height such that, in operation of the device, electrons with sufficient energy to surmount the barrier (P) provided by the injector region (9) are emitted into the active region (6) with an energy comparable to that of the at least one relatively high mass, low mobility conduction band satellite minimum. An electron containing well region (10a, 10b) of a material different from that of the active region (6) and of the injector region (9) is provided between the injector region (9) and the active region (6) for inhibiting the spread of a depletion region into the active region (6) during operation of the device.

Abstract: A quantum effect device which operates in a mesoscopic region and eliminates the need for making monochromatic electron waves for the operation and moreover can operate in a high temperature region. The quantum effect device comprises a first waveguide for connecting a first region and a second region, wherein carriers are injected into the first region and emitted from the second region, a second waveguide being branched off from the center of the first waveguide and connected to a third region, and a control region being formed in the branch part of the first and second waveguides for controlling a potential barrier. When the potential barrier is low, the control region emits carriers on the first waveguide from the second region and when the potential barrier is high, the control region leads carriers into the second waveguide from the first waveguide by quantum-mechanical reflection for emitting the carriers from the third region.

Abstract: A heterojunction semiconductor device includes an unipolar transistor having, a collector layer, a base layer, a collector side barrier layer provided between the collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between the base layer and the emitter layer. The emitter side barrier layer has a thickness for tunneling a carrier from the emitter and base layer and injecting the carrier into the base layer according to a predetermined voltage applied between the emitter and base layers, the base layer includes a superlattice structure. The superlattice structure includes a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.

Abstract: A quantum wire embedded in another material or a quantum wire which is free standing. Specifically, the quantum wire structure is fabricated such that a quantum well semiconductor material, for example Gallium Arsenide (GaAS), is embedded in a quantum barrier semiconductor material, for example Aluminum Arsenide (AlAs). Preferably, the entire quantum wire structure is engineered to form multiple subbands and is limited to a low dimensional quantum structure. The dimensions of the quantum wire structure are preferably around 150.times.250 .ANG.. This structure has a negative absolute conductance at a predetermined voltage and temperature. As a result of the resonant behavior of the density of states, the rates of electron scattering in the passive region (acoustic phonon and ionized impurity scattering as well as absorption of optical phonons) decrease dramatically as the electron kinetic energy increases.

Abstract: A heterojunction bipolar transistor with an exponentially graded base doping is disclosed, in addition to a technique for fabricating the transistor. In accordance with the preferred embodiment, the transistor employs a base with an exponentially graded Beryllium doping which varies from 5.times.10.sup.19 cm.sup.-3 at the base-emitter junction to 5.times.10.sup.18 cm.sup.-3 at the base-collector junction. The built-in field due to the exponentially graded doping profile significantly reduces base transit time despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping, the cut off frequency is increased and the maximum frequency of oscillation is also increased. Also, consistently higher common emitter current gain results even though the Gummel number is twice as high and the base resistance is reduced by 40%.

Abstract: A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).

Abstract: A room temperature high speed transistor that does not suffer deleterious effects from plasmon scattering. The transistor of the present invention comprises a semiconducting base region having a type of majority carriers and sub-band ordering associated with the majority carriers. The transistor further comprises a semiconducting collector region contacting the base region at a collector-base heterojunction, the semiconducting collector region having the same type of majority carriers as the semiconducting base region and having a sub-band ordering different than that of the base region. The transistor further comprises a semiconducting emitter region contacting the base region at an emitter-base heterojunction, the semiconducting emitter region having the same type of majority carriers as the semiconducting base region. In active operation of the transistor of the present invention, carriers are injected from a main sub-band in the emitter region into a satellite sub-band the base region.

Abstract: A method for electrically isolating an integrated circuit element in an acoustic charge transport device comprises the steps of providing a semi-insulating substrate; providing an epitaxial layer with a thickness and carrier concentration appropriate for an ACT device; providing a circuit element semiconductor layer in the epitaxial layer for construction of an integrated circuit element, the layer having a thickness substantially less than the thickness of the epitaxial layer and having a carrier concentration substantially greater than the ACT epitaxial layer; laterally isolating the semiconductor layer from other regions of the ACT epitaxial layer; and bombarding the semiconductor layer with protons at a dose sufficient to provide significant vertical electrical isolation from underlying regions of the epitaxial layer semi-insulating with minimal detrimental effect on the electrical characteristics of the semiconductor layer.

Abstract: A solid state, electronic, optical transition device includes a multiple-layer structure of semiconductor material which supports substantially ballistic electron/hole transport at energies above/below the conduction/valance band edge. The multiple layer structure of semiconductor material includes a Fabry-Perot filter element for admitting electrons/holes at a first quasibound energy level above/below the conduction/valance band edge, and for depleting electrons/holes at a second quasibound energy level which is lower/higher than the first energy level. Such an arrangement allows common semiconductor material to be used to produce emitters and detectors and other devices which can operate at any of selected frequencies over a wide range of frequencies.

Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.

Abstract: In a semiconductor device, a channel layer of an undoped semiconductor material passes carriers therethrough ballistically, a carrier injection part injects the carriers into the channel layer with directivity to form a quantum mechanical wave of carriers, a carrier collection part provided on the channel layer recovers the carriers; a carrier drainage part provided on the channel layer absorbs the carriers that have been scattered; a carrier control part controls the flow of the carriers from the carrier injection part to the carrier collection part; and a potential control layer, provided adjacent to the channel layer, controls the potential level of the channel layer such that the potential level is uniform throughout the channel layer.