Combined With Insulated Gate Field Effect Transistor (igfet) Patents (Class 257/262)
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Publication number: 20140231829Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.Type: ApplicationFiled: September 30, 2011Publication date: August 21, 2014Inventors: Takamitsu Kanazawa, Satoru Akiyama
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Patent number: 8810040Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.Type: GrantFiled: November 20, 2012Date of Patent: August 19, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kentaro Kaneko, Kazuhiro Kobayashi
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Patent number: 8803241Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.Type: GrantFiled: June 29, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jr-Jung Lin, Chih-Han Lin, Ming-Ching Chang
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Patent number: 8803205Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
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Patent number: 8785988Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.Type: GrantFiled: January 11, 2013Date of Patent: July 22, 2014Assignee: Macronix International Co., Ltd.Inventors: Wing-Chor Chan, Li-Fan Chen, Chen-Yuan Lin
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Patent number: 8785987Abstract: An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.Type: GrantFiled: July 22, 2011Date of Patent: July 22, 2014Assignee: AccoInventor: Denis Masliah
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Publication number: 20140197466Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Applicant: MACRONIX INTERNATIONAL CO., LTDInventors: Wing-Chor Chan, Li-Fan Chen, Chen-Yuan Lin
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Patent number: 8766367Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.Type: GrantFiled: June 30, 2011Date of Patent: July 1, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street
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Patent number: 8736069Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.Type: GrantFiled: August 23, 2012Date of Patent: May 27, 2014Assignee: Macronix International Co., Ltd.Inventors: Chiajung Chiu, Guanru Lee
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Publication number: 20140117415Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.Type: ApplicationFiled: October 29, 2013Publication date: May 1, 2014Applicant: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Rongyao Ma, Tiesheng Li, Lei Zhang, Daping Fu
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Publication number: 20140117416Abstract: A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer.Type: ApplicationFiled: October 31, 2013Publication date: May 1, 2014Inventors: Lei Zhang, Tiesheng Li, Rongyao Ma, Daping Fu
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Patent number: 8698229Abstract: Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.Type: GrantFiled: May 31, 2011Date of Patent: April 15, 2014Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler
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Patent number: 8691638Abstract: A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.Type: GrantFiled: December 10, 2010Date of Patent: April 8, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng Tan, Chunshan Yin
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Patent number: 8680538Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.Type: GrantFiled: February 12, 2008Date of Patent: March 25, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Kenichi Ohtsuka, Naruhisa Miura, Yoshinori Matsuno, Masayuki Imaizumi
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Patent number: 8652916Abstract: A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.Type: GrantFiled: March 22, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., Paul Chang, Kangguo Cheng, Chengwen Pei, William R. Tonti
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Patent number: 8653510Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.Type: GrantFiled: December 17, 2010Date of Patent: February 18, 2014Assignee: SRI InternationalInventors: John Hodges, Jr., Marc Rippen, Carl Biver, Jr.
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Publication number: 20140001517Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.Type: ApplicationFiled: March 1, 2012Publication date: January 2, 2014Applicant: K.EKLUND INNOVATIONInventors: Klas-Hakan Eklund, Lars Vestling
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Patent number: 8618557Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.Type: GrantFiled: February 14, 2012Date of Patent: December 31, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Koh Yoshikawa
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Publication number: 20130335134Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.Type: ApplicationFiled: June 4, 2013Publication date: December 19, 2013Inventors: Takamitsu KANAZAWA, Satoru AKIYAMA
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Patent number: 8610182Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.Type: GrantFiled: April 5, 2012Date of Patent: December 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
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Publication number: 20130313618Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20130307606Abstract: A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current.Type: ApplicationFiled: March 13, 2013Publication date: November 21, 2013Applicant: Leadtrend Technology Corp.Inventors: Chi-Pin Chen, Yung-Hao Lin, Ming-Nan Chuang, Ming-Ying Kuo
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Publication number: 20130248945Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.Type: ApplicationFiled: March 14, 2013Publication date: September 26, 2013Inventors: Alexandre G. Bracale, Denis A. Masliah
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Publication number: 20130248946Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.Type: ApplicationFiled: May 17, 2013Publication date: September 26, 2013Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)Inventor: Mieno FUMITAKE
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Patent number: 8513713Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.Type: GrantFiled: May 10, 2012Date of Patent: August 20, 2013Assignee: Analog Devices, Inc.Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson, William Allan Lane
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Patent number: 8502280Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.Type: GrantFiled: April 13, 2011Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes
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Publication number: 20130187160Abstract: An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Inventor: Tiesheng LI
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Patent number: 8492747Abstract: A transistor includes at least three terminals comprising a gate electrode, a source electrode and a drain electrode, an insulating layer disposed on a substrate, and a semiconductor layer disposed on the substrate, wherein a current which flows between the source electrode and the drain electrode is controlled by application of a voltage to the gate electrode, where the semiconductor layer includes a graphene layer and at least one of a metal atomic layer and a metal ion layer, and where the metal atomic layer or the metal ion layer is interposed between the graphene layer and the insulating layer.Type: GrantFiled: October 25, 2010Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-young Choi, Hyeon-jin Shin, Seon-mi Yoon, Won-mook Choi
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Patent number: 8441046Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.Type: GrantFiled: October 31, 2010Date of Patent: May 14, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Anup Bhalla
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Patent number: 8426279Abstract: According to one exemplary embodiment, an asymmetric transistor includes a channel region having a drain-side channel portion and a source-side channel portion. The asymmetric transistor can be an asymmetric MOSFET. The source-side channel portion can comprise silicon, for example. The drain-side channel portion can comprise germanium, for example. The asymmetric transistor comprises a vertical heterojunction situated between the drain-side channel portion and the source-side channel portion. According to this exemplary embodiment, the bandgap of the source-side channel portion is higher than the bandgap of the drain-side channel portion and the carrier mobility of the drain-side channel portion is higher than the carrier mobility of the source-side channel portion. The transistor can further include a gate oxide layer situated over the drain-side channel portion and the source-side channel portion, and can also include a gate situated over the gate oxide layer.Type: GrantFiled: August 29, 2006Date of Patent: April 23, 2013Assignee: GLOBALFOUNDRIES Inc.Inventor: Qiang Chen
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Patent number: 8415719Abstract: A low gate charging rectifier having a MOS structure and a P-N junction and a manufacturing method thereof are provided. The low gate charging rectifier is a combination of an N-channel MOS structure and a lateral P-N junction diode. A portion of the gate-covering region is replaced by a thicker dielectric layer or a low conductivity polysilicon layer. In a forward mode, the N-channel MOS structure and the P-N junction diode are connected with each other in parallel. Under this circumstance, like the Schottky diode, the low gate charging rectifier has low forward voltage drop and rapid switching speed. Whereas, in a reverse mode, the leakage current is pinched off and the N-channel is shut off by the depletion region of the P-N junction diode, so that the low gate charging rectifier has low leakage current.Type: GrantFiled: July 7, 2011Date of Patent: April 9, 2013Inventor: Tzu-Hsiung Chen
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Publication number: 20130037864Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Viraj Y. Sardesai, Robert C. Wong
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Patent number: 8373204Abstract: A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.Type: GrantFiled: October 29, 2010Date of Patent: February 12, 2013Assignee: IMECInventors: Kai Cheng, Stefan Degroote
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Patent number: 8373208Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.Type: GrantFiled: April 30, 2010Date of Patent: February 12, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
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Patent number: 8362528Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.Type: GrantFiled: November 3, 2009Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Min-Hwa Chi
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Patent number: 8354292Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: GrantFiled: March 6, 2012Date of Patent: January 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 8354698Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.Type: GrantFiled: July 1, 2010Date of Patent: January 15, 2013Assignee: System General Corp.Inventors: Hsin-Chih Chiang, Han-Chung Tai
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Patent number: 8350291Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.Type: GrantFiled: September 29, 2011Date of Patent: January 8, 2013Assignee: Intel CorporationInventors: Mantu K. Hudait, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Jack T. Kavalieros
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Publication number: 20120305993Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.Type: ApplicationFiled: May 31, 2012Publication date: December 6, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
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Patent number: 8304780Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.Type: GrantFiled: June 9, 2010Date of Patent: November 6, 2012Assignee: Kovio, Inc.Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
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Patent number: 8288824Abstract: A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.Type: GrantFiled: October 27, 2011Date of Patent: October 16, 2012Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Hiromitsu Tanabe, Kenji Kouno
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Patent number: 8278682Abstract: A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side.Type: GrantFiled: May 26, 2011Date of Patent: October 2, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Koh Yoshikawa, Kenichi Iguchi
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Patent number: 8269262Abstract: A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.Type: GrantFiled: August 10, 2007Date of Patent: September 18, 2012Assignee: SS SC IP LLCInventors: Igor Sankin, Joseph Neil Merrett
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Patent number: 8269263Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.Type: GrantFiled: May 12, 2008Date of Patent: September 18, 2012Assignee: Vishay-SiliconixInventors: Jian Li, King Owyang
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Publication number: 20120228677Abstract: A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused.Type: ApplicationFiled: March 7, 2012Publication date: September 13, 2012Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 8264015Abstract: A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).Type: GrantFiled: April 3, 2009Date of Patent: September 11, 2012Inventor: Klas-Håkan Eklund
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Publication number: 20120205724Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.Type: ApplicationFiled: April 10, 2012Publication date: August 16, 2012Inventors: Alexandre G. Bracale, Denis A. Masliah
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Publication number: 20120199885Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.Type: ApplicationFiled: April 23, 2012Publication date: August 9, 2012Applicant: POWER INTEGRATIONS, INC.Inventors: Sujit Banerjee, Martin H. Manley
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Patent number: 8222649Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.Type: GrantFiled: November 17, 2006Date of Patent: July 17, 2012Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
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Patent number: 8222681Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.Type: GrantFiled: December 21, 2011Date of Patent: July 17, 2012Assignee: Infineon Technologies Austria AGInventors: Hans-Joachim Schulze, Francisco Javier Santos Rodriguez