Abstract: A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Abstract: A semiconductor device comprises an insulated gate field effect transistor and a protection diode. The insulated gate field effect transistor has a gate electrode formed on a gate insulating film, a source and a drain. The source and the drain are formed in a first area of a semiconductor substrate. A first silicon oxide film is formed on a second area of the semiconductor substrate adjacent to the first area. The first silicon oxide film is thicker than the gate insulating film and contains larger amount of impurities than the gate insulating film. A poly-silicon layer is formed on the first silicon oxide film. The protection diode has a plurality of PN-junctions formed in the poly-silicon layer. The protection diode is connected between the gate electrode and the source so as to prevent breakdown of the gate insulating film.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and electrically insulated from the semiconductor substrate. A photodiode is formed in the semiconductor substrate on one side of the transfer gate, and a floating diffusion region is formed on the semiconductor substrate in the other side of the transfer gate. A local impurity region of a first conductivity type is formed to be partially overlapped the transfer gate between the photodiode and the floating diffusion region.

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

Abstract: A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.

Abstract: A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.

Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract: A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).

Abstract: A low gate charging rectifier having a MOS structure and a P-N junction and a manufacturing method thereof are provided. The low gate charging rectifier is a combination of an N-channel MOS structure and a lateral P-N junction diode. A portion of the gate-covering region is replaced by a thicker dielectric layer or a low conductivity polysilicon layer. In a forward mode, the N-channel MOS structure and the P-N junction diode are connected with each other in parallel. Under this circumstance, like the Schottky diode, the low gate charging rectifier has low forward voltage drop and rapid switching speed. Whereas, in a reverse mode, the leakage current is pinched off and the N-channel is shut off by the depletion region of the P-N junction diode, so that the low gate charging rectifier has low leakage current.

Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.

Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.

Abstract: A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.

Abstract: Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80?) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80?) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801?, 801-1, 801-2, 801-3) conveniently provides this switching function.

Abstract: The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench.

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively.

Abstract: A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.

Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Abstract: A hybrid packaged gate controlled semiconductor switching device (HPSD) has an insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die. The RGT gate and source are electrically connected to the IGT source and drain respectively. The HPSD includes a package base with package terminals for interconnecting the HPSD to external environment. The IGT is die bonded atop the package base. The second semiconductor die is formed upon a composite semiconductor epi layer overlaying an electrically insulating substrate (EIS) thus creating a RGT die. The RGT die is stacked and bonded atop the IGT die via the EIS. The IGT, RGT die and package terminals are interconnected with bonding wires. Thus, the HPSD is a stacked package of IGT die and RGT die with reduced package footprint while allowing flexible placements of device terminal electrodes on the IGT.

Abstract: A display device having improved aperture ratio includes a switching element, a liquid crystal capacitor and a storage capacitor. The switching element is electrically connected to a gate line and a source line crossing each other. The liquid crystal capacitor has a pixel electrode electrically connected to the switching element through a first contact to define a pixel area. The storage capacitor has a storage line partially overlapping the source line. The storage line is electrically connected to the pixel electrode through a second contact hole.

Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 ?m greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 ?m greater than LC.

Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Abstract: A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).

Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer.

Abstract: A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The protective layer covers the active device and a part of the insulation layer. The protective layer has a contact window exposing the active device. The pixel electrode is disposed on the protective layer and electrically connected to the active device through the contact window. The patterned semiconductor layer is disposed on the insulation layer above the common line pattern. The patterned semiconductor layer is located between the common line pattern and the pixel electrode.

Abstract: A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: A field effect transistor includes a nitride semiconductor layer; an InxAlyGa1-x-yN layer (wherein 0<x<1, 0<y<1 and 0<x+y<1) formed on the nitride semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the InxAlyGa1-x-yN layer. The lower ends of the conduction bands of the nitride semiconductor layer and the InxAlyGa1-x-yN layer are substantially continuous on the interface therebetween.

Abstract: A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.

Abstract: A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.

Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.