Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

Abstract: A semiconductor module has a heat conduction section provided between a multilayer substrate, on which semiconductor chips are mounted, and a cooler. The heat conduction section includes a frame and an opening, and the opening has a grease portion which is provided partly in the opening and is in contact with the multilayer substrate and the cooler, and a space portion which is provided between the grease portion and the frame in a partial and band-shaped manner.

Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.

Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

Abstract: The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a gate structure overlying a front-side surface of a first substrate. The first substrate has a back-side surface opposite the front-side surface. A first source/drain structure overlies the first substrate and is laterally adjacent to the grate structure. A power rail is embedded in the first substrate and directly underlies the first source/drain structure. A first source/drain contact continuously extends from the first source/drain structure to the power rail. The first source/drain contact electrically couples the first source/drain structure to the power rail.

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

Abstract: A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.

Abstract: This disclosure is directed to systems and methods for maskless gap integration in interconnects having one or more vias above one or more interconnect lines (for example, metal interconnect lines). In various embodiments, the systems and methods described in the disclosure may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines from electrical shorting during subsequent metal layer depositions in a fabrication sequence of the interconnects. Further, in various embodiments, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps, for example, without the need for additional lithography steps.

Abstract: A structure and a method for fabricating a bottom electrode for an integrated circuit device are described. A first dielectric layer is provided over a substrate and the first dielectric layer has a recess. A bottom electrode is formed over the recess. The bottom electrode consists of a microstud layer disposed completely within the recess of the dielectric and conforming to the recess, a bottom pedestal disposed on a top surface of the microstud and a top pedestal on a top surface of the bottom pedestal. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A conductive element of the integrated circuit device is formed on a top surface of the bottom electrode. A first portion of the bottom electrode is disposed in and conforms to the recess. A second portion of the bottom electrode and the conductive element are conical sections.

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.

Abstract: An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

Abstract: A light emitting module including a circuit carrier and a plurality of light emitting devices is provided. The circuit carrier includes a first circuit layer, a second circuit layer, a dielectric layer and a plurality of conductive vias. The first circuit layer and the second circuit layer are located at two opposite sides of the dielectric layer. The conductive vias pass through the dielectric layer and two opposite end portions of each of the conductive vias are respectively connected to the first circuit layer and the second circuit layer. The light emitting devices are electrically bonded to the first circuit layer. Moreover, the light emitting devices are disposed in a device disposing area of the circuit carrier and the conductive vias are arranged outside the device disposing area. A display device is also provided.

Abstract: A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

Abstract: A component assembly includes a body having an electronics component mounted on a first face of the body. A light emitting diode is mounted on a first portion of the first face. A top plate is attached to the body and covers the light emitting diode and the electronics component. The top plate includes: a first cavity having the electronics component positioned within the first cavity; and a first support area homogeneously connected to the top plate and extending from the top plate to directly contact the body outside of the cavity to provide support for the top plate and to mitigate against collapse of the cavity.

Abstract: Roughness of an end surface portion of a step shape can be decreased. An etching method includes a first etching process and a second etching process. In the first etching process, etching is performed on a processing target object, which has a silicon-containing film thereon and a photoresist formed on a surface of the silicon-containing film and which is placed in a processing vessel, to etch the silicon-containing film by using the photoresist as a mask. In the second etching process, a first processing gas containing oxygen and halogen is supplied into the processing vessel, or a third processing gas containing the oxygen is supplied into the processing vessel after a second processing gas containing the halogen is supplied into the processing vessel. The first etching process and the second etching process are repeated a multiple number of times.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.

Abstract: Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.

Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.

Abstract: A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed radially extending around a central axis of the opening; arranging in the recesses separate ring-shaped strips made of a material catalyzing the growth of carbon nanotubes; and growing carbon nanotubes in the opening from said ring-shaped strips.

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract: A manufacturing method of a semiconductor module includes: sealing an assembly with resin, the assembly including a semiconductor chip, a heat-dissipation plate on the semiconductor chip, and multiple terminals, such that the resin includes a first surface, a second surface located opposite to the first surface, and a side surface, a groove extends in the side surface from the first surface to the second surface, an inner surface of the groove includes a first tapered surface, and a second tapered surface provided between the first tapered surface and the first surface, the second tapered surface inclining toward the first surface at a greater inclination angle than an inclination angle of the first tapered surface; and cutting the first surface within an area located on a first surface side from a boundary between the first tapered surface and the second tapered surface such that the heat-dissipation plate exposes.

Abstract: A semiconductor device includes: a semiconductor substrate through which a via hole is formed from a back surface to a front surface of the semiconductor substrate; an electrode provided on the front surface of the semiconductor substrate and closing the via hole; and a metal film provided on the back surface of the semiconductor substrate, a side wall of the via hole and a lower surface of the electrode, wherein an opening is provided in the metal film on the back surface of the semiconductor substrate, and the opening abuts on only part of a circumference of the via hole.

Abstract: A diffusion soldering method for joining an electronic component to a substrate is provided. The joining surfaces are designed such that cavities are formed in a joining gap between the component and substrate. The formation of such cavities can be provided, e.g., by depressions in a mounting surface of the component and/or in a contact surface of the substrate, the depressions being cup-shaped and/or defining channels that surround columnar structural elements, the end faces of which define the mounting surface and/or contact surface. The cavities are designed such that solder material can leak into the cavities when the component during a heating process to achieve a desired width of the joining gap. This allows for the formation of a narrow-width joining having a diffusion zone that bridges the joining gap upon soldering. In this manner, a diffusion solder connection can be produced even using standard solder.

Abstract: A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

Abstract: A semiconductor device includes: diffusion layers that are formed over a semiconductor substrate in a first direction, that are separated from one another by separation regions, and that serve as drain regions or source regions of respective transistors; a gate electrode of the transistors, which is formed in the first direction so as to straddle the diffusion layers; gate extraction wirings that are formed above the separation regions so as to sandwich therebetween the individual diffusion layers in the first direction, that are electrically coupled to the gate electrode above the separation regions, and that supply a gate signal to the gate electrode.

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

Abstract: A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.

Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.

Abstract: A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die.

Abstract: Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.

Abstract: A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces of the base material permeable by a current to the total volume of the base material is increased by a) dividing the base material perpendicularly to the direction of current into at least two segments, which are spaced from each other by an electrically conductive intermediate piece and connected both electrically and mechanically to each other, and/or b) topographical structures in or on the surface of the base material and/or c) inner porosity of at least a portion of the base material compared to a design of the base material in which the respective feature was omitted.

Abstract: A semiconductor device having a via hole whose side surface is covered with nitride metal is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials. The via hole is filled with a back metal and in side surfaces thereof is covered with the nitride metal which is heat treated at a preset temperature for a preset period. Nitrogen atoms in the nitride metal diffuse into the nitride semiconductor materials in the insulating regions and compensate nitride vacancies therein. The interface between the nitride metal and the nitride semiconductor material is converted into an altered region that shows enough resistivity to suppress currents leaking from the via hole metal to the conductive region of the nitride semiconductor material.

Abstract: Embodiments of the disclosure provide an array substrate having via-hole conductive layer and display device. The array substrate includes: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer.

Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.

Abstract: A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.

Abstract: An epitaxial structure is provided. The epitaxial structure includes a substrate, an first epitaxial layer, a second epitaxial layer, a first carbon nanotube layer and a second carbon nanotube layer. The first epitaxial layer is located on the substrate. The first carbon nanotube layer is located between the substrate and the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer. The second carbon nanotube layer is located between the first epitaxial layer and the second epitaxial layer.

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed to expose the epitaxial layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.