Microwave Integrated Circuit (e.g., Microstrip Type) Patents (Class 257/275)
  • Patent number: 10374641
    Abstract: A multiband antenna-equipped electronic device is provided. An electronic device includes a housing, a memory, an antenna for multi-band communication, a communication unit processing a radio frequency (RF) signal using the antenna, a switching unit including a first switch connected with a first point of the antenna, a second switch connected between the first switch and a second point of the antenna, a third switch connected with a third point of the antenna, a fourth switch connected between the second point and the third switch, a fifth switch connected between a first node between the first switch and the second switch and a ground, and a sixth switch connected between a second node between the third switch and the fourth switch and the ground, and a processor electrically connected with the memory, the communication unit, and the switching unit.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Sub Lim
  • Patent number: 10367258
    Abstract: An antenna device of the present disclosure includes: an antenna element that radiates a main lobe of a radio wave and one or more side lobes of the radio wave; and a radome through which the main lobe of the radio wave and the one or more side lobes of the radio wave. The radome has a focusing lens structure that focuses the main lobe of the radio wave and a diverging lens structure that diverges the one or more side lobes of the radio wave.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 30, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Hiroyoshi Tagi
  • Patent number: 10257943
    Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 9, 2019
    Assignee: STMICROELECTRONICS (GRENOVLE 2) SAS
    Inventors: David Auchere, Laurent Marechal
  • Patent number: 10236573
    Abstract: A capacitor radio frequency (RF) shielding structure may include a ground plane partially surrounding a coupling capacitor in an RF signal path. The ground plane may include a first ground plane portion extending between a positive terminal of the RF signal path and a negative terminal of the RF signal path. The ground plane may include a second ground plane portion extending between the positive terminal and the negative terminal of the RF signal path. The second ground plane portion may be opposed the first ground plane portion. The capacitor RF shielding structure may also include a patterned shielding layer electrically contacting the first ground plane portion and/or the second ground plane portion. The patterned shielding layer may electrically disconnecting a return current path over the patterned shielding layer to confine a return current to flowing over the first ground plane portion or the second ground plane portion.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Zhang Jin
  • Patent number: 10204791
    Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 12, 2019
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
  • Patent number: 9947616
    Abstract: Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction in parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact and a gate jumper extending in the first direction. The gate jumper conductively connects to the gate finger at two or more locations that are spaced apart from each other along the first direction.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 17, 2018
    Assignee: Cree, Inc.
    Inventors: Simon M. Wood, James Milligan, Mitchell Flowers, Donald Farrell
  • Patent number: 9910145
    Abstract: A wireless communication system includes a first semiconductor module and a second semiconductor module. The first semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the first semiconductor module and the antenna structure of the first semiconductor module are arranged within a common package. The semiconductor die of the first semiconductor module includes a transmitter module configured to transmit the wireless communication signal through the antenna structure of the first semiconductor module. The second semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the second semiconductor module includes a receiver module configured to receive the wireless communication signal through the antenna structure of the second semiconductor module from the first semiconductor module.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Walter Hartner
  • Patent number: 9841458
    Abstract: De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho
  • Patent number: 9805151
    Abstract: Disclosed are methods and apparatus for implementing system simulation. The method includes generating a high-order equation based on a transfer function that represents characteristics of at least one frequency-domain component in a circuit; converting the high-order equation into a state equation comprising a series of state variables, wherein the high-order equation and the state equation have corresponding coefficients for each order and state variable, and the coefficients of the state equation have a first dynamic range; and normalizing the coefficients for the state variables by adjusting each state variable with a corresponding factor to obtain a normalized state equation having normalized coefficients, wherein the normalized coefficients of the normalized state equation have a second dynamic range smaller than the first dynamic range. The method and apparatus improve accuracy of analyses for the system.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: October 31, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jimin Wen, Peng Wang
  • Patent number: 9786581
    Abstract: Embodiments of the present disclosure are directed toward through-silicon via (TSV)-based devices and associated techniques and configurations. In one embodiment, an apparatus includes a die having active circuitry disposed on a first side of the die and a second side disposed opposite to the first side, a bulk semiconductor material disposed between the first side and the second side of the die and a device including one or more of a capacitor, resistor or resonator disposed in the bulk semiconductor material, the capacitor, resistor or resonator including one or more TSV structures that extend through the bulk semiconductor material, an electrically insulative material disposed in the one or more TSV structures and an electrode material or resistor material in contact with the electrically insulative material within the one or more TSV structures.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventor: Telesphor Kamgaing
  • Patent number: 9716185
    Abstract: A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 25, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Kenichi Horiguchi, Norio Higashisaka, Shinsuke Watanabe, Toshiaki Kitano
  • Patent number: 9711862
    Abstract: A wireless device includes an antenna that has a planar shape and radiates a radio signal toward another wireless device, and a chassis housing the antenna and having an outer peripheral portion placed to face the antenna. Multiple distances between a surface of the outer peripheral portion and the antenna are non-uniform.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 18, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Suguru Fujita, Maki Nakamura
  • Patent number: 9679860
    Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 13, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Shinya Osakabe
  • Patent number: 9595515
    Abstract: A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: March 14, 2017
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 9508787
    Abstract: Two rows of resistive bodies, first resistive body and second resistive body, having slits are provided on an input matching circuit substrate. Since a high-frequency signal flows through not only the resistive bodies but also a transmission line pattern formed in the slits, the burnout of the resistive bodies can be prevented.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takaaki Yoshioka
  • Patent number: 9478463
    Abstract: A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a front-end device containing a transistor, a radio frequency (RF) device and a first interconnect structure, and a second substrate containing a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate is facing the cavity in the second substrate, and the cavity is over the RF device. Because of the cavity, the distance between the second substrate and the RF device is relatively large so that the second substrate has less impact on the performance of the RF device, thereby improving the performance of the semiconductor device.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 25, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Haiting Li, Herb He Huang, Qiang Zhou, Hongtao Ge
  • Patent number: 9362237
    Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 7, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Ward G. Fillmore, Paul J. Duval
  • Patent number: 9349863
    Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, Krishna Iyengar, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9324512
    Abstract: Various embodiments provide a single pole single throw switch. The switch may include a first terminal, a second terminal and a control terminal; a field-effect transistor having a drain connected to the first terminal, a source connected to the ground, and a gate; a bias resistor connected between the gate of the field-effect transistor and the control terminal; an inductor connected between the first terminal and the second terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 26, 2016
    Assignee: Nanyang Technological University
    Inventors: Jin He, Yue Ping Zhang
  • Patent number: 9293456
    Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Nita, Kazutaka Suzuki, Takahiro Korenari, Yoshimasa Uchinuma
  • Patent number: 9281446
    Abstract: Disclosed are a light emitting diode and a method of fabricating the same. The light emitting diode includes a GaN substrate having a plurality of through-holes; a GaN-based semiconductor stack structure placed on the substrate and including a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer; and a first electrode electrically connected to the first conductive-type semiconductor layer via the through-holes. The light emitting diode can reduce crystal defects and prevent reduction in light emitting area.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 8, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Duk Il Suh, Kyoung Wan Kim, Yeo Jin Yoon, Ji Hye Kim
  • Patent number: 9256267
    Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a voltage monitor circuit; a storage circuit storing an output target characteristic value of the voltage monitor circuit; a comparator configured to compare the output characteristic value of the voltage monitor circuit and the target characteristic value; and a switch control circuit configured to control the number of the plurality of turned-on discrete supply switches based on the comparison result of the comparator.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 9, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kenichi Kawasaki
  • Patent number: 9244515
    Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a delay monitor circuit having a delay path whose amount of delay changes in accordance with a change in the voltage value of the local power source, and whose output logical value changes in accordance with the amount of delay of the delay path; and a switch control circuit configured to control the number of the plurality of discrete supply switches based on the output logical value of the delay monitor circuit.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kenichi Kawasaki
  • Patent number: 9236478
    Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 12, 2016
    Assignees: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec, Maud Vinet
  • Patent number: 9219024
    Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 22, 2015
    Assignee: Raytheon Company
    Inventors: Ward G. Fillmore, Paul J. Duval
  • Patent number: 9103884
    Abstract: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu
  • Patent number: 9082633
    Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventor: Douglas M. Grant
  • Patent number: 9041074
    Abstract: A multilayered antenna package including: a radio frequency integrated circuit (RFIC) interface layer that is configured to transmit a radio frequency (RF) signal; a first dielectric layer that is disposed on the RFIC interface layer; a coplanar waveguide layer that is disposed on the first dielectric layer and is configured to receive the RF signal transmitted by RFIC layer; a second dielectric layer disposed on the coplanar waveguide layer; and an antenna portion that is disposed on the second dielectric layer and is configured to irradiate a signal that is transmitted from the coplanar waveguide layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-bin Hong, Alexander Goudelev, Kwang-hyun Baek, Young-hwan Kim
  • Patent number: 8981433
    Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 17, 2015
    Assignee: NXP, B.V.
    Inventors: Lukas Frederik Tiemeijer, Vittorio Cuoco, Rob Mathijs Heeres, Jan Anne van Steenwijk, Marnix Bernard Willemsen, Josephus Henricus Bartholomeus van der Zanden
  • Publication number: 20140339609
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Patent number: 8866291
    Abstract: A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Raytheon Company
    Inventor: Roberto W. Alm
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8780584
    Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: July 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Chang-Sup Ryu
  • Patent number: 8742476
    Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist
  • Patent number: 8742506
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 8710548
    Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka
  • Patent number: 8461005
    Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 11, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Huan-Ting Tseng, Chun-Hsien Huang, Hung-Chin Huang, Chen-Wei Lee
  • Patent number: 8373210
    Abstract: A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mitsuru Shiozaki, Atsushi Iwata
  • Patent number: 8344430
    Abstract: In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 1, 2013
    Assignee: Raytheon Company
    Inventor: Premjeet Chahal
  • Patent number: 8338866
    Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki
  • Patent number: 8304271
    Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: November 6, 2012
    Inventors: Jenn Hwa Huang, Bruce M. Green
  • Patent number: 8288864
    Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: October 16, 2012
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Werner Perndl, Thomas Reichel
  • Publication number: 20120074470
    Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hisao KAWASAKI
  • Patent number: 8143654
    Abstract: Embodiments of apparatuses, articles, methods, and systems for a monolithic microwave integrated circuit with a substrate having a diamond layer are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: March 27, 2012
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Paul Saunier
  • Patent number: 8097906
    Abstract: A semiconductor device which has low input inductance is provided.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8089107
    Abstract: A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter ? of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter ? of the apertures.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventor: Akihiko Okubora
  • Patent number: 8084793
    Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki
  • Patent number: 8049117
    Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Won Lee, Yul Kyo Chung, In Hyung Lee
  • Patent number: 8039759
    Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Won Lee, Yul Kyo Chung, In Hyung Lee
  • Patent number: 7973630
    Abstract: A thin film magnetic device is provided, in which magnetic permeability in a high frequency range can be easily improved. Scratch-like grooves extending along an extending direction of a coil (for example, a Y-axis direction being an extending direction of a second coil part) are formed at least one side of a surface and a back of each of a lower magnetic film and an upper magnetic film. A magnetization direction of anisotropic magnetization is controlled in each of formation areas of the scratch-like grooves (formation areas of lower magnetic films and upper magnetic films), and therefore displacement (rotation) of the magnetization direction of the anisotropic magnetization is pinned by the scratch-like grooves. Consequently, certain magnetic permeability is kept even in a high frequency range. Moreover, such formation of the scratch-like grooves may not cause complexity in manufacturing process.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: July 5, 2011
    Assignee: TDK Corporation
    Inventors: Taku Masai, Ryuji Hashimoto