Abstract: A switch circuit (10) includes: a transistor (T1) switching the conductivity state between a drain terminal (D1) and a source terminal (S1) between being conductive and non-conductive; a transistor (T2) switching the conductivity state between a drain terminal (D2) and a source terminal (S2) between being conductive and non-conductive, the source terminals (S1) and (S2) being connected to a node (N1) and an input/output terminal (120), respectively, and the drain terminals (D1) and (D2) being connected to an input/output terminal (110) and the node (N1) respectively; a transistor (T3) switching the conductivity state between a drain terminal (D3) and a source terminal (S3) between being conductive and non-conductive, the drain terminal (D3) and the source terminal (S3) being arranged along a second path connecting the node (N1) and ground; and a capacitor (C1) placed in the second path and connected in series to the transistor (T3).

Abstract: An electronic package is provided and has a packaging substrate including a ground pad and a power pad. The power pad surrounds at least three directions of the ground pad so as to increase the footprint of the power pad on the packaging substrate, thereby avoiding cracking of an electronic element disposed on the packaging substrate and effectively reducing the voltage drop.

Abstract: A method of fabricating an optical structure comprises providing a layer of single crystal crystalline silicon supported on an insulating surface of a silicon substrate; using etching to remove part of the silicon layer and define a side wall which is non-parallel to the insulating surface of the substrate; forming a layer of insulating material over the side wall; forming a further layer of silicon over at least the insulating material; and removing the silicon of the further layer to a level of the layer of silicon such that the layer of insulating material occupies a slot between a portion of silicon in the layer and a portion of silicon in the further layer, a thickness of the layer of insulating material defining a width of the slot.

Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.

Abstract: Apparatus and methods for tunable filtering are provided. In certain embodiments, a tunable filter is implemented using one or more controllable capacitors formed on a semiconductor die and using one or more shielded integrated inductors formed on a secondary circuit board that attaches to a carrier circuit board. Additionally, the shielded integrated inductors are formed from patterned metallization layers of the secondary circuit board, and shielding is provided on the secondary circuit board and/or the carrier circuit board to shield the inductors from the semiconductor die and/or other components.

Abstract: A packaged radio frequency (RF) amplifier device includes a flange and a transistor die mounted to the flange. The transistor die includes an output terminal. The packaged RF amplifier device includes a first bond wire array including a first plurality of bond wires. Each bond wire in the first plurality of bond wires is electrically coupled to the output terminal of the transistor die. A first ground loop area of a first bond wire in the first plurality of bond wires is greater than a second ground loop area of a second bond wire in the first plurality of bond wires.

Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.

Abstract: A length of a zone in which a power propagation direction from an input/output terminal (P251) toward a common terminal (P20) and a power propagation direction from the common terminal (P20) toward an external connection terminal (P10) are opposite to each other is longer than a length of a zone in which a power propagation direction from an input/output terminal (P211) toward the common terminal (P20) and a power propagation direction from the common terminal (P20) toward the external connection terminal (P10) are opposite to each other. A FET (251) and a FET (211) have structures that power transferred between a drain and a source of the FET (251) in accordance with predetermined input power is greater than power transferred between a drain and a source of the FET (211).

Abstract: An RF frontend IC device includes an RF transceiver to transmit and receive RF signals and a frequency synthesizer to perform frequency synthetization to operate within a predetermined frequency band. The frequency synthesizer generates an LO signal to the RF transceiver to enable the RF transceiver to transmit and receive RF signals within the predetermined frequency band. The frequency synthesizer includes a QPG circuit to generate signals shifted in phases based on the LO signal and a phase shifting circuit to generate quadrant signals based on the signals shifted in phases. Each of the quadrant signals corresponds to one of the four quadrants in phases in the respective quadrant spaces. The phase shifting circuit includes multiple phase switches operable in a collaboration manner to further shift in phase based on the signal shifted in phases to generate the quadrant signals in proper quadrant spaces.

Abstract: Provided is an antenna apparatus which is capable of improving a gain in a specific direction, reducing an unnecessary gain in an angle range, and reducing its height. A radome 220 is formed such that a central portion positioned above a patch array antenna 130 is formed in different shapes in an outer wall and an inner wall. The central portion of the outer wall of the radome 220 is formed in a flat shape, and thus the height of the radome 120 is reduced. On the other hand, the center portion of the inner wall of the radome 220 is formed such that a radome thickness at a position of the radome 220 in directions in which an angle ? is about ?45° and about +45° when viewed from the center of the patch array antenna 130 changes stepwise.

Abstract: A display may have gate driver circuitry that include a series of linked gate driver circuits each of which has an output and has an input coupled to the output of a preceding one of the gate driver circuits. Bootstrapping circuitry may be provided in the gate driver circuitry. Each gate driver circuit may have a bootstrapping circuit that includes transistors and a bootstrapping capacitor. Bootstrapping efficiency may be enhanced by configuring the bootstrapping capacitor to reduce parasitic capacitances. A transistor in each bootstrapping circuit may have first and second source-drain terminals, and a gate terminal that lies between the first and second source-drain terminals and that runs parallel to the first and second source-drain terminals. The bootstrapping capacitor may have a first electrode formed from the gate terminal and a second electrode that overlaps the first electrode and that lies between the first and second source-drain terminals.

Abstract: The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.

Abstract: A back alignment mark on a surface of a semiconductor substrate is detected and a resist mask patterned into a circuit pattern corresponding to a surface element structure is formed on a back of the semiconductor substrate. Detection of the back alignment mark is performed by using a detector opposing the back of the semiconductor substrate and measuring contrast based on the intensity of reflected infrared light irradiated from the back of the semiconductor substrate. The back alignment mark is configured by a step formed by the surface of the semiconductor substrate and bottoms of trenches formed from the surface of the semiconductor substrate. A polysilicon film is embedded in the trenches. The back alignment mark has, for example, a cross-shaped planar layout in which three or more trenches are disposed in a direction parallel to the surface of the semiconductor substrate.

Abstract: A multiband antenna-equipped electronic device is provided. An electronic device includes a housing, a memory, an antenna for multi-band communication, a communication unit processing a radio frequency (RF) signal using the antenna, a switching unit including a first switch connected with a first point of the antenna, a second switch connected between the first switch and a second point of the antenna, a third switch connected with a third point of the antenna, a fourth switch connected between the second point and the third switch, a fifth switch connected between a first node between the first switch and the second switch and a ground, and a sixth switch connected between a second node between the third switch and the fourth switch and the ground, and a processor electrically connected with the memory, the communication unit, and the switching unit.

Abstract: An antenna device of the present disclosure includes: an antenna element that radiates a main lobe of a radio wave and one or more side lobes of the radio wave; and a radome through which the main lobe of the radio wave and the one or more side lobes of the radio wave. The radome has a focusing lens structure that focuses the main lobe of the radio wave and a diverging lens structure that diverges the one or more side lobes of the radio wave.

Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.

Abstract: A capacitor radio frequency (RF) shielding structure may include a ground plane partially surrounding a coupling capacitor in an RF signal path. The ground plane may include a first ground plane portion extending between a positive terminal of the RF signal path and a negative terminal of the RF signal path. The ground plane may include a second ground plane portion extending between the positive terminal and the negative terminal of the RF signal path. The second ground plane portion may be opposed the first ground plane portion. The capacitor RF shielding structure may also include a patterned shielding layer electrically contacting the first ground plane portion and/or the second ground plane portion. The patterned shielding layer may electrically disconnecting a return current path over the patterned shielding layer to confine a return current to flowing over the first ground plane portion or the second ground plane portion.

Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.

Abstract: Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction in parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact and a gate jumper extending in the first direction. The gate jumper conductively connects to the gate finger at two or more locations that are spaced apart from each other along the first direction.

Abstract: A wireless communication system includes a first semiconductor module and a second semiconductor module. The first semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the first semiconductor module and the antenna structure of the first semiconductor module are arranged within a common package. The semiconductor die of the first semiconductor module includes a transmitter module configured to transmit the wireless communication signal through the antenna structure of the first semiconductor module. The second semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the second semiconductor module includes a receiver module configured to receive the wireless communication signal through the antenna structure of the second semiconductor module from the first semiconductor module.

Abstract: De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure.

Abstract: Disclosed are methods and apparatus for implementing system simulation. The method includes generating a high-order equation based on a transfer function that represents characteristics of at least one frequency-domain component in a circuit; converting the high-order equation into a state equation comprising a series of state variables, wherein the high-order equation and the state equation have corresponding coefficients for each order and state variable, and the coefficients of the state equation have a first dynamic range; and normalizing the coefficients for the state variables by adjusting each state variable with a corresponding factor to obtain a normalized state equation having normalized coefficients, wherein the normalized coefficients of the normalized state equation have a second dynamic range smaller than the first dynamic range. The method and apparatus improve accuracy of analyses for the system.

Abstract: Embodiments of the present disclosure are directed toward through-silicon via (TSV)-based devices and associated techniques and configurations. In one embodiment, an apparatus includes a die having active circuitry disposed on a first side of the die and a second side disposed opposite to the first side, a bulk semiconductor material disposed between the first side and the second side of the die and a device including one or more of a capacitor, resistor or resonator disposed in the bulk semiconductor material, the capacitor, resistor or resonator including one or more TSV structures that extend through the bulk semiconductor material, an electrically insulative material disposed in the one or more TSV structures and an electrode material or resistor material in contact with the electrically insulative material within the one or more TSV structures.

Abstract: A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.

Abstract: A wireless device includes an antenna that has a planar shape and radiates a radio signal toward another wireless device, and a chassis housing the antenna and having an outer peripheral portion placed to face the antenna. Multiple distances between a surface of the outer peripheral portion and the antenna are non-uniform.

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

Abstract: A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing.

Abstract: Two rows of resistive bodies, first resistive body and second resistive body, having slits are provided on an input matching circuit substrate. Since a high-frequency signal flows through not only the resistive bodies but also a transmission line pattern formed in the slits, the burnout of the resistive bodies can be prevented.

Abstract: A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a front-end device containing a transistor, a radio frequency (RF) device and a first interconnect structure, and a second substrate containing a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate is facing the cavity in the second substrate, and the cavity is over the RF device. Because of the cavity, the distance between the second substrate and the RF device is relatively large so that the second substrate has less impact on the performance of the RF device, thereby improving the performance of the semiconductor device.

Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

Abstract: Various embodiments provide a single pole single throw switch. The switch may include a first terminal, a second terminal and a control terminal; a field-effect transistor having a drain connected to the first terminal, a source connected to the ground, and a gate; a bias resistor connected between the gate of the field-effect transistor and the control terminal; an inductor connected between the first terminal and the second terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground.

Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.

Abstract: Disclosed are a light emitting diode and a method of fabricating the same. The light emitting diode includes a GaN substrate having a plurality of through-holes; a GaN-based semiconductor stack structure placed on the substrate and including a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer; and a first electrode electrically connected to the first conductive-type semiconductor layer via the through-holes. The light emitting diode can reduce crystal defects and prevent reduction in light emitting area.

Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a voltage monitor circuit; a storage circuit storing an output target characteristic value of the voltage monitor circuit; a comparator configured to compare the output characteristic value of the voltage monitor circuit and the target characteristic value; and a switch control circuit configured to control the number of the plurality of turned-on discrete supply switches based on the comparison result of the comparator.

Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a delay monitor circuit having a delay path whose amount of delay changes in accordance with a change in the voltage value of the local power source, and whose output logical value changes in accordance with the amount of delay of the delay path; and a switch control circuit configured to control the number of the plurality of discrete supply switches based on the output logical value of the delay monitor circuit.

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.

Abstract: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.

Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.

Abstract: A multilayered antenna package including: a radio frequency integrated circuit (RFIC) interface layer that is configured to transmit a radio frequency (RF) signal; a first dielectric layer that is disposed on the RFIC interface layer; a coplanar waveguide layer that is disposed on the first dielectric layer and is configured to receive the RF signal transmitted by RFIC layer; a second dielectric layer disposed on the coplanar waveguide layer; and an antenna portion that is disposed on the second dielectric layer and is configured to irradiate a signal that is transmitted from the coplanar waveguide layer.

Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract: A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.