Significant Semiconductor Chemical Compound In Bulk Crystal (e.g., Gaas) Patents (Class 257/289)
  • Patent number: 10453841
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 10332975
    Abstract: Provided is a group 13 nitride epitaxial substrate with which the HEMT device having superior characteristics can be manufactured. This epitaxial substrate is provided with: a base substrate composed of SiC and having a main surface with a (0001) plane orientation; a nucleation layer formed on one main surface of the base substrate and composed of AlN; an electron transit layer formed on the nucleation layer and composed of a group 13 nitride with the composition AlyGa1-yN (0?y<1); and a barrier layer formed on the electron transit layer and composed of a group 13 nitride with the composition InzAl1-zN (0.13?z?0.23) or AlwGa1-wN (0.15?w?0.35). The (0001) plane of the base substrate has an off angle of 0.1° or more and 0.5° or less, and an intermediate layer composed of a group 13 nitride with the composition AlxGa1-xN (0.01 ?x?0.4) is further provided between the nucleation layer and the electron transit layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 25, 2019
    Assignee: NGK INSULATORS, LTD.
    Inventors: Mikiya Ichimura, Sota Maehara, Yoshitaka Kuraoka
  • Patent number: 10283349
    Abstract: A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y2O3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuanhsiung Chen, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin
  • Patent number: 10224245
    Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Lin, Chien-Tai Chan, Hsien-Chin Lin, Shyue-Shyh Lin
  • Patent number: 10134628
    Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae Song, Seunggeol Nam, Seongjun Park, Keunwook Shin, Hyeonjin Shin, Jaeho Lee, Changseok Lee, Yeonchoo Cho
  • Patent number: 10049870
    Abstract: To inhibit excessive oxidation and increase oxidation resistance of a polysilicon film on a substrate during recovery process, an oxygen-containing silicon layer present on the substrate is modified into a silicon oxynitride layer or a silicon nitride layer with high nitrogen concentration prior to the recovery process by heating the substrate and supplying active species containing nitrogen radicals and hydrogen radicals for increasing nitrogen content in the silicon oxynitride layer or the silicon nitride layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 14, 2018
    Assignee: Kokusai Electric Corporation
    Inventor: Akito Hirano
  • Patent number: 9934972
    Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: April 3, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Victorina Poenariu, Gerald Reinwald, Roland Rupp, Gerald Unegg
  • Patent number: 9911676
    Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: March 6, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Michael E. Givens, Qi Xie, Xiaoqiang Jiang, Petri Raisanen, Pauline Calka
  • Patent number: 9893146
    Abstract: A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and a drift region formed by a series of P-type and N-type implants, respectively. The implant doses and depths are tuned so that the highest concentration gradient of the body-drift junction is formed below the surface, which suppresses the injection and trapping of hot holes in the device drain-gate oxide region vicinity, and the associated device performance changes, during operation in breakdown.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 13, 2018
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung, Ji-Hyoung Yoo
  • Patent number: 9869033
    Abstract: A crystal has a diameter of 1 cm or more and shows a strongest peak in cathode luminescent spectrum at a wavelength of 360 nm in correspondence to a band edge.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 16, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventors: Seiji Sarayama, Masahiko Shimada, Hisanori Yamane, Hirokazu Iwata
  • Patent number: 9831320
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9806180
    Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
  • Patent number: 9793375
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9768075
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Sean Teehan
  • Patent number: 9761666
    Abstract: The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mark van Dal, Gerben Doornbos, Georgios Vellianitis, Tsung-Lin Lee, Feng Yuan
  • Patent number: 9748235
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Patent number: 9741832
    Abstract: Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Uygar Avci, Dmitri Nikonov, Ian Young
  • Patent number: 9728633
    Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer having a main surface, the main surface being provided with a trench which has a bottom portion and a sidewall inclined with respect to the main surface; a gate insulating film covering each of the bottom portion and the sidewall; a gate electrode provided at least on the gate insulating film; and an upper insulating film provided on the main surface and having a part which protrudes into the trench.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: August 8, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda, Yu Saitoh
  • Patent number: 9711396
    Abstract: In some aspects, methods of forming a metal chalcogenide thin film are provided. According to some methods, a metal chalcogenide thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase chalcogen reactant. In some aspects, methods of forming three-dimensional structure on a substrate surface are provided. In some embodiments, the method includes forming a metal chalcogenide dielectric layer between a substrate and a conductive layer. In some embodiments the method includes forming an MIS-type contact structure including a metal chalcogenide dielectric layer.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 18, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Michael Eugene Givens, Jacob Huffman Woodruff, Qi Xie, Jan Willem Maes
  • Patent number: 9685322
    Abstract: The present disclosure relates to a method (100) for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing (102) a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX3. X is selected from H, Cl, O—CH3, O—C2H5, and O—C3H2, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing (107) the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing (108) a layer on the III-V semiconductor surface in the non-oxidizing environment.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: June 20, 2017
    Assignee: IMEC VZW
    Inventors: Christoph Adelmann, Silvia Armini
  • Patent number: 9666707
    Abstract: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: May 30, 2017
    Assignee: Cree, Inc.
    Inventors: Scott Sheppard, Richard Peter Smith
  • Patent number: 9640797
    Abstract: The present invention relates to a polymer possessing a linear backbone selected from the homopolymers belonging to the family of polyfluorenes, polycarbazoles, polyanilines, polyphenylenes, polyisothionaphthenes, polyacetylenes, polyphenylene vinylenes, and copolymers thereof, said backbone bearing at least one side group possessing at least one nitroxide function. It also relates to an electrode material, an electrode and a lithium secondary battery obtained from such a polymer.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: May 2, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thibaut Gutel, Yann Kervella, Lionel Picard, Jean-Benoit Denis
  • Patent number: 9608101
    Abstract: The present invention concerns semiconductor devices comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS2, MoSe2, WS2, WSe2, MoTe2 or WTe2. Replacing a stack by only one or two 2-dimensional layer(s) of MoS2, MoSe2, WS2, or WSe2, MoTe2 or WTe2 provides an enhanced electrostatic control, low power dissipation, direct band gap and tunability.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 28, 2017
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Andras Kis, Branimir Radisavljevic
  • Patent number: 9590031
    Abstract: A fin-type field effect transistor includes a semiconductor body formed on a substrate, the semiconductor body having a top surface and a pair of laterally opposite sidewalls, and a gate electrode formed above the sidewalls and the top surface of the semiconductor body. The semiconductor body further includes a source region formed on an end portion of the semiconductor body, a drain region formed on another end portion of the semiconductor body, and a channel region formed between the source region and the drain region and surrounded by the gate electrode, wherein a doping concentration of the channel region decreases with increasing distance from the top surface and the sidewalls.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 7, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Deyuan Xiao, Hanming Wu, MengFeng Cai, Shaofeng Yu, ShiuhWuu Lee
  • Patent number: 9564526
    Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Christopher Peter D'Emic, William J. Gallagher, Effendi Leobandung, Devendra K. Sadana
  • Patent number: 9343355
    Abstract: A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae-Ho Lim, Bo-Young Song, Cheol-Ju Yun
  • Patent number: 9343544
    Abstract: MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 17, 2016
    Assignee: University of South Carolina
    Inventors: Asif Khan, Vinod Adivarahan
  • Patent number: 9275998
    Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride grown epitaxially on a substrate, a barrier, a two-dimensional hole gas in the barrier layer material at the heterointerface of the first material, and wherein the gallium-polar III-Nitride material comprises III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face of a substrate so that the gallium-polar (0001) face is the dominant face for growth of III-Nitride epitaxial layer growth material, growing a GaN epitaxial layer, doping, growing a barrier, etching, forming a contact, performing device isolation, defining a gate opening, defining gate metal, making a contact window, and depositing and defining a thick metal.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 1, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9196614
    Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride barrier material, a second material layer, a two-dimensional hole gas in the second layer, and wherein the gallium-polar material comprises one or more III-Nitride epitaxial material layers grown such that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making an inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the gallium-polar (0001) face is the dominant face, growing a nucleation layer, growing a gallium-polar epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 24, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9093548
    Abstract: Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9087902
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9029854
    Abstract: A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 12, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventor: Michael R. Seacrist
  • Patent number: 9024330
    Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 5, 2015
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Yukihiko Watanabe, Sachiko Aoi, Masahiro Sugimoto, Akitaka Soeno, Shinichiro Miyahara
  • Patent number: 9018678
    Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Soitec
    Inventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
  • Patent number: 9006799
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 14, 2015
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 9006803
    Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20150069465
    Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8896034
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8890234
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film formed on the semiconductor layer; an organic molecular layer that is formed on the tunnel insulating film, and includes first organic molecules and second organic molecules having a smaller molecular weight than the first organic molecules, the first organic molecules each including a first alkyl chain or a first alkyl halide chain having one end bound to the tunnel insulating film, the first organic molecules each including a charge storage portion bound to the other end of the first alkyl chain or the first alkyl halide chain, the second organic molecules each including a second alkyl chain or a second alkyl halide chain having one end bound to the tunnel insulating film; a block insulating film formed on the organic molecular layer; and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaya Terai, Shigeki Hattori, Hideyuki Nishizawa, Koji Asakawa, Tsukasa Tada
  • Patent number: 8823146
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8809872
    Abstract: A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Robert H. Dannard, Bruce B. Doris, Barry P. Linder, Ramachandran Muralidhar
  • Patent number: 8809928
    Abstract: An oxide semiconductor is used for a semiconductor layer of a transistor included in a semiconductor device, whereby leakage current between a source and a drain can be reduced, so that reduction in power consumption of a semiconductor device and a memory device including the semiconductor device and an improvement in characteristics of retaining stored data (electric charge) in the semiconductor device and the memory device can be achieved. Further, a drain electrode of the transistor, the semiconductor layer, and a first electrode which overlaps with the drain electrode form a capacitor, and a gate electrode is led to an overlying layer at a position which overlaps with the capacitor. Thus, the semiconductor device and the memory device including the semiconductor device can be miniaturized.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichiro Sakata
  • Publication number: 20140145250
    Abstract: A semiconductor device includes a bulk substrate having a plurality of trenches formed therein. The trenches define a plurality of semiconductor fins that are integral with the bulk semiconductor substrate. A local dielectric material is disposed in each trench and between each pair of semiconductor fins among the plurality of semiconductor fins. The semiconductor device further includes an etch resistant layer formed on the local dielectric material.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 29, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Raghavasimhan Sreenivasan
  • Patent number: 8729611
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Publication number: 20140117427
    Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: May 1, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki SAITO, Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto
  • Patent number: 8674407
    Abstract: The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0?x?1), a channel layer composed of InyGa1-yN (0?y?1) with compressive strain and a contact layer composed of AlzGa1-zN (0?z?1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 8637909
    Abstract: Various aspects of the technology provide for a converter circuit such as a dc-dc voltage converter or buck converter. The circuit includes a enhancement mode control Field Effect Transistor (FET) fabricated using gallium arsenide and an depletion mode sync FET fabricated using gallium arsenide. A drain of the sync FET may be coupled to a source of the control FET and an inductor may be coupled to the source of the control FET and the drain of the sync FET.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 28, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8575621
    Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 5, 2013
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8569811
    Abstract: Various aspects of the technology provide for clamping a transient from a transient generator in a circuit using a Field Effect Transistor (FET) including a compound semiconductor layer forming a drain coupled to the transient voltage generator, a source, and a gate. The gate and the drain may be configured to clamp voltage transients in the circuit from the transient voltage generator independent of a clamping diode between the source and the drain. The FET may be a depletion mode type fabricated using germanium or a compound semiconductor such as gallium arsenide (GaAs) or gallium nitride (GaN).
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 29, 2013
    Assignee: Sarda Technologies, Inc.
    Inventors: James L. Vorhaus, Anthony G. P. Marini
  • Patent number: 8530978
    Abstract: A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET including a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact, and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 10, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Zijian “Ray” Li, Karim S. Boutros, Shawn Burnham