Abstract: A gallium arsenide-based field effect transistor has a passivation layer of aluminum oxide below a gallium arsenide channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state gallium arsenide channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.

Abstract: A silicon carbide switching device having near ideal electrical characteristics includes an electrical insulator with an electrical permittivity greater than about ten times the permittivity of free space (.epsilon..sub.o) and more preferably greater than about fifteen times the permittivity of free space, as a gate electrode insulating region. The use of electrical insulators having high electrical permittivities relative to conventional electrical insulators such as silicon dioxide significantly improves the breakdown voltage and on-state resistance characteristics of a silicon carbide switching device to the point of near ideal characteristics, as predicted by theoretical analysis. Thus, the preferred advantages of using silicon carbide, instead of silicon, can be more fully realized.

Abstract: The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors.

Abstract: A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.

Abstract: A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Abstract: A semiconductor device including a GaAs semiconductor substrate, an insulating layer which is made of material selected from the group MgS, MgSSe and CaZnS and is formed on the GaAs substrate, and a conductive electrode formed on the insulating layer.

Abstract: A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Shottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

Abstract: A buried, gate insulator field effect transistor is disclosed. It comprises a source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are excised into this covering layer to allow electrical connection to the source, substrate, drain, and gate. The substrate and gate are vertically aligned in the resulting structure. The source, drain and gate are fabricated from a doped, semiconductor of one polarity while the substrate is fabricated from doped semiconductor of the opposite polarity. The gate insulator layer is fabricated by implanting an element or elements selected from Group V, VI or VII into the semiconductor to form a semiconductor-compound insulator. Methods of fabricating this device are also disclosed. In one embodiment the device is fabricated on top of an insulating support. The gate is formed next to the base. In a second embodiment, no base is used.

Abstract: Articles according to the invention comprise an improved organic thin film transistor (TFT) that can have substantially higher source/drain current on/off ratio than conventional organic TFTs. An exemplary TFT according to the invention comprises, in addition to a p-type first organic material layer (e.g., .alpha.-6T), an n-type second organic material layer (e.g., Alq) in contact with the first material layer. TFTs according to the invention can be advantageously used in, for instance, active liquid crystal displays and electronic memories.

Abstract: Organic thin film transistors having improved properties (e.g., on/off ratio>10.sup.5 at 20.degree. C.) are disclosed. The improved transistors comprise an organic active layer of low conductivity (<5.times.10.sup.-8 S/cm at 20.degree. C., preferably less than 10.sup.-8 or even 10.sup.-9 S/cm). A method of producing such materials is disclosed. Rapid thermal annealing was found to have beneficial results. An exemplary and preferred material is .alpha.-hexathienylene (.alpha.-6T). The improved transistors are expected to find use for, e.g., active liquid crystal displays and for memories.

Abstract: A full wafer to full wafer integrated circuit apparatus wherein substrate removal and replacement on one wafer has been used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo feed effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Abstract: A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.

Abstract: A semiconductor device with an improved insulating and passivating layer including the steps of providing a gallium arsenide substrate with a surface, and crystallographically lattice matching an insulating and passivating layer of indium gallium fluoride on the surface of the gallium arsenide substrate. In one embodiment the semiconductor device is a FET and the layer of indium gallium fluoride covers at least an inter-channel area surrounding the gate.

Abstract: A combination of a semiconductor region essentially consisting of Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1), an insulating film formed on the surface of the semiconductor region and essentially consisting of GaAs.sub.x P.sub.y O.sub.z (w, y, z>0), and a passivation film formed on the insulating film and made of an insulating material different from the insulating film. The laminated insulating film has an extremely low leakage current. An excellent MISFET can be realized by forming a gate electrode on the surface of the laminated insulating film.

Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.

Abstract: A semiconductor device comprises a channel of a semiconductor material for passing carriers, a carrier injecting part for injecting the carriers into the channel and establishing an ohmic contact with the channel at a first location, a carrier collecting part for collecting the carriers from the channel, the carrier collecting part establishing an ohmic contact with the channel at a second, different location, a carrier control part provided on the channel at a third location located between the first and second locations, the carrier control part being applied with a control voltage and controlling the passage of the carriers through the channel from the carrier injecting means to the carrier collecting means in response to the control voltage, and an acceleration part provided between the first and third locations including the third location.

Abstract: A vertical Metal Oxide Semiconductor Heterojunction Field Effect Transistor (MOSHFET) and method of fabrication therefor. The MOSHFET is in a layered wafer made by successively growing an N.sup.+ silicon layer, and a N.sup.- silicon layer, a P.sup.- Si.sub.1-x Gex layer, a P.sup.- Silicon layer and then, an N.sup.- silicon layer, one on top of the other. Trenches are etched through the top 3 layers to form islands that are the MOSHFETs heterojunction channel. A gate deposited or grown in a trench extends vertically from the drain at the bottom of the trench to the source in the layer near the top of the trench.

Abstract: A semiconductor structure including a single-crystal region composed of an isotopically enriched material, wherein the isotopically enriched material is selected from a subset consisting of all semiconductor materials except elemental silicon; and a semiconductor device formed by using said isotopically enriched semiconductor region.

Abstract: A microelectronic structure including a plurality of spaced apart diamond structures on which a plurality of semiconductor devices may be formed. The semiconductor devices include a semiconducting diamond layer on each of the diamond structures. The diamond structures are preferably oriented relative to a single crystal nondiamond substrate so that the diamond structures have a (100)-oriented outer face for forming the semiconductor devices thereon. The microelectronic structure may be diced into discrete devices, or the devices interconnected, such as to form a higher powered device. One embodiment of the microelectronic structure includes the plurality of diamond structures, wherein each diamond structure is formed of a highly oriented textured diamond layer approaching single crystal quality, yet capable of fabrication on a single crystal nondiamond substrate.

Abstract: The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.

Abstract: A semiconductor device having in a body of a group III-V semiconductor material at least one isolation region which is stable at temperatures up to about 900.degree. C. The isolation region is formed of ions of a group III or V element which are implanted into the body and then thermally annealed at a temperature of between 650.degree. C. and 900.degree. C. This provides the regions with voids which remove free carriers and makes the region highly resistive.

Abstract: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another.

Abstract: A MOSFET (100) device having a silicon carbide substrate (102) of a first conductivity type. A first epitaxial layer (104) of said first conductivity type and a second epitaxial layer (106) of a second conductivity type are located on a top side of the substrate (102). An insulator layer (108) separates gate electrode (112) from second epitaxial layer (106). A drift region (118) of the first conductivity type is located within the second epitaxial layer (106) on the first side of the gate electrode (112). The drift region has an extension which extends through the second epitaxial layer (106) to the first epitaxial layer (104). Source regions (116) and body contact regions (122) are located within the second epitaxial layer (106) on the second side of the gate electrode (112). Source regions (116,) and body contact regions (122) are of opposite conductivity type. Source electrode (126) electrically connects source regions (116) and body contact regions (122 ).

Abstract: Electrical quality insulating films on n-type and p-type diamond substrates are provided in which an insulating film such as a silicon dioxide film is deposited onto the exposed face of a diamond substrate, such as by chemical vapor deposition. Forming a conducting layer atop the silicon dioxide allows the creation of a metal-oxide-silicon device with which semiconductor carriers can be controlled through the application of a bias voltage to the conductor surface.

Abstract: An organic electric-field switching device has transparent or semitransparent upper electrodes and second insulating film so as to bias an electric field on a hetero-junction membrane formed on a lower electrode, in which the doping speed of a carrier is fast, and the switching device can be operated as the solid-state device and can be easily formed on a semiconductor made of silicon and the like. Therefore, the degree of integration of the device can be rapidly increased due to its multilayered structure.

Abstract: A thin-layer field-effect transistor (TFT) with an MIS structure includes a thin semiconductor layer between a source and a drain. The thin semiconductor layer is in contact with one surface of a thin layer made of insulating material, and in contact by its other surface with a conducting grid. The semiconductor is composed of at least one polyconjugated organic compound with a specific molecular weight. The polyconjugated organic compound or polyconjugated organic compounds contain at least 8 conjugated bonds and have a molecular weight of no greater than approximately 2,000. The thin layer of insulating material is made of an insulating organic polymer having a dielectric constant of at least equal to 5. The transistor is useful as a switching or amplifying element.

Abstract: A MODFET structure having a semi-insulating substrate overlayed with an undoped semiconductor buffer layer of a first composition. The buffer layer is overlayed with an undoped semiconductor layer having a second composition different from the composition of the buffer layer. An etch stop layer having a composition different from the composition of spacer layer is formed on the spacer layer, which in turn is overlayed with a doped semiconductor layer having the same composition as the spacer layer. A gate well is selectively etched through the doped semiconductor layer using a gate mask and is terminated at the top surface of the etch stop layer. In a first embodiment, a gate electrode is deposited on the surface of the stop layer at the bottom of the gate well. In an alternate embodiment the etch stop layer at the bottom of the gate well is removed and a thin dielectric layer is formed between the spacer layer and the gate electrode.

Abstract: A process for selective formation of a II-VI group compound film comprises applying a compound film forming treatment, in a gas phase including a starting material for supplying the group II atoms of periodic table and a starting material for supplying the group VI atoms of periodic table, on a substrate having a non-nucleation surface (S.sub.NDS) with small nucleation density and a nucleation surface (S.sub.NDL) with larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and a large area sufficient for a number of nuclei to be formed and forming selectively a II-VI group compound film only on said nucleation surface (S.sub.NDL).

Abstract: A superconducting device including first and second trenches formed on a principal surface of a semiconductor substrate, separated from each other, and first and second superconductor electrodes filled in the first and second trenches and planarized to have a surface coplanar with the principal surface of the semiconductor substrate. The first and second superconductor electrodes form a separation zone which is defined by opposing sides of the first and second superconductor electrodes. An insulating layer is formed to cover a portion of the first superconductor electrode, the separation zone and a portion of the second superconductor electrode, and a gate electrode is formed on the insulating layer so as to be positioned above at least the separation zone.

Abstract: A MISFET includes a GaAs substrate, a gate insulating film of a II-VI group compound including Zn, Mg, S, and Se epitaxially grown on the GaAs substrate, and a gate electrode formed on the gate insulating film.

Abstract: A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.

Abstract: A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.

Abstract: A process and resultant devices is described for forming MOSFET, CMOS and BICMOS devices of Group IV alloys, in particular Si.sub.x Ge.sub.1-x wherein 0<x<1, using ion beam oxidation (IBO) or ion beam nitridation (IBN) by CIMD to form insulators of the Group IV alloys.

Abstract: An SB FET comprising source and drain regions formed in the surface of a gallium arsenide (GaAs) substrate, and a channel region formed between the source and drain regions. The gate electrode of the SB FET is formed on the channel region in Schottky contact therewith. The SB FET further comprises source and drain electrodes which are mounted on the source and drain regions in ohmic contact therewith, while being separated from each other at a greater distance than the length of the channel region.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.

Abstract: A silicon carbide field-effect transistor is disclosed which includes an MOS structure composed successively of a silicon carbide layer, a gate insulator film, and a gate electrode. The field-effect transistor has source and drain regions formed in the silicon carbide layer, between which the MOS structure is disposed, wherein at least one of the source and drain regions is formed by the use of a Schottky contact on the silicon carbide layer.

Abstract: A silicon carbide semiconductor device is disclosed which includes a semiconductor substrate and a silicon carbide single-crystal layer formed above the substrate, the silicon carbide single-crystal layer having a device active region. The silicon carbide semiconductor device further includes an aluminum nitride single-crystal layer which is disposed between the silicon carbide single-crystal layer and the substrate. The aluminum nitride single-crystal layer functions as an electrically insulating layer by which the silicon carbide signale-crystal layer is isolated electrically from the substrate.

Abstract: A field effect transistor comprises a diamond substrate which has a p-type ion implanted region coterminous with a surface of the diamond substrate, wherein the ion implanted region has a hole concentration in the range of 1.times.10.sup.15 to 1.times.10.sup.17 holes/cm.sup.2, and a hole mobility equal to or greater than 1 cm.sup.2 /V-sec; spaced apart source and drain electrodes formed over the p-type ion implanted region on the surface of the diamond substrate; an electrically insulating material formed over the p-type ion implanted region on the surface of the diamond substrate between the source and drain electrodes; and a gate electrode formed on the surface of the insulating material.