Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: Disclosed are a CMOS image sensor and a fabrication method thereof, which is adequate to reduce dark current. The CMOS image sensor comprises a device isolation region and an active region, which are formed on a semiconductor substrate; a photocharge generating portion formed on the active region for absorbing light externally and generating and accumulating charges; a transistor portion including at least one transistor for processing the charges accumulated in the photocharge generating portion; and a control terminal for preventing dark current from being introduced into the photocharge generating portion, and ejecting the dark current after temporally storing the dark current. The control terminal is operated to store the dark current for an integration time when a photodiode as the photocharge generating portion receives light, and eject the stored dark current by being grounded when the reset transistor is turned on.

Abstract: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading gate. Therein, a groove is formed on the surface side of the substrate, and the transfer register and the reading gate are formed at the bottom part of the groove. With such a structure, in the solid-state image pickup device, reduction can be achieved for the smear characteristics, a reading voltage, noise, and others.

Abstract: A CMOS image device comprises a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region, a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of nMOS transistors and pMOS transistors, and contact studs formed on the floating diffusion region and the junction region in the pixel array region, the contact studs comprising impurity-doped polysilicon layers.

Abstract: The present invention provides a display device having an illuminance detection circuit. The illuminance detection circuit includes: a photosensor which changes an optical current in response to illuminance of an external light; a capacitor which discharges a charge when the optical current flows in the photosensor; a comparator which compares a voltage at one end of the capacitor and a comparison reference voltage; a switching circuit which is connected to one end of the capacitor and charges the capacitor in response to a level of an output signal of the comparator; and a selection circuit which applies either a first voltage or a second voltage to the other end of the capacitor in response to the level of the output signal of the comparator.

Abstract: A photodetector device is provided which comprises a photodiode for generating an electrical signal corresponding to an amount of incident light, and a logarithmic conversion transistor for subjecting a voltage value of the electrical signal to logarithmic conversion. The logarithmic conversion transistor comprises a first electrode which is one of a source electrode and a drain electrode, a second electrode which is the other of the source electrode and the drain electrode, and a gate electrode. The first electrode is connected to the photodiode. A first voltage is applied to the second electrode so that the logarithmic conversion transistor operates in a subthreshold region. The photodetector device further comprising a section for causing a voltage of the gate electrode to be in a floating state when the logarithmic conversion transistor subjects the voltage value of the electrical signal to logarithmic conversion.

Abstract: A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer formed in a plane shape on a semiconductor substrate, and the shield layer is electrically connected directly to the semiconductor substrate and is fixed to a power supply potential or the ground potential.

Abstract: Disclosed is a photodiode array which includes a plurality of p-i-n photodiodes arrayed on a semi-insulative semiconductor substrate, each photodiode including an n-type semiconductor layer grown on the substrate, an i-type semiconductor layer grown on the n-type semiconductor layer, a p-type semiconductor layer grown on the i-type semiconductor layer, an n-type electrode provided on the n-type semiconductor layer in a region exposed by partially removing the p-type semiconductor layer and the i-type semiconductor layer, and a p-type electrode provided on the p-type semiconductor layer. A trench is provided between the two adjacent photodiodes by partially removing the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer. Consequently, the size and pitch of the photodiodes can be decreased and crosstalk between the photodiodes can be reduced. Also disclosed is an optical receiver device including the photodiode array.

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract: A solid-state image pick-up device of a photoelectric converting film lamination type including a semiconductor substrate and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films. The pixel electrode films correspond to pixels respectively, and at least three layers of photoelectric converting films are laminated through insulating layers. The at least three layers of photoelectric converting films are above the semiconductor substrate. Sets of the pixel electrode films are provided on each of the at least three layers of photoelectric converting films, and electric charge storage portions formed on the semiconductor substrate are connected through sets of columnar contact electrodes. Resistance values of the sets of columnar contact electrodes are equal to each other.

Abstract: A self-aligned silicide (salicide) process is used to form a local interconnect for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An oxide layer is deposited over the pixel array of the image sensor. Portions of the oxide layer is removed and a metal layer is deposited. The metal layer is annealed to form a metal silicide. Optionally, a protective oxide layer is then deposited.

Abstract: A solid-state imaging device can increase the amount of signal charge accumulation in a photodiode. The solid-state imaging device includes a gate electrode formed on a p-type semiconductor substrate. An n-type signal accumulation region accumulates the signal charge obtained through a photo-electrical conversion, and is formed in the semiconductor substrate so that a portion of the signal accumulation region is positioned below the gate electrode. An n-type drain region is positioned in the semiconductor substrate so that the n-type drain region is positioned opposite the signal accumulation region across the gate electrode. A p-type punch-through stopper region has a higher impurity concentration than the semiconductor substrate, and is formed in the semiconductor substrate so that the p-type punch-through region is positioned below the drain region, wherein an end of the punch-through stopper region is positioned closer to the signal accumulation region than the end of the drain region.

Abstract: A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating diffusion region to the junction region upon receipt of a reset signal, and a potential well incorporated underneath the gate.

Abstract: A pixel structure is provided. The pixel structure comprises a scan line, a data line, a pixel electrode and a thin film transistor. The data line branches out into a plurality of subsidiary lines in the area above the scan line. If there is a short circuit between the scan line and the data line, the short circuit can be repaired by cutting the connections to one of the branching subsidiary lines. In one embodiment of this invention, a repair line is set up on one side of the data line such that a portion of the repair line crosses over the scan line. If there is a short circuit between the scan line and the data line, a laser repair operation can be carried out through the repair line.

Abstract: A sensor includes control circuitry and a pixel. The pixel includes a photo site, a first storage node and a second storage node. The control circuitry causes the pixel to transfer a first collected signal from the photo site to the first storage node during a first period, to transfer a second collected signal from the photo site to the second storage node during a second period that follows the first period, and to transfer the first and second collected signals out of the pixel during a third period that follows the second period.

Abstract: A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

Abstract: A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.

Abstract: A display device has an array 40 of pixels and row and column driver circuitry comprising row driver circuit portions R and column driver circuit portions C, each pixel being addressed by a row driver circuit portion R and a column driver circuit portion C which connect to respective row and column conductor lines. The array of pixels has a non-rectangular outer shape, and the device comprises at least three row driver circuit portions R and at least three column driver circuit portions C disposed alternately around the outer periphery of the array. This arrangement enables row and column drivers to be divided into portions which are arranged in such a way that addressing can be provided for complicated display shapes.

Abstract: In a photoelectric conversion device having a buried layer in a part of an anode and a cathode of a photodiode, such as a CCD having a sensor structure and a CMOS sensor, well of the same conduction type as the conduction type of the buried layer can be disposed in a peripheral circuit and the potential of each well is independently controlled.

Abstract: A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device by a minimum predetermined distance, forming an etch stop layer for covering a contact area of the transistor device, removing at least a portion of the etch stop layer in the predetermined area for exposing the image sensor, and covering the image sensor and the transistor device by at least one transparent protection layer.

Abstract: A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge system to transform the silicon nitride/silicon oxide layer into a silicon oxynitride layer. The semiconductor device may be completely manufactured in simplex equipment. Therefore, the production time and production cost are favorably reduced.

Abstract: Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this performance is achieved by forming a trench type light-transmission layer to occupy a major surface of the photo diode so as to reduce the area available for defects on the surface of the semiconductor substrate. As a result of this reduction, the depletion region formed upon the operation of the sensor may extend toward the surface of the semiconductor substrate without concern for defects. The image sensor may be manufactured without forming a blocking layer in connection with a silicide layer.

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.

Abstract: The present invention provides an electro-optical device capable of achieving an increased light emission efficiency and an enhanced visibility. An organic electroluminescents (EL) display device has a plurality of material layers including a luminescent layer. In a plurality of material layers layered in the direction of light emission from the luminescent layer, first and second insulating interlayers are disposed between a substrate, which is positioned at the outermost surface, and the luminescent layer. The first and second insulating interlayers have a refractive index lower than that of the substrate. Accordingly, by forming predetermined materials having a low refractive index, the resulting low refractive index layers have a low dielectric constant, and consequently, the capacity between wires can be reduced.

Abstract: A semiconductor photodetector device includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and having a light-receiving region. The first semiconductor layer includes a first region containing an impurity of the first conductivity type at a high concentration and a second region formed on the first region and containing an impurity of the first conductivity type at a concentration lower than that of the first region. The second semiconductor layer includes a third region containing an impurity of the second conductivity type at a concentration higher than that of the second region and a fourth region formed on the third region and containing an impurity of the second conductivity type at a concentration higher than that of the third region.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A device is provided having a first electrode, a second electrode, a first photoactive region having a characteristic absorption wavelength ?1 and a second photoactive region having a characteristic absorption wavelength ?2. The photoactive regions are disposed between the first and second electrodes, and further positioned on the same side of a reflective layer, such that the first photoactive region is closer to the reflective layer than the second photoactive region. The materials comprising the photoactive regions may be selected such that ?1 is at least about 10% different from ?2. The device may further comprise an exciton blocking layer disposed adjacent to and in direct contact with the organic acceptor material of each photoactive region, wherein the LUMO of each exciton blocking layer other than that closest to the cathode is not more than about 0.3 eV greater than the LUMO of the acceptor material.

Abstract: The organic photoelectric conversion element according to the invention has enhanced the light-absorbing property by incorporating two or more kinds of electron donating organic materials 4a and 4b in the photoelectric conversion region 14. With such measure, it has become possible to efficiently absorb the incident light and enhance the photoelectric conversion characteristic. In addition, a light-to-light conversion material 7 is incorporated in the photoelectric conversion region, too. With this measure, even the light of such a wavelength that an electron donating organic material cannot inherently absorb comes to be absorbed since the light-to-light conversion material 7 converts the wavelength, thus enabling the light to be utilized for carrier generation. Accordingly, an organic photoelectric conversion element with a high conversion efficiency can be obtained.

Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.

Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.

Abstract: There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A TFT array panel is provided, including an insulating substrate, gate lines horizontally provided on the insulating substrate, data lines isolated from the gate lines and intersecting the gate lines, a pixel electrode in a pixel region defined by intersecting the gate lines and data lines, a TFT for transmitting or intercepting an image signal transmitted through the plurality of data lines to the pixel electrode in response to a scanning signal transmitted from the plurality of gate lines, a transmission gate for distributing the image signal input from an input line to the plurality of data lines, and a repair line intersecting the input line of the transmission gate. Therefore, since the input repair line and the input line of the transmission gate are intersected, a parasitic capacitance occurring between the repair line and the input line of the transmission gate can be reduced.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a predetermined portion of a substrate in the logic area to thereby define an active area and a field area; a field stop ion implantation area formed on a predetermined portion of the substrate in the pixel area, the field stop ion implantation area having a predetermined depth from a surface of the substrate to define an active area and a field area; and an oxide layer deposited on a substrate surface corresponding to the field stop ion implantation area.

Abstract: A solid-state imaging device is provided which has preferable linearity of signal outputs according to light intensities and does not cause dark defects even at a low light intensity. The solid-state imaging device comprises: a ring gate having a non-uniform width; a source region formed inside the ring gate; a drain region formed surrounding a circumference of the ring gate; and a carrier pocket formed under the ring gate, wherein a region where (X divided by Y) is the smallest substantially coincides with a region where Z is the shortest; X is a pocket-to-source distance; Y is a pocket-to-drain distance; and Z is a source-to-drain distance.

Abstract: An image pickup apparatus or a radiation image pickup apparatus according to the present invention includes: a plurality of pixels which are two-dimensionally arranged on a substrate, each of the plurality of pixels including a set of a semiconductor conversion element that converts an incident electromagnetic wave into an electrical signal and a switching element connected with the semiconductor conversion element; a drive wiring which is commonly connected with the plurality of switching elements arranged in a direction; and a signal wiring which is commonly connected with the plurality of switching elements arranged in a direction different from the direction, the switching element including a first semiconductor layer, the semiconductor conversion element being formed after the switching elements are formed and including the second semiconductor layer formed after the first semiconductor layer is formed, in which the semiconductor conversion element has an electrode formed outside a region in which two of

Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.

Abstract: A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss. The charge storage region is adjacent to a gate of a transistor. The transistor gate is adjacent to the photo-conversion device and, in conjunction with the control gate, transfers photo-generated charge from the photo-conversion device to the charge storage region.

Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.

Abstract: An image sensor includes a semi-conducting substrate having a photo-sensitive region and doping for forming a path to a charge-to-voltage mechanism; a dielectric spanning the substrate; and a semi-conducting layer, which is less than approximately 1 micrometer, spanning the dielectric which contains electrodes and circuit elements that control flow of charge.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: The invention provides a solid-state imaging device that include a pixel array where a plurality of unit pixels each including a photo diode and an insulated gate field effect transistor for detecting a photocharge are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can apply a predetermined voltage to a source diffused region of the insulated gate field effect transistor and applies voltage by which a channel region becomes a conductive state to a gate electrode to bias a junction region formed of a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type in a forward direction so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and thereby causing the charge of a predetermined conductivity type accumulated in the accumulation region to be discharged.

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract: A fault detection system detecting malfunctions or deteriorations, which may result in an inverter fault, is provided. The system has a temperature sensor installed on a semiconductor module to monitor a temperature rise rate. It is judged that an abnormal condition has occurred if the thermal resistance is increased by the deterioration of a soldering layer of the semiconductor module or by drive circuit malfunctions and, as a result, the relation between an operation mode and the temperature rise rate falls outside a predetermined range.

Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.