Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a dielectric structure over the substrate. The semiconductor device structure includes a contact structure passing through the dielectric structure. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer. The first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, the contact layer passes through the first barrier layer and extends into the dielectric structure, and the first barrier layer passes through the second barrier layer and extends into the dielectric structure.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.

Abstract: Ferroelectric semiconductor device with a memory cell, with a ferroelectric memory layer and a first conductive layer disposed on the ferroelectric memory layer; and a semiconductor device connected to the memory cell. The ferroelectric memory layer of the memory cell can include a mixed crystal with a group III nitride and a non-group III element.

Abstract: A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.

Abstract: Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: An adder device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A set of regions are positioned on a top layer above a continuous bottom layer, and the regions excited with magnetization for A and not A, B and not B, and C and not C to form a sum and an inverse carry output magnetization.

Abstract: A MEMS device is provided that includes a piezoelectric film, a first electrode and a second electrode sandwiching the piezoelectric film, a protective film that covers at least part of the second electrode and having a cavity that opens part of the second electrode, a third electrode that contacts the second electrode at least in the cavity and is provided so as to cover at least part of the protective film, and a first wiring layer having a first contact portion in contact with the third electrode.

Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.

Abstract: A piezoelectric micromachined ultrasound transducer (PMUT) device may include a plurality of layers including a structural layer, a piezoelectric layer, and electrode layers located on opposite sides of the piezoelectric layer. Conductive barrier layers may be located between the piezoelectric layer and the electrodes to the prevent diffusion of the piezoelectric layer into the electrode layers.

Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

Abstract: The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.

Abstract: According to one embodiment, a magnetic storage device includes a nonvolatile magnetic memory including a magnetoresistance effect element capable of storing data. A magnetic sensor is configured to measure the magnitude of an external magnetic field. A controller is configured to detect errors in the data at first time intervals when the measured magnitude of the external magnetic field is less than a threshold value and to detect errors in the data at second time intervals shorter than the first time interval when the measured magnitude of the external magnetic field is equal to or greater than the threshold value.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a porous insulating layer positioned above the substrate, a first conductive feature positioned in the porous insulating layer, and covering liners including two top segments and two side segments. The two side segments are positioned on sidewalls of the first conductive feature, and the two top segments are positioned on top surfaces of the porous insulating layer.

Abstract: An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.

Abstract: An inductor includes a magnetic body, and a conductor embedded in the magnetic body. The conductor includes a first conductor, and a second conductor covering a periphery of the first conductor.

Abstract: A method of nitridation includes cyclically performing the following steps in situ within a processing chamber at a temperature less than about 400° C.: treating an unreactive surface of a substrate in the processing chamber to convert the unreactive surface to a reactive surface by exposing the unreactive surface to an energy flux, and nitridating the reactive surface using a nitrogen-based gas to convert the reactive surface to a nitride layer including a subsequent unreactive surface.

Abstract: Methods of removing native oxide layers and depositing dielectric layers having a controlled number of active sites on MEMS devices for biological applications are disclosed. In one aspect, a method includes removing a native oxide layer from a surface of the substrate by exposing the substrate to one or more ligands in vapor phase to volatize the native oxide layer and then thermally desorbing or otherwise etching the volatized native oxide layer. In another aspect, a method includes depositing a dielectric layer selected to provide a controlled number of active sites on the surface of the substrate. In yet another aspect, a method includes both removing a native oxide layer from a surface of the substrate by exposing the substrate to one or more ligands and depositing a dielectric layer selected to provide a controlled number of active sites on the surface of the substrate.

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Abstract: A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al2O3 film between the top electrode and the dielectric film, wherein the doped Al2O3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al2O3.

Abstract: Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

Abstract: A memory device, transistor, and methods of making the same, the memory device including a memory device including: a ferroelectric (FE) structure including: a dielectric layer, an FE layer disposed on the dielectric layer, and an interface metal layer disposed on the FE layer, in which the interface metal layer comprises W, Mo, Ru, TaN, or a combination thereof to induce the FE layer to have an orthorhombic phase; and a top electrode layer disposed on the interface metal.

Abstract: A semiconductor device includes a gate electrode, a channel layer, and a ferroelectric layer. The ferroelectric layer includes a monocrystalline region located between the gate electrode and the channel layer to serve as a gate dielectric, and a polycrystalline region located at an edge of the gate electrode. A method for manufacturing the semiconductor device is also disclosed.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions.

Abstract: A memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Abstract: A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate having a first surface and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to the bottom electrode layer.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

Abstract: A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer.

Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A memory device is provided that includes at least one resistive memory cell, a negative capacitance field effect transistor (NC-FET) serving as a voltage amplifier, and a switch enable circuit connecting NC-FET to the memory cell. The NC-FET includes a regular FET having a metal gate terminal and a ferroelectric capacitor. The NC-FET gate terminal forms one plate of the ferroelectric (FE) capacitor. The ferroelectric capacitor includes a ferroelectric dielectric material deposited between a formed upper gate conductive contact and he metal gate terminal. To provide further flexibility, a metal layer can be deposited before the deposition of the ferroelectric material to form a MIM-like FE capacitor so that the capacitance of FE capacitance can be independently tuned by choosing the right height (H), width (W), and length (L) to achieve desired matching between |CFE| and Cox where Cox is the gate oxide capacitance and CFE is the ferroelectric capacitance.

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

Abstract: A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

Abstract: A memory cell arrangement may include: a first memory cell including a first field-effect transistor structure, a first capacitive memory structure coupled to a gate of the first field-effect transistor structure, and a first capacitive lever structure coupled to the gate of the first field-effect transistor structure, and wherein a second memory cell of the plurality of memory cells includes a second field-effect transistor structure, a second capacitive memory structure coupled to a gate of the second field-effect transistor structure, and a second capacitive lever structure coupled to the gate of the second field-effect transistor structure; wherein at least one of the first capacitive memory structure and/or the second capacitive memory structure is disposed in a memory structure region between the first capacitive lever structure and the second capacitive lever structure.

Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.

Abstract: Transistors with switchable polarity and non-volatile configurations are provided. The transistors include a van der Waals (vdW) semiconductor layer. A ferroelectric layer with local polarization determines the type and concentration of the doping in the vdW semiconductor layer. Local program gates allow application of voltage to set or switch the polarization in the ferroelectric layer in the source and drain regions. Source and drain contacts permit either n-type or p-type transistor operations according to the carrier polarity in the vdW semiconductor layer.

Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.

Abstract: A memory element including a layered structure including a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information stored therein, a magnetization-fixed layer having magnetization perpendicular to the film face, which becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.