Abstract: Some embodiments relate to a memory device. The memory device includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode cups an underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.

Abstract: A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion.

Abstract: A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150 nm, without impairing the data retention property of not less than 105 seconds and the data rewrite endurance property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.

Abstract: In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) device. The MIM device includes a substrate, and a first and second electrode stacked over the substrate. A dielectric layer is arranged between the first and second electrodes. Further, the MIM device includes a titanium getter layer that is disposed over the substrate and separated from the dielectric layer by the first electrode. The titanium getter layer has a higher getter capacity for hydrogen than the dielectric layer.

Abstract: A semiconductor includes a ferroelectric layer, a first semiconductor layer, a first gate, a second semiconductor layer, a second gate and contact structures. The ferroelectric layer has a first surface and a second surface opposite to the first surface. The first semiconductor layer is disposed on the first surface of the ferroelectric layer. The first gate is disposed on the first semiconductor layer over the first surface. The second semiconductor layer is disposed on the second surface of the ferroelectric layer. The second gate is disposed on the second semiconductor layer over the second surface. The contacts structures are connected to the first semiconductor layer and the second semiconductor layer.

Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.

Abstract: Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to top electrode interconnect structures and methods of manufacture. The structure includes: a lower metallization feature; an upper metallization feature; a bottom electrode in direct contact with the lower metallization feature; one or more switching materials over the bottom electrode; a top electrode over the one or more switching materials; and a self-aligned via interconnection in contact with the top electrode and the upper metallization feature.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, and a gate over the multilayer gate dielectric stack.

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.

Abstract: A method includes: providing a bottom layer; depositing a first seed layer over the bottom layer, the first seed layer having at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer; and cooling the dielectric layer, wherein after the cooling the dielectric layer becomes a ferroelectric layer.

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

Abstract: A device for directly electrically generating and detecting the current-generated spin polarization in topological insulators, comprising a first and fourth contact on a layer of Bi2Se3 and a second contact comprising a ferromagnet/oxide tunnel barrier contact as a detector, and a third contact comprising nonmagnetic metal as a reference contact, a current to the first and fourth contact to produce a net spin polarization, and the spin polarization manifesting as a voltage between the second (magnetic) and third (reference) contacts.

Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.

Abstract: The present disclosure relates to a resistance random access memory device, including a first electrode, a resistance change layer formed on the first electrode, and a second electrode formed on the resistance change layer, and the resistance change layer includes a bismuth halide-based BiIxBr3-x thin film (where 0?x?3) and/or a Cs2AgBiBrxI6-x thin film (where 0?x?6) having an elpasolite structure.

Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.

Abstract: Systems, apparatus, and methods for initializing spin qubits with no external magnetic fields are described. An apparatus for quantum computing includes a quantum well and a pair of contacts. At least one of the contacts is formed of a ferromagnetic material. One of the contacts in the pair of contacts interfaces with a semiconductor material at a first position adjacent to the quantum well and the other contact in the pair of contacts interfaces with the semiconductor material at a second position adjacent to the quantum well. The ferromagnetic material initializes an electron or hole with a spin state prior to injection into the quantum well.

Abstract: A semiconductor structure including silicon substrate, buried word lines, active areas, isolating areas, and nitride pillars is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas and the isolating areas are located on the carrier surface. The nitride pillars are disposed in the isolating areas respectively. The active areas and the isolating areas are arranged along a first direction. The buried word lines are extended along a second direction. The nitride pillars are located below the buried word lines in the isolating areas. A manufacturing method of semiconductor structure is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

Abstract: An organic light-emitting diode array substrate and manufacturing method thereof are provided. The manufacturing method includes forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate; forming a first metal pattern on the first insulating layer, and the first metal pattern connecting to the gate through the through hole; forming a second insulating layer covering the first metal pattern on the first insulating layer; and forming a second metal pattern on the second insulating layer so that the second metal pattern and the first metal pattern overlap each other to form a capacitor.

Abstract: A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

Abstract: The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.

Abstract: A variable low-resistance line memory device and an operating method thereof are provided. The memory device includes: a base including a spontaneous polarizable material; a gate arranged adjacent to the base; at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other; a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other; a source located to contact the variable low-resistance line; and a drain located to contact the variable low-resistance line, wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.

Abstract: A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

Abstract: Embodiments of the present disclosure generally relate to a large field range TMR sensor of magnetic tunnel junctions (MTJs) with a free layer having an intrinsic anisotropy. In one embodiment, a tunnel magnetoresistive (TMR) based magnetic sensor in a Wheatstone configuration includes at least one MTJ. The MTJ includes a free layer having an intrinsic anisotropy produced by deposition at a high oblique angle from normal. Magnetic domain formations within the free layer can be further controlled by a pinned layer canted at an angle to the intrinsic anisotropy of the free layer, by a hard bias element, by shape anisotropy, or combinations thereof.

Abstract: A magnetic random access memory assisted non-volatile Hall effect device includes a spin orbit torque layer disposed over a substrate, and a magnetic layer disposed over the spin orbit torque layer. A metal oxide layer disposed over the magnetic layer. Portions of the spin orbit torque layer extend outward from the magnetic layer and the metal oxide layer on opposing sides of a first direction and opposing sides of a second direction in plan view, and the second direction is perpendicular to the first direction.

Abstract: A semiconductor device includes: a silicon layer in which a trench is disposed; a surface structure portion disposed on the silicon layer at a position distant from the trench and having a surface provided by a metal layer; and a low electric conductivity portion disposed on the surface of the metal layer or in a part of the resist disposed on the trench side of the metal layer, and having an electric conductivity lower than at least a part of the metal layer covering a trench side portion of the surface of the metal layer.

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Abstract: The present disclosure is to provide a ferromagnetic tunnel junction element and a method of manufacturing the ferromagnetic tunnel junction element capable of avoiding changes in the characteristics of the element and maintaining a high fabrication yield, while avoiding an increase in the area occupied by the element and an increase in the number of manufacturing steps. The ferromagnetic tunnel junction element to be provided includes: a first magnetic layer; a first insulating layer disposed on the first magnetic layer; a second magnetic layer containing a magnetic transition metal, the second magnetic layer being disposed on the first insulating layer; and a magnesium oxide film containing the magnetic transition metal, the magnesium oxide film being disposed to cover the side surfaces of the second magnetic layer.

Abstract: The present disclosure provides a semiconductor device with a graphene layer and a method for forming the same. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a gate dielectric layer, and a lower electrode layer disposed over the gate dielectric layer. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a first graphene layer disposed between the lower electrode layer and the upper electrode layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

Abstract: This piezoelectric element includes a lower electrode formed on a substrate, a piezoelectric layer formed on the lower electrode, and an upper electrode formed on the piezoelectric layer. The upper electrode includes a first upper electrode layer made of a metal oxide including an amorphous portion at least at a boundary with the piezoelectric layer and a second upper electrode layer formed on the first upper electrode layer.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A method and a composition to stabilize the surface cation chemistry of the perovskite or related oxides, and thus, to minimize or completely avoid the detrimental segregation and phase separation of dopant cations at the surface can include modifying the surface with more oxidizable metal cations and/or more oxidizable metal oxides, thereby reducing the oxygen vacancy concentration at the very surface.

Abstract: The disclosed technology generally relates semiconductor devices, and relates more particularly to a spin transfer torque device, a method of operating the spin-transfer torque device and a method of fabricating the spin-transfer torque device. According to one aspect, a spin-transfer torque device includes a magnetic flux guide layer and a set of magnetic tunnel junction (MTJ) pillars arranged above the magnetic flux guide layer. Each one of the pillars includes a separate free layer, a separate tunnel barrier layer and a separate reference layer. A coupling layer is arranged between the magnetic flux guide layer and the MTJ pillars, wherein a magnetization of the separate free layer of each of the each of the MTJ pillars is coupled, parallel or antiparallel, to a magnetization of the magnetic flux guide layer through the coupling layer.

Abstract: A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

Abstract: A semiconductor device includes a first cell and a second cell. The first cell includes a first circuit, and the first circuit includes a first gate. The second cell is disposed adjacent the first cell and includes a second circuit which includes a second gate. The doping concentration of the first circuit is different from that of the second circuit, and the first gate and the second gate have the same gate critical dimension. A method for manufacturing the semiconductor device is also disclosed herein.

Abstract: Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.

Abstract: A magnetic device includes a pinned layer having an in-plane magnetization direction; a free layer, having an in-plane magnetization direction, vertically spaced apart from the pinned layer to be aligned with the pinned layer; a conductive spacer layer disposed between the pinned layer and the free layer; an antiferromagnetic layer disposed to fin the magnetization direction of the pinned layer and vertically spaced apart from the pinned layer to be aligned with the pinned layer; and a noble metal spacer layer disposed between the pinned layer and the antiferromagnetic layer.