Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: A semiconductor memory having a memory cell including a stacked capacitor in which a lower electrode contacting one of two diffusion regions of an access transistor is formed in the form of two layers. It is preferable that impurities having a smaller diffusion coefficient, or arsenic is introduced into a first layer of the lower electrode contacting the diffusion region, and impurities having a larger diffusion coefficient, or phosphorus is introduced into a second layer of the lower electrode contacting capacitor dielectric film. Since a diffusion coefficient of arsenic is small, it is possible to prevent the junction of the diffusion region from becoming deep and on the other hand since phosphorus is introduced into the second polycrystalline Si film contacting the capacitor dielectric film, it is possible to prevent the degradation of the film quality of the capacitor dielectric film.

Abstract: A barrier for terminating the edge of a semiconductor die such as a dynamic random access memory device is disclosed. The barrier reduces contamination of the dielectric layers such as TEOS and BPSG from mobile ions which are inherent in fabrication materials. While the barrier can be formed at many points in the die fabrication process, its formation is preferably incorporated into the Metal1 mask, thereby preventing the need for an additional mask step. The barrier, if formed with the Metal1 mask, would therefore be formed from the material of the Metal1, conventionally tungsten, a tungsten alloy, or other metals.

Abstract: A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.

Abstract: A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed.

Abstract: The invention provides a trench sidewall structure and a method of forming and using the same to reduce parasitic sidewall leakage through a trench sidewall, for example from bitline contact to storage node or from storage node to substrate. The method involves placing a polysilicon layer of the same polarity as that of the array well, along with a diffusion barrier layer such an titanium nitride, between the storage node poly and the oxide collar.

Abstract: A power MOS semiconductor device, such as a vertical MOSFET, IGBT, and IPD, includes a body of semiconductor material having a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and formed in the first semiconductor layer to provide a channel, a third semiconductor layer having the first conductivity type and formed in the second semiconductor layer, a trench formed in the first semiconductor layer across the third and second semiconductor layers, a gate insulating film covering a surface of the trench and extending to a surface of the third semiconductor layer, a gate electrode layer provided on the gate insulating film, and a buried layer having the first conductivity type provided in the first semiconductor layer so as to be contiguous to a bottom of the trench.

Abstract: A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

Abstract: In a semiconductor memory device having a memory cell comprising a switching transistor and a storage capacitor, a storage electrode of the capacitor is formed of at least part of a poly-silicon film deposited on an insulating film selectively formed on a silicon substrate, and the transistor comprises a MOS transistor having a channel region formed in a silicon epitaxial layer grown on the silicon substrate simultaneously with the deposition of said poly-silicon film, and has a source region at least part of which is formed in at least part of said poly-silicon film.

Abstract: A lateral heterojunction bipolar transistor (LHBT) comprises emitter and/or collector regions forming a p-n heterojunctions at the emitter/base junction and at the collector/base junction with a planar base region wherein at least the emitter region is formed by employing impurity induced disordering (IID) to produce emitter or collector region of wider bandgap than the base region. The lateral heterojunction bipolar transistor of this invention can also double as a hetero transverse junction (HTJ) laser.