Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.

Abstract: A method for forming transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell area and periphery area, wherein the cell area comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery area comprises numerous periphery P-type regions and numerous periphery N-type regions; covering the first P-type region, the second P-type region and the periphery P-type regions by a first photoresist; forming numerous N-type sources and numerous N-type drains in the first P-type region, the second P-type region and the periphery P-type regions. Remove the first photoresist.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs each having a gate connected to any one of the word lines and a source-drain path interposed between one of the paired bit lines on the one hand and a terminal of any one of the data storage capacitors on the other hand. A positive internal voltage higher than a circuit ground potential is generated and fed as a bias voltage to P-type regions wherein address selection MOSFETs of dynamic memory cells are formed.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and formed at both sides of the gate electrode. In a transistor that is turned on/off depending on a voltage applied to the gate electrode, a region where the gate electrode and the source/drain overlap is maintained to have the same voltage by the auxiliary electrode by always applying a high voltage to the auxiliary electrode upon an on operation of the transistor even when the gate electrode becomes a zero (0) volt upon a refresh operation of a DRAM device. Therefore, the present invention can prevent generation of GIDL current. Further, even though the gate electrode is continuously turned on/off, the auxiliary electrode always maintains the same voltage between the gate electrode and the bit line.

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A vertical read-only memory (ROM) is provided, which includes a gate on a substrate, a source/drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the side-walls of the trench. The polysilicon bit-line electrically connects with the source/drain. The substrate of the side-wall of the trench adjacent to the gate serves as a coding region.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: A semiconductor device suppressing increase of the number of types of exposure mask for implantations, preventing complication of manufacturing steps and suppressing the manufacturing cost and manufacturing steps therefor are provided. An impurity implantation region (R81) is formed by first implantation with an exposure mask for implantation having an opening at the lower right and this exposure mask for implantation is turned over for forming another impurity implantation region (R82) by second implantation, thereby forming three types of impurity implantation regions including the impurity implantation region (R81) formed through the first implantation, the impurity implantation region (R82) formed through the second implantation and still another impurity implantation region (R83) formed through the first implantation and the second implantation. Four types of regions inclusive of a region (R84) not subjected to impurity implantation can be formed with a single type of exposure mask for implantation.

Abstract: An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and a second semiconductor zone of the first conductivity type adjoining the first semiconductor zone and doped more weakly than the first semiconductor zone in a region near a front side, a first component region in the body having at least one semiconductor zone of a second conductivity type, a second component region in the body having at least one semiconductor zone of the second conductivity type, and a conversion structure having a semiconductor zone of the second conductivity type and a semiconductor zone of the first conductivity type that are short-circuited and disposed at a distance from the first semiconductor zone between the first and second component regions in the second semiconductor zone.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.

Abstract: In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers.

Abstract: A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.

Abstract: In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).

Abstract: A liquid crystal device, which is an example of an electro-optical device, includes a TFT, a data line, a scanning line, a second capacitor electrode, and a pixel electrode, all formed on a TFT array substrate. The pixel electrode and the TFT are electrically connected to each other via a conductive layer and via two contact holes. A second storage capacitor is formed between the second capacitor electrode and a part of the conductive layer, wherein a part of a second insulating thin film is disposed between the second capacitor electrode and the part of the conductive layer. The second insulating thin film is formed of an oxide film obtained by oxidizing the scanning line and the second capacitor electrode.

Abstract: A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing.

Abstract: Provided is a substrate of a semiconductor integrated circuit which can easily manufacture an integrated circuit having a soft error resistance, a latch up resistance and an ESD resistance increased. A thickness of a semiconductor surface layer having a lower impurity concentration than that of each of substrate single crystals 51 and 55 is varied according to a resistance which should be possessed by each section such as a memory cell section 5, a logic section 6, an input-output section 8 or the like for a region where each section is to be formed.

Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

Abstract: A capacitor has a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover layer formed on an insulation substrate made of an organic film or a ceramic material, and through holes formed at positions corresponding to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package, with electrodes for connection to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package provided within through holes. In a method for mounting the capacitor, the capacitor is interposed between a flip-chip connected semiconductor element and a mounting substrate.

Abstract: A redundant circuit of the semiconductor memory device is composed of a fuse block which assigns addresses of defective memory cells by selectively disconnecting fuses of the fuse block, address latches which individually generate and hold fuse information depending on whether the fuses are supplied with currents or not at the time of initialization, a redundant circuit-selecting latch which generates and holds fuse information depending on whether a redundant circuit-selecting fuse is supplied with a current or not and outputs a terminal voltage of the redundant circuit-selecting fuse at the time of initialization, and a N-type MOS transistor which forms returning paths of the currents flowing through the fuses of the fuse block in accordance with the terminal voltage of the redundant circuit-selecting fuse.

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract: A semiconductor device and a method for fabricating the same which improve characteristic of stand-by current of an SRAM cell is disclosed in the present invention.

Abstract: In the semiconductor storage device, a dummy P+ diffusion region which does not contribute to a storage operation is formed in the vicinity of two P+ diffusion regions constituting a storage node. Moreover, a dummy N+ diffusion region which does not contribute to the storage operation is formed in the vicinity of N+ diffusion regions FL210 and FL220 constituting a storage node. Consequently, a part of electrons generated in a P well region PW by irradiation of &agr; rays or neutron rays can be collected into the dummy N+ diffusion region FL250, and a part of holes generated in an N well region NW by the irradiation of the &agr; rays or the neutron rays can be collected into the dummy P+ diffusion region FL150.

Abstract: A semiconductor device and a method of producing the semiconductor device, fabricated by forming a memory device and a logic device on a single semiconductor substrate, are provided. A side wall (9) and a silicide protection film (10) of a gate electrode (7e) are used instead of forming a silicide protection film in a logic device region (101), whereby the number of steps in forming a logic process consolidating device can be reduced. Further, high concentration impurity regions are formed using the silicide protection film (10) as a mask, whereby a degree of freedom of a condition of implanting ions becomes high.

Abstract: In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.

Abstract: An improved silicon on sapphire structure and/or device has one or more buffer layers. In a first preferred embodiment, the buffer layer is layer of silicon oxide material that prevents the stress induced defects in the silicon layer. In an alternative embodiment, the buffer layer comprises two layers. A first silicon oxide layer attached to the silicon to insure a perfect interface between the silicon. A second silicon oxide layer then is attached to the sapphire layer. The first and second silicon oxide layers are then attached, e.g., by a wafer bonding technique. This structure has no conductive paths beneath the oxide insulator(s) and therefore enables improved performance in radio frequency applications.

Abstract: A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Abstract: A semiconductor device has a plurality of basic units formed on a semiconductor substrate, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element formed in a second active region and having second and third gate electrodes and source/drain regions with silicide layers, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor for connecting the storage electrode and third gate electrode. A semiconductor device is provided which has a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration.

Abstract: A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Abstract: There is provided a semiconductor device including a transistor formed by means of a common contact hole that connects a gate electrode, and a diffused layer forming a source/drain terminal; and a semiconductor device comprising the gate electrode of the transistor, and a connecting terminal to which capacitance between substrates and capacitance between the gate electrode and the source/drain terminal are added, thereby improving the soft error resistance caused by alpha rays and neutron beams.

Abstract: A semiconductor chip having circuits which are produced in at least one layer of a semiconductor substrate and are arranged in at least one group. The semiconductor chip has at least one conductive protective layer which is arranged above at least one such circuit group and is electrically connected to at least one of the circuits. The substrate has at least one protective sensor, and the detection connection(s) of the protective sensor/protective sensors is/are connected to the conductive protective layer or to at least one of the conductive protective layers. Output connections of the protective sensor/protective sensors are connected to at least one of the circuits such that the circuit(s) cannot operate properly if there is a defined, nonvolatile level at the output of the protective sensor(s).

Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a capacity device, (c) an interlayer insulating layer formed between the semiconductor substrate and the capacity device for electrically isolating them with each other, the interlayer insulating layer being formed below the capacity device with a contact hole therethrough, (d) a contact plug composed of an electrically conductive material and formed in the contact hole, (e) a first film composed of a first material through which hydrogen is not allowed to pass, and formed between the interlayer insulating layer and capacity device, (f) a second film composed of a second material through which hydrogen is not allowed to pass, and formed on an inner wall of the contact hole, (g) a third film composed of a third material through which hydrogen is not allowed to pass, and formed to cover an upper surface of the capacity device therewith, and (h) a fourth film composed of a fourth material through which hydrogen is not allowed t

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.

Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

Abstract: A method for fabricating a bit line junction in a DRAM array device which improves the doping profile in the channel region. The method includes contradoping via ion implantation through the bit line contact opening made in the device during processing. This particular doping method increases the concentration of dopants in the channel region on the bit line side of the array, without a corresponding increase of dopants on the buried strap side. Such a doping profile results in an improvement in the off current behavior of the device. Depending on the aspect ratio of the contact opening, tilt angles for the ion implantation are possible and can be adjusted for maximum off current efficiency.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: An improved memory cell (600) for use in a high-intensity light environment. The memory (600) comprises a substrate (616) capable of generating photocarriers when exposed to radiant energy, at least one transistor (602), at least one capacitor (604), and address node (610) electrically connecting the transistor (602) and the capacitor (604), and an active collector region (626). The active collector region (626) is fabricated in the substrate (616) in a position to allow the active collector region (626) to recombine photocarriers traveling through the substrate (616) thus preventing the photocarriers from reaching the address node (610).

Abstract: A semiconductor integrated circuit device and a method of manufacturing such a device provides the advantages that undulations are prevented from being produced in the polycrystal silicon plugs in the bit line contact holes and that the undesired phenomenon of transversally etching the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines BL formed at the time of forming a first wiring layer 18 is made of a laminate film having a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c and a titanium silicide film 20 containing nitrogen or oxygen is formed in the contact areas of the bit lines BL and the plugs 19. A titanium silicide film 20 containing nitrogen or oxygen is also formed in the contact areas of the first wiring layer 18 and the semiconductor substrate 1.

Abstract: A semiconductor device has a plurality of basic units formed on a semiconductor substrate, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element formed in a second active region and having second and third gate electrodes and source/drain regions with silicide layers, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor for connecting the storage electrode and third gate electrode. A semiconductor device is provided which has a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration.

Abstract: A preparation for forming a thin film capacitor includes forming an amorphous ferroelectric film, such as barium strontium titanate [(Ba,Sr)TiO3] film, for use as an interface between a metal electrode and a polycrystalline ferroelectric film, such as (Ba,Sr) TiO3 film. The polycrystalline ferroelectric film serves as a dielectric layer of the thin film capacitor in view of the fact that the polycrystalline ferroelectric film has a high dielectric constant. The amorphous ferroelectric film serves as a buffer layer for inhibiting the leakage current of the thin film capacitor. The amorphous ferroelectric film is grown by sputtering and by introducing a working gas, such as argon, and a reactive gas, such as oxygen, into a reaction chamber in which a plasma is generated at room temperature.