Capacitor For Signal Storage In Combination With Non-volatile Storage Means Patents (Class 257/298)
  • Patent number: 10734399
    Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Haitao Liu, Jin Chen, Guangyu Huang, Mojtaba Asadirad
  • Patent number: 10685962
    Abstract: Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacrturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xi Lin, Yi Hua Shen
  • Patent number: 10672771
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
  • Patent number: 10658480
    Abstract: A memory device includes plural electrode layers stacked in a first direction, a semiconductor layer interacting with the plural electrode layers and extending in the first direction, a first insulating film provided between the semiconductor layer and at least one electrode layer and extending along the semiconductor layer in the first direction, and a charge trapping film provided between the electrode layer and the first insulating film. The memory device further includes a second insulating film provided between the charge trapping film and the first insulating film and in contact with the first insulating film. In a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level that is closer to the conduction band of the semiconductor layer than the first trap level.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Ryuji Ohba
  • Patent number: 10651094
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Aono, Tetsuya Yoshida, Makoto Ogasawara, Shinichi Okamoto
  • Patent number: 10515799
    Abstract: The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 24, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiao Jun Wang, Wei Zhou, Lin Kang Xu, Guan Nan Li
  • Patent number: 10510538
    Abstract: Representative systems and methods for preventing or otherwise reducing extreme-ultraviolet-induced material property changes (e.g., layer thickness shrinkage) include one or more thermal treatments to at least partially stabilize a material forming a material layer disposed over a substrate prior to extreme ultraviolet (EUV) exposure (e.g., wavelengths spanning about 124 nm to about 10 nm) attendant to photolithographic processing. Representative systems and methods provide for reduction of average compressive stress in a material layer after thermal treatment prior to extreme EUV photolithographic patterning. Representative thermal treatments may include one or more annealing processes, ultraviolet (UV) radiation treatments, ion implantations, ion bombardments, plasma treatments, surface baking treatments, surface coating treatments, surface ashing treatments, or pulsed laser treatments.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Ying Li
  • Patent number: 10497715
    Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Chet E. Carter, Cole Smith, Collin Howder, Richard J. Hill, Jie Li
  • Patent number: 10453853
    Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 22, 2019
    Assignee: THIN FILM ELECTRONICS ASA
    Inventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
  • Patent number: 10424585
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10416197
    Abstract: An apparatus for measuring an electric current in an electrical conductor, wherein the apparatus comprises a detection apparatus for detecting the electric current, wherein the apparatus comprises a shielding apparatus for shielding a coupling between the electrical conductor and the detection apparatus, wherein the shielding apparatus is designed in such a way that the shielding of the coupling can be controlled.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: September 17, 2019
    Assignee: Dr. Ing. h.c. F. Porsche Aktiengesellschaft
    Inventors: Stefan Götz, Hermann Dibos
  • Patent number: 10388855
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, wherein as viewed in a direction parallel to a stacked direction of the stacked structure, a pattern of a lower surface of the first magnetic layer is located inside a pattern of an upper surface of the first magnetic layer, and a pattern of an upper surface of the second magnetic layer is located inside a pattern of a lower surface of the second magnetic layer or substantially conforms to the pattern of the lower surface of the second magnetic layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa, Kenji Noma
  • Patent number: 10276430
    Abstract: Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 30, 2019
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Zhiyong Wang, Dejin Wang, Jingjing Ma
  • Patent number: 10262967
    Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joo Hwang, Eun-Seok Song
  • Patent number: 10249627
    Abstract: A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hoon Han, Dong Wan Kim, Ji Hun Kim, Jae Joon Song, Hiroshi Takeda
  • Patent number: 10147776
    Abstract: Disclosed are a display device and a method of manufacturing the same. In the disclosed display device, a pad cover electrode disposed on a pad area comes into contact with an upper surface and a side surface of a pad electrode since a planarization layer is disposed on an active area excluding the pad area, which may prevent contact failure between the pad cover electrode and a conductive ball. In addition, in the display device, a first electrode, which is connected to a thin film transistor via a pixel connection electrode, is formed via the same mask process as the planarization layer so that it has a line width similar to that of the planarization layer and overlaps the planarization layer, which may simplify a structure and a manufacturing process.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 4, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Hee Nam, Jeong-Oh Kim, Jung-Ho Bang, Jung-Sun Beak, Jong-Won Lee
  • Patent number: 10109575
    Abstract: A method for forming a semiconductor structure having a non-planar MIM capacitor is provided. The method includes forming a first dielectric layer on a base structure that has one or more recesses each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10014325
    Abstract: A semiconductor device which can retain data for a long period is provided. The semiconductor device includes a memory circuit and a retention circuit. The memory circuit includes a first transistor and the retention circuit includes a second transistor. The memory circuit is configured to write data by turning on the first transistor and to retain the data by turning off the first transistor. The retention circuit is configured to supply a first potential at which the first transistor is turned off to a back gate of the first transistor by turning on the second transistor and to retain the first potential by turning off the second transistor. The first transistor and the second transistor have different electrical characteristics.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 3, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Ryota Hodo, Shunpei Yamazaki
  • Patent number: 10003257
    Abstract: A DC to DC converter for converting voltage between two voltage levels is described. The converter comprises a plurality of capacitors and switch units and is controllable between a first and second commutation state. In the first commutation state, the converter is configured for connection to higher voltage terminals and the capacitors are connected in series. In the second commutation state, the converter is configured for connection to lower voltage terminals, and the capacitors are connected to form at least two branches connected in parallel, the branches comprising a series connection of at least two capacitors. In some embodiments, one or more intermediate commutation states may also be provided.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: June 19, 2018
    Assignee: ALSTOM TECHNOLOGY LTD
    Inventors: Carl Barker, Jose Maneiro
  • Patent number: 9997610
    Abstract: Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Aritra Dasgupta, Oleg Gluschenkov, Balaji Kannan, Unoh Kwon
  • Patent number: 9935135
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 3, 2018
    Assignee: SONY CORPORATION
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Patent number: 9887300
    Abstract: A transistor with small parasitic capacitance is provided. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor includes a first region, a second region, and a third region. The oxide semiconductor includes a fourth region, a fifth region, and a sixth region. The first region has a region where the first region and the sixth region overlap each other with the first insulator positioned therebetween. The second region has a region where the second region and the second conductor overlap each other with the first insulator and the second insulator positioned therebetween. The third region has a region where the third region and the third conductor overlap each other with the first insulator and the second insulator positioned therebetween. The fourth region has a region in contact with the second conductor.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9853048
    Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: December 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Jeong Kim, O Ik Kwon, Jong Kyoung Park, Su Jee Sunwoo
  • Patent number: 9818833
    Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 14, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura
  • Patent number: 9754661
    Abstract: A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an element isolation region overlying the main surface; a first and a second active region located in the n-type well region and surrounded by the element isolation region; an insulating film overlying the main surface in the first active region; a semiconductor layer overlying the insulating film; a gate electrode layer overlying the semiconductor layer through a gate insulating film; a p-type source and a drain region formed in the semiconductor layer at both ends of the gate electrode layer; a dummy gate electrode layer overlying the semiconductor layer through the gate insulating film; an n-type semiconductor region overlying an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 9728544
    Abstract: A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tea Kwang Yu, Yong Tae Kim, Jae Hyun Park, Kyong Sik Yeom
  • Patent number: 9716102
    Abstract: A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: July 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JinGyun Kim, Myoungbum Lee, Seungmok Shin
  • Patent number: 9691907
    Abstract: A non-volatile memory device includes a plurality of memory cells. Each memory cell includes a vertical channel, a control gate, a floating gate, and an erase gate disposed on a substrate. The vertical channel extends upwards in a vertical direction. The control gate, the floating gate, and the erase gate surround the vertical channel respectively, and a part of the floating gate is surrounded by the control gate. The erase gate is disposed between the substrate and the floating gate in the vertical direction, and the floating gate include a tip extending toward the erase gate. The vertical channel and electrodes surrounding the vertical channel, such as the control gate, the floating gate, and the erase gate, are used to reduce the area of the memory cell on the substrate of the non-volatile memory device in the present invention. The density of the memory cells may be enhanced accordingly.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Shih-Chang Huang
  • Patent number: 9685211
    Abstract: The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeunghwan Park, Sunghoon Kim
  • Patent number: 9679909
    Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 13, 2017
    Assignee: Taiwan Samiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Yu-Hsiung Wang, Chen-Chin Liu
  • Patent number: 9679641
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • Patent number: 9646979
    Abstract: To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (1), while each of the memory transistor (MGA1) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell (3a) is turned on by applying a high voltage to one end of a memory transistor (MGA1) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL1), a voltage drop occurs in a low-concentration impurity extension region (ET2) in the memory transistor (MGA1) between the source line (SL) and the bit line (BL1) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 9, 2017
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 9633944
    Abstract: A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a stack structure including conductive layers stacked in a step shape, a first interlayer insulating layer formed over the stack structure, the first interlayer insulating layer including contact holes with a uniform depth, which expose the conductive layers, lower contact plugs formed in the contact holes, the lower contact plugs being respectively contacted with the conductive layers, and lower contact pads respectively connected to the contact plugs.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 25, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hae Soo Kim
  • Patent number: 9595535
    Abstract: Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: March 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Takuya Ariki, Toru Miwa
  • Patent number: 9589981
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: March 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Hiroaki Koketsu, Johann Alsmeier
  • Patent number: 9570456
    Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 14, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Jen, Chao-Sheng Cheng
  • Patent number: 9570511
    Abstract: Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.
    Type: Grant
    Filed: April 30, 2016
    Date of Patent: February 14, 2017
    Assignee: SK hynix Inc.
    Inventors: Seok-Pyo Song, Sung-Woong Chung, Jong-Han Shin
  • Patent number: 9570575
    Abstract: Aspects include a semiconductor structure and fabrication method. A semiconductor structure may include alternating first and second crystalline layers and a capacitor. The capacitor may include a first terminal, a second terminal, and a dielectric. The first terminal may include a first central portion and first lobes extending laterally from the first central portion. The second terminal may include a second central portion and second lobes extending laterally from the second central portion. A portion of the second lobes may be fitted between consecutive first lobes. The fabrication method may include forming alternating first and second crystalline layers, forming a first trench, selectively etching the first crystalline layers within the first trench, depositing a dielectric in the first trench, filling the first trench with a metal, forming a second trench, etching the first and second crystalline layers within the second trench, and filling the second trench with a metal.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9559178
    Abstract: A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. A charge storage layer is formed over the capacitor region and the memory region including over the select gate and the plurality of lines. A control gate layer is formed over the charge storage layer over the capacitor region and over the memory region. The control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of a capacitor over the capacitor region. The plurality of lines are connected to the capacitor region to form a second electrode of the capacitor.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Satoshi Sekine, Cheong Min Hong
  • Patent number: 9536872
    Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventor: Hartmud Terletzki
  • Patent number: 9530834
    Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a patterned first conductive layer on the material layer, forming a first dielectric layer on the patterned first conductive layer; forming a second conductive layer and a cap layer on the first dielectric layer; removing part of the cap layer to form a spacer on the second conductive layer; and using the spacer to remove part of the second conductive layer for forming a trench above the patterned first conductive layer and fin-shaped structures adjacent to the trench.
    Type: Grant
    Filed: December 13, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin
  • Patent number: 9520504
    Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 13, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima
  • Patent number: 9425205
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and a charge storage film. The stacked body includes a plurality of electrode layers crosswise extending in a first direction and second direction crossing the first direction, the plurality of electrode layers separately stacked each other in a third direction crossing the first direction and second direction. The semiconductor body extends in the third direction and provided in the stacked body. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiro Shimura
  • Patent number: 9417208
    Abstract: A method for operating a sensor for biomolecules or charged ions, the sensor comprising a first field effect transistor (FET) and a second FET, wherein the first FET and the second FET comprise a shared node includes placing an electrolyte containing the biomolecules or charged ions on a sensing surface of the sensor, the electrolyte comprising a gate of the second FET; applying an inversion voltage to a gate of the first FET; making a first electrical connection to an unshared node of the first FET; making a second electrical connection to unshared node of the second FET; determining a change in a drain current flowing between the unshared node of the first FET and the unshared node of the second FET; and determining an amount of biomolecules or charged ions contained in the electrolyte based on the determined change in the drain current.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald Dorman, Tak Ning, Sufi Zafar
  • Patent number: 9412597
    Abstract: The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 9385161
    Abstract: A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 5, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hae Chan Park
  • Patent number: 9337195
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including a gate dielectric and a gate disposed over the gate dielectric, and reshaping a top surface of the gate to form a gate with a rounded profile.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Ching Chang, I-Yin Lu, Jih-Jse Lin, Chao-Cheng Chen
  • Patent number: 9324726
    Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 26, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Kawashima, Hiraku Chakihara, Kyoko Umeda, Akio Nishida
  • Patent number: 9299716
    Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Woon-Kyung Lee, Won-Seok Cho
  • Patent number: 9281476
    Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Peking University
    Inventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang