Abstract: Some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. The charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the stack. Charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. The charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.

Abstract: A system may include a first conductive plate configured at least to receive an input signal. The system may include a second conductive plate configured at least to output an output signal. The system may further include a memristor material positioned between the first conductive plate and the second conductive plate.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier layer and a top electrode. The first dielectric layer is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer. A contact area between the oxygen exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.

Abstract: The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The invention also provides a manufacturing method for manufacturing the above-mentioned split gate flash memory cell, and the manufacturing method provided by the invention can be compatible with the existing manufacturing process of the split gate flash memory cell without increasing the process cost and the process complexity.

Abstract: An electric double layer capacitor includes a plurality of current collector plates, an electrode layer formed on one surface of each of the current collector plates, and a plurality of separators which extend through the electrode layer from one surface of each of the current collector plates in a continuous pattern of a predetermined design and in which a repeated pattern is formed in the length and width directions of the current collector plates.

Abstract: A package structure and method for forming the same are provided. The package structure includes a conductive layer formed over a first substrate, and a dielectric layer formed over the conductive layer. The package structure includes a metal-insulator-metal (MIM) capacitor embedded in the dielectric layer, and a shielding layer formed over the MIM capacitor. The shielding layer is insulated from the MIM capacitor by the dielectric layer. The package structure also includes a first through via formed through the MIM capacitor, and the first through via is connected to the conductive layer, and the first through via is insulated from the shielding layer.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures for subtractively forming a top via using a hybrid metallization scheme. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a topmost surface of a first liner layer. The first liner layer can be positioned between the conductive line and a dielectric layer. A top via layer is formed on the recessed surface of the conductive line and a hard mask is formed over a first portion of the top via layer. A second portion of the top via layer is removed. The remaining first portion of the top via layer defines the top via. The conductive line can include copper while the top via layers can include ruthenium or cobalt.

Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.

Abstract: There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A gate on array (GOA) circuit with capacitors connected in parallel includes a plurality of cascading GOA units. An nth GOA unit includes: a pull-up control circuit unit, a pull-up circuit unit, a pass-down circuit unit, a pull-down circuit unit, a pull-down maintaining circuit unit, and a bootstrap capacitor. The bootstrap capacitor is divided into a plurality of first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, a connecting line of at least one of the first capacitors being unable to store is cut off.

Abstract: A semiconductor memory device, with which a manufacturing method is associated, includes a substrate. The semiconductor memory device also includes a source structure disposed on a first region of the substrate, memory cell strings connected to the source structure, and a capacitor structure disposed on a second region of the substrate. The capacitor structure is spaced apart from the source structure in a horizontal direction.

Abstract: A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

Abstract: A display device includes a substrate, a semiconductor layer on the substrate, a first insulating layer on the semiconductor layer, a first conductive layer on the semiconductor layer, a second insulating layer on the first conductive layer, a first contact hole penetrating the first insulating layer and the second insulating layer, a second conductive layer on the second insulating layer, connected to the semiconductor layer through the first contact hole, and including a hydrogen barrier material, and a third insulating layer on the second conductive layer.

Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.

Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.

Abstract: Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.

Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

Abstract: Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.

Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.

Abstract: A memory device includes plural electrode layers stacked in a first direction, a semiconductor layer interacting with the plural electrode layers and extending in the first direction, a first insulating film provided between the semiconductor layer and at least one electrode layer and extending along the semiconductor layer in the first direction, and a charge trapping film provided between the electrode layer and the first insulating film. The memory device further includes a second insulating film provided between the charge trapping film and the first insulating film and in contact with the first insulating film. In a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level that is closer to the conduction band of the semiconductor layer than the first trap level.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.

Abstract: Representative systems and methods for preventing or otherwise reducing extreme-ultraviolet-induced material property changes (e.g., layer thickness shrinkage) include one or more thermal treatments to at least partially stabilize a material forming a material layer disposed over a substrate prior to extreme ultraviolet (EUV) exposure (e.g., wavelengths spanning about 124 nm to about 10 nm) attendant to photolithographic processing. Representative systems and methods provide for reduction of average compressive stress in a material layer after thermal treatment prior to extreme EUV photolithographic patterning. Representative thermal treatments may include one or more annealing processes, ultraviolet (UV) radiation treatments, ion implantations, ion bombardments, plasma treatments, surface baking treatments, surface coating treatments, surface ashing treatments, or pulsed laser treatments.

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

Abstract: An apparatus for measuring an electric current in an electrical conductor, wherein the apparatus comprises a detection apparatus for detecting the electric current, wherein the apparatus comprises a shielding apparatus for shielding a coupling between the electrical conductor and the detection apparatus, wherein the shielding apparatus is designed in such a way that the shielding of the coupling can be controlled.

Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, wherein as viewed in a direction parallel to a stacked direction of the stacked structure, a pattern of a lower surface of the first magnetic layer is located inside a pattern of an upper surface of the first magnetic layer, and a pattern of an upper surface of the second magnetic layer is located inside a pattern of a lower surface of the second magnetic layer or substantially conforms to the pattern of the lower surface of the second magnetic layer.

Abstract: Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.

Abstract: Disclosed are a display device and a method of manufacturing the same. In the disclosed display device, a pad cover electrode disposed on a pad area comes into contact with an upper surface and a side surface of a pad electrode since a planarization layer is disposed on an active area excluding the pad area, which may prevent contact failure between the pad cover electrode and a conductive ball. In addition, in the display device, a first electrode, which is connected to a thin film transistor via a pixel connection electrode, is formed via the same mask process as the planarization layer so that it has a line width similar to that of the planarization layer and overlaps the planarization layer, which may simplify a structure and a manufacturing process.

Abstract: A method for forming a semiconductor structure having a non-planar MIM capacitor is provided. The method includes forming a first dielectric layer on a base structure that has one or more recesses each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.

Abstract: A semiconductor device which can retain data for a long period is provided. The semiconductor device includes a memory circuit and a retention circuit. The memory circuit includes a first transistor and the retention circuit includes a second transistor. The memory circuit is configured to write data by turning on the first transistor and to retain the data by turning off the first transistor. The retention circuit is configured to supply a first potential at which the first transistor is turned off to a back gate of the first transistor by turning on the second transistor and to retain the first potential by turning off the second transistor. The first transistor and the second transistor have different electrical characteristics.

Abstract: A DC to DC converter for converting voltage between two voltage levels is described. The converter comprises a plurality of capacitors and switch units and is controllable between a first and second commutation state. In the first commutation state, the converter is configured for connection to higher voltage terminals and the capacitors are connected in series. In the second commutation state, the converter is configured for connection to lower voltage terminals, and the capacitors are connected to form at least two branches connected in parallel, the branches comprising a series connection of at least two capacitors. In some embodiments, one or more intermediate commutation states may also be provided.

Abstract: Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.

Abstract: A transistor with small parasitic capacitance is provided. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor includes a first region, a second region, and a third region. The oxide semiconductor includes a fourth region, a fifth region, and a sixth region. The first region has a region where the first region and the sixth region overlap each other with the first insulator positioned therebetween. The second region has a region where the second region and the second conductor overlap each other with the first insulator and the second insulator positioned therebetween. The third region has a region where the third region and the third conductor overlap each other with the first insulator and the second insulator positioned therebetween. The fourth region has a region in contact with the second conductor.

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.