Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: A semiconductor device in which an increase in circuit area is inhibited is provided. The semiconductor device includes a first circuit layer and a second circuit layer over the first circuit layer; the first circuit layer includes a first transistor; the second circuit layer includes a second transistor; a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor; a source and a drain of the second transistor are electrically connected to the other of the source and the drain of the first transistor; and a semiconductor layer of the second transistor contains a metal oxide.

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Abstract: A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor.

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

Abstract: A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

Abstract: A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

Abstract: A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n?4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a conductive pattern, a support structure, a first conductive layer, and a dielectric layer. The conductive pattern extends vertically from the substrate. The support structure extends from an outer sidewall of the conductive pattern. The first conductive layer covers the conductive pattern. The dielectric layer at least covers the first conductive layer and the support structure.

Abstract: An organic light-emitting diode (OLED) display is disclosed.

Abstract: The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A nanopore cell includes a conductive layer. The nanopore cell further includes a titanium nitride (TiN) working electrode disposed above the conductive layer. The nanopore cell further includes insulating walls disposed above the TiN working electrode, wherein the insulating walls and the TiN working electrode form a well into which an electrolyte may be contained. In some embodiments, the TiN working electrode comprises a spongy and porous TiN working electrode that is deposited by a deposition technique with conditions tuned to deposit sparsely-spaced TiN columnar structures or columns of TiN crystals above the conductive layer.

Abstract: In an embodiment, a method of forming a neural network circuit may include forming a dielectric layer overlying a semiconductor substrate that has active devices formed in the semiconductor substrate. An opening may be formed in the dielectric layer, and a series connected resistor and diode may be formed within the opening.

Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.

Abstract: A text log feature vector generator generates a text log feature vector on the basis of a text log. A numerical log feature vector generator generates a numerical log feature vector on the basis of a numerical log. A system feature vector generator generates a system feature vector on the basis of the text log feature vector and the numerical log feature vector. A learning unit learns a plurality of appearance values of the system feature vector to generate a system state model as a model indicating a state of the system. A determination unit determines the state of the system at determination target time on the basis of the system feature vector at the determination target time and the system state model.

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode. The dielectric layer is made of at least one selected from the group consisting of a hafnium oxide and a zirconium oxide. A thickness of the dielectric layer is 12 nm or more. The dielectric layer has a monoclinic crystal system structure. A concentration of hydrogen in the dielectric layer is 2.5×1021 atoms/cm3 or less.

Abstract: A capacitor includes a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor is coupled to the first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. In a normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor through the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor through the control circuit. In a power saving mode, the control circuit turns off the first transistor and the second transistor.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Abstract: An anti-fuse structure includes a substrate, an active layer, an electrode layer, and a dielectric layer. The active layer is on the substrate and has a body portion and a convex portion protruding from the body portion. The electrode layer is on the active layer and partially overlaps the convex portion of the active layer. The electrode layer has a hollow region, and the convex portion of the active layer is in the hollow region. The dielectric layer is between the active layer and the electrode layer.

Abstract: A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Abstract: Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode. The dielectric layer is made of at least one selected from the group consisting of a hafnium oxide and a zirconium oxide. A thickness of the dielectric layer is 12 nm or more. The dielectric layer has a monoclinic crystal system structure. A concentration of hydrogen in the dielectric layer is 2.5×1021 atoms/cm3 or less.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.

Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

Abstract: The present technology relates to a communication system, and a transmission method that a restoration time from a state that a transmission of a signal between AC-coupled apparatuses is suspended can be shortened without increasing a power consumption. A first control signal is transmitted via the second signal line in a case where a transmission of the signal via the first signal line is restored from a suspended state, and that a transmission of a charging signal that charges an AC coupling capacitance serially connected to the first signal line via the first signal line is started before a timing when the transmission of the first control signal is ended. The present technology is applicable, for example, to a communication system in conformity with the eDP standard.

Abstract: Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the dielectric region, an insulative wall laterally surrounding a volume of the first semiconductor material, and a first doped region along a lower surface of the first semiconductor material. The first semiconductor material is patterned to form a pillar within a tub. The pillar has top and bottom portions. An upper doped region is formed within the pillar top portion. A dielectric liner is formed to extend along the pillar, and to extend along the bottom of the tub. Conductive gate material is formed within the tub and over the dielectric liner. The lower and upper doped regions within the pillar are first and second source/drain regions, respectively, and the conductive gate material includes a transistor gate which gatedly couples the first and second source/drain regions.

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.