With Means To Insulate Adjacent Storage Nodes (e.g., Channel Stops Or Field Oxide) Patents (Class 257/305)
  • Patent number: 12022647
    Abstract: A microelectronic device comprises memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures comprises a central portion in contact with a digit line, extending from the base material and comprising opposing arcuate surfaces, an end portion in contact with a storage node contact on a side of the central portion, and an additional end portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Stephen D. Snyder, Thomas A. Figura, Siva Naga Sandeep Chalamalasetty, Ping Chieh Chiang, Scott L. Light, Yashvi Singh, Yan Li, Song Guo
  • Patent number: 11996422
    Abstract: An electronic device includes: a capacitor; an insulating layer; at feast one trench provided in the insulating layer; and a first conductive plug, at least part of which is surrounded by the insulating layer. The capacitor includes: a first lower electrode provided along an inner wall of the at least one trench, a dielectric layer provided on the first lower electrode, and an upper electrode provided on the dielectric layer. At least part of the first conductive plug is positioned between an upper surface of the insulating layer and a lowermost portion of the at least one trench.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 28, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Takase, Shunsuke Isono, Yuuko Tomekawa
  • Patent number: 11950412
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 2, 2024
    Assignee: Longitude Flash Memory Solutions LTD.
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Patent number: 11943929
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11887889
    Abstract: A method of manufacturing a semiconductor device can include: forming an interlayer dielectric layer on an upper surface of a lower metal layer, the lower metal layer including first and second regions; forming a through hole extending from an upper surface of interlayer dielectric layer to the lower metal layer to expose the upper surface of the lower metal layer; forming a conductive layer covering a bottom part and sidewall parts of the through hole, and the upper surface of the interlayer dielectric layer; forming a first dielectric layer covering the first conductive layer on the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer above the upper surface of the interlayer dielectric layer.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: January 30, 2024
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Zheng Lv, Xunyi Song, Meng Wang
  • Patent number: 11855123
    Abstract: A display device including a base layer, a pixel circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulation layers, a first electrode electrically connected to the pixel circuit, a second electrode spaced apart from the first electrode, a light emitting element electrically connected to the first electrode and the second electrode, a first refraction layer disposed on the pixel circuit layer and having a first refractive index, and a second refraction layer disposed on the light emitting element and having a second refractive index larger than the first refractive index.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woongsik Kim, Saehee Han
  • Patent number: 11784216
    Abstract: A manufacturing method of a capacitive structure includes: providing a semiconductor base; forming a first mask layer on the semiconductor base, the first mask layer having a plurality of first round hole patterns distributed uniformly; forming first openings distributed uniformly on the semiconductor base by etching based on the first round hole patterns; forming a second mask layer on one side, away from the semiconductor base, of the first openings, and forming a plurality of second patterns on the second mask layer; forming second openings distributed uniformly on the semiconductor base by etching based on the second patterns; and etching the first openings and the second openings to form capacitive holes, and depositing a lower electrode layer, a dielectric layer and an upper electrode layer within the capacitive holes to form the capacitive structure.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 10, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chaojun Sheng
  • Patent number: 11758708
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 12, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11751403
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: September 5, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11729991
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11729995
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11716838
    Abstract: A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Yasuyuki Sakogawa
  • Patent number: 11676998
    Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: June 13, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11587785
    Abstract: An electronic apparatus is provided and includes a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the connecting material consists of a single material; and the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 21, 2023
    Assignee: Japan Display Inc.
    Inventors: Yoshikatsu Imazeki, Shoji Hinata
  • Patent number: 11502206
    Abstract: A semiconductor wafer manufacturing method including: forming a plurality of trench capacitors at a main surface of a semiconductor wafer, wherein each of the plurality of trench capacitors is configured as unit cells that internally include unit trench capacitors, and wherein a length component in a predetermined direction of a layout pattern of trenches of the plurality of trench capacitors is made equivalent, within a fixed tolerance range, to a length component in a direction that intersects the predetermined direction.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 15, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Shibata
  • Patent number: 10811420
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 20, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Szu-Han Chen, Hsu Chiang, Ching-Yuan Kuo
  • Patent number: 9556021
    Abstract: A method creates MEMS structures by selectively etching a silicon wafer that is patterned by using a masking layer. The method comprises depositing and patterning a first mask on a silicon wafer to define desired first areas on the wafer to be etched. First trenches are etched on parts of the wafer not covered by the first mask. The first trenches are filled with a deposit layer. A part of the deposit layer is removed on desired second areas to be etched and a remainder is left on areas to function as a second mask to define final structures. Parts of the wafer on the desired second areas is etched, and the second mask is removed. A gyroscope or accelerator can be manufactured by dimensioning the structures.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: January 31, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Altti Torkkeli
  • Patent number: 9077922
    Abstract: A solid state image pickup device is provided that includes a pixel array unit having a plurality of pixels and a signal processing circuit that has a capacitor operatively configured to process a respective signal output from each of the plurality of pixels. The capacitor is operatively configured as a stacked capacitor or a trench capacitor.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 7, 2015
    Assignee: SONY CORPORATION
    Inventors: Toshifumi Wakano, Keiji Mabuchi
  • Patent number: 9006810
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8932932
    Abstract: An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Anne Marie Kimball
  • Patent number: 8884350
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Patent number: 8865545
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se In Kwon
  • Patent number: 8846495
    Abstract: Disclosed is a bonding system which efficiently performs a bonding of a substrate to a support substrate, thereby improving the throughput in a bonding processing. The disclosed bonding system includes a loading/unloading station and a processing station. The processing station includes: an adhesive applying device configured to apply an adhesive to the wafer; a protective agent applying device configured to apply a protective agent to the wafer, a remover applying device configured to apply a remover to the support wafer, a heat processing device configured to heat the wafer or the support wafer which is applied with at least the adhesive, the protective agent or the remover, at a predetermined temperature, a bonding device configured to bond the wafer to the support wafer through the adhesive, the protective agent and the remover, and a wafer transfer area configured to transfer the wafer, the support wafer or the bonded wafer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Masatoshi Deguchi
  • Patent number: 8841716
    Abstract: A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Wilfried E. Haensch, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20140252441
    Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
  • Patent number: 8816419
    Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 26, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8772850
    Abstract: A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
  • Patent number: 8753906
    Abstract: A method for manufacturing a structure having a textured surface, including a substrate made of mineral glass having a given texture, for an organic-light-emitting-diode device, the method including supplying a rough substrate, having a roughness defined by a roughness parameter Ra ranging from 1 to 5 ?m over an analysis length of 15 mm and with a Gaussian filter having a cut-off frequency of 0.8 mm; and depositing a liquid-phase silica smoothing film on the substrate, the film being configured to smooth the roughness sufficiently and to form the textured surface of the structure.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: June 17, 2014
    Assignee: Saint-Gobain Glass France
    Inventors: Francois-Julien Vermersch, Hélène Gascon, Sophie Besson
  • Patent number: 8698147
    Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin-film transistor (TFT), which includes an active layer, a gate electrode, and source/drain electrodes; an organic electroluminescent device electrically connected to the TFT and includes a pixel electrode formed on the same layer as the gate electrode, an intermediate layer including an organic light emitting layer, and a counter electrode that are stacked in the order stated; and a capacitor, which includes a bottom electrode, which is formed on the same layer and of the same material as the active layer and is doped with an impurity; a top electrode formed on the same layer as the gate electrode; and a metal diffusion medium layer formed on the same layer as the source/drain electrodes and is connected to the bottom electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Na-Young Kim, Dae-Woo Lee
  • Patent number: 8693163
    Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Chi-Chun Hsieh, Tzu-Yu Wang, Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 8653596
    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8637378
    Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
  • Patent number: 8614472
    Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Syed S. Islam, Mansour Keramat
  • Patent number: 8598643
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaori Kawasaki, Yoshiaki Fukuzumi, Masaru Kito, Tomoko Fujiwara, Takeshi Imamura, Ryouhei Kirisawa, Hideaki Aochi
  • Patent number: 8592902
    Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Texas Instrument Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8587047
    Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Wei Ting, Shing-Hwa Renn, Yu-Teh Chiang, Chung-Ren Li, Tieh-Chiang Wu
  • Patent number: 8587048
    Abstract: Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 19, 2013
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Dong Hoon Park, Jin Hyo Jung, Min Kyung Ko
  • Patent number: 8569817
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Se In Kwon
  • Patent number: 8519463
    Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, Thomas M. Graettinger
  • Patent number: 8492817
    Abstract: An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Anne Marie Ebert, Johnathan E. Faltermeier
  • Patent number: 8492822
    Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Sung Lim, Chul-Ho Chung
  • Patent number: 8471322
    Abstract: A semiconductor device includes a wiring configured to be formed in a surface portion of a first interlayer insulating layer in a first region, a common upper electrode configured to be formed in a surface portion of the first interlayer insulating layer in a second region, a plurality of capacitance portions configured to have the common upper electrode as an upper electrode and be extended below, wherein an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Ken Inoue
  • Patent number: 8455327
    Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Xi Li, Geng Wang
  • Patent number: 8415732
    Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
  • Patent number: 8384143
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Patent number: 8367497
    Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 5, 2013
    Assignee: Agere Systems LLC
    Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 8350311
    Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kaneko, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
  • Patent number: 8338870
    Abstract: A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Heon Kim
  • Patent number: 8299515
    Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph E. Ervin, Yanli Zhang