Capacitor In Trench Patents (Class 257/301)
  • Patent number: 11121241
    Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, a first region formed in a surface layer of the first main surface, a drift layer disposed adjacent to the first region, a charge accumulation region having a higher concentration than the drift region, and a trench gate including a trench penetrating the first region and the charge accumulation region, and a gate electrode formed in the trench. The trench gate includes a main trench having a gate electrode to which a gate voltage is applied, and a dummy trench having a gate electrode to which a voltage different from the main trench is applied. The main trench and the dummy trench sandwiches the charge accumulation region, and a contact area S1 between the dummy trench and the charge accumulation region is larger than a contact area S2 between the main trench and the charge accumulation region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 14, 2021
    Assignee: DENSO CORPORATION
    Inventor: Hiromitsu Tanabe
  • Patent number: 11101271
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11094655
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Chang-Jung Hsueh, Chin-Wei Kang, Hui-Min Huang, Wei-Hung Lin, Cheng-Jen Lin, Ming-Da Cheng, Chien-Chun Wang
  • Patent number: 11094360
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 17, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi
  • Patent number: 11075265
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Zhen Zhang
  • Patent number: 11069688
    Abstract: Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing a bulk substrate with a first doped layer thereon, depositing a first hard mask over the substrate, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, where the grown second polysilicon material and epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 11062989
    Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 11053601
    Abstract: A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 6, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Adam M. Rowen, Robert K. Grubbs, Jonathan Joseph Coleman
  • Patent number: 11049932
    Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Steven M. Shank, Mark David Levy, Bruce W. Porth
  • Patent number: 11049862
    Abstract: A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: June 29, 2021
    Assignee: HeFeChip Corporation Limited
    Inventors: John Zhang, Yanzun Li, GuoLiang Zhu, Tongqing Chen, Huang Liu
  • Patent number: 11043496
    Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen W. Russell, Stephen H. Tang
  • Patent number: 11037942
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 11031460
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Patent number: 10991698
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 27, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10985173
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 10978368
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an insulating film, and a photo sensitive film. The substrate includes a semiconductor chip region and a scribe line region disposed along an edge of the semiconductor chip region. The insulating film includes a first portion disposed on the semiconductor chip region, a second portion disposed on the scribe line region and connected with the first portion, and a third portion disposed on the scribe line region and protruded in a first direction from the second portion. The photo sensitive film is disposed on the insulating film and has a sidewall exposed on the second portion of the insulating film. A first width of the third portion in a second direction perpendicular to the first direction decreases as a distance from the semiconductor chip region increases.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho Sung Cho, Sang Kweon Lee, Sang Young Kim
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10943979
    Abstract: The disclosure relates to a semiconductor device having a SiC semiconductor body. The SiC semiconductor body includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region is electrically contacted at a first surface of the SiC semiconductor body and forms a pn junction with the second semiconductor region. The first semiconductor region and the second semiconductor region are arranged one above the other in a vertical direction perpendicular to the first surface. The first semiconductor region has a first dopant species and a second dopant species.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Rainer Stegner, Hans-Joachim Schulze
  • Patent number: 10910321
    Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
  • Patent number: 10903216
    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoung Kim, Daewon Kim, Dongjin Lee
  • Patent number: 10847602
    Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu
  • Patent number: 10840854
    Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: November 17, 2020
    Assignee: Circuit Seed, LLC
    Inventors: Robert C. Schober, Susan Marya Schober
  • Patent number: 10840189
    Abstract: Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Jye-Yen Cheng
  • Patent number: 10784338
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 10784267
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • Patent number: 10770454
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 10763118
    Abstract: Techniques for tight pitch patterning of fins using a cyclic selective deposition process are provided. In one aspect, a method of patterning fins in a wafer includes: forming at least one mandrel on the wafer; forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel; removing the at least one mandrel; removing either the first dielectric or the second dielectric; and patterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks. A finFET device and method for forming a finFET device are also provided.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Zhenxing Bi, Juntao Li, Dexin Kong
  • Patent number: 10748907
    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 10727107
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Hermann Gruber, Markus Muellauer, Matthias Stecher
  • Patent number: 10644099
    Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert V. Seidel, Thomas G. McKay, Tibor Bolom
  • Patent number: 10629474
    Abstract: Various capacitive isolation structures which can be readily incorporated into existing IC manufacturing procedures. An illustrative method embodiment for forming an isolation capacitance includes: (a) forming a recess on a surface of an integrated circuit substrate, the recess having a bottom surface; (b) coating the bottom surface with an insulating layer; (c) overlaying a bottom electrode on the insulating layer; (d) filling the recess with a bulk insulator having a minimum thickness no less than half a depth of the recess; and (e) depositing a top electrode above the bulk insulator.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 21, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: YongZhong Hu
  • Patent number: 10593659
    Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10566414
    Abstract: A backend-of-the-line (BEOL) semiconductor capacitor made by method, apparatus, or computer program product, through an airgap metallization process, patterning a first electrode by removing a portion of inter-layer dielectric for a desired capacitor area, depositing a dielectric for a capacitor insulator, filling the desired capacitor area to form a second electrode, polishing and capping the second electrode, and interconnecting the first electrode and the second electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher Waskiewicz
  • Patent number: 10553587
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10475727
    Abstract: A semiconductor device includes an electrode plate, a metallic member, and solder connecting the metallic member with the electrode plate. On a surface of the electrode plate, a first groove and a group of second grooves are provided. The first groove has first to fourth linear parts. The group of second grooves is arranged within a range surrounded by the first groove, and has end portions on an outer periphery side that are connected with the first groove. The group of second grooves includes first to fourth sets. Each of the sets includes a plurality of second grooves connected with the first to fourth linear parts. When the metallic member is seen in a lamination direction of the electrode plate and the metallic member, an outer peripheral edge of a region of the metallic member, the region being connected with the solder, goes across the first to fourth sets.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: November 12, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Takahagi, Syou Funano, Takuya Kadoguchi, Yuji Hanaki, Shingo Iwasaki, Takanori Kawashima
  • Patent number: 10453864
    Abstract: A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Dae Suk, Geum Jong Bae, Joo Hee Jeong
  • Patent number: 10439033
    Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
  • Patent number: 10431284
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura, Charles L. Ingalls
  • Patent number: 10424649
    Abstract: A semiconductor device includes a substrate, device isolation film defining an active region of the substrate in which a gate trench extends, a gate insulating film disposed along sides and a bottom of the gate trench, a gate electrode disposed on the gate insulating film in the gate trench and having a first portion, a second portion on the first portion, and a third portion on the second portion, a first barrier film pattern interposed between the first portion of the gate electrode and the gate insulating film, a second barrier film pattern interposed between the second portion of the gate electrode and the gate insulating film, and a third barrier film pattern interposed between the third portion of the gate electrode and the gate insulating film. The work function of the first barrier film pattern is greater than the work function of the second barrier film pattern and less than the work function of the third barrier film pattern.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Seok Moon, Dong Sik Kong, Sung Won Yoo, Hee Sun Joo, Kyo-Suk Chae
  • Patent number: 10388574
    Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juyoun Kim
  • Patent number: 10388664
    Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 20, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Yukai Huang, Chun Ling Chiang, Yung-Tai Hung, Chun Min Cheng, Tuung Luoh, Ling Wuu Yang, Ta-Hung Yang, Kuang-Chao Chen
  • Patent number: 10373866
    Abstract: A capacitor structure and a method for constructing the structure are described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert
  • Patent number: 10347626
    Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yufei Xiong, Yunlong Liu, Hong Yang, Jianxin Liu
  • Patent number: 10340377
    Abstract: Edge termination for MOSFETs. In accordance with an embodiment of the present invention, a metal oxide semiconductor field effect transistor (MOSFET) includes a core region including a plurality of parallel core plates coupled to a source terminal of the MOSFET. The MOSFET also includes a termination region surrounding the core region comprising a plurality of separated floating termination segments configured to force breakdown into the core region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 2, 2019
    Assignee: Vishay-Siliconix
    Inventor: Deva Pattanayak
  • Patent number: 10312321
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Zhen Zhang
  • Patent number: 10304839
    Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10297545
    Abstract: The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric layer, and a plurality of vias. The substrate has a plurality of first regions and a plurality of second regions arranged in a staggered manner along a first direction. The first wires are embedded in the substrate and extended along the first direction. The first wires include a conductive layer and a cap layer located on the conductive layer, and the upper surface of the cap layer has a groove. The etch-stop layers are located on the cap layer and filled in the groove. The dielectric layer is located on the substrate and has a plurality of via openings in the first regions. The via openings expose the substrate and the etch-stop layer. The vias are filled in the via openings and electrically connected to the substrate. The invention further provides a manufacturing method of a memory device.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 21, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Shu-Mei Lee
  • Patent number: 10297613
    Abstract: Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed by using a first etching liquid; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned by using a second etching liquid different from the first etching liquid. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed. An etching speed of each of the insulating film and the insulating layer due to the first etching liquid is smaller than an etching speed of the semiconductor layer by using the first etching liquid.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama
  • Patent number: 10290637
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix Beaudoin, Stephen M. Lucarini, Xinhui Wang, Xinlin Wang
  • Patent number: 10276672
    Abstract: A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 30, 2019
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada