Capacitor In Trench Patents (Class 257/301)
  • Patent number: 11417661
    Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.
    Type: Grant
    Filed: March 1, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
  • Patent number: 11417647
    Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Yicheng Du, Meng Wang, Hui Yu
  • Patent number: 11417574
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: August 16, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tsang-Po Yang, Jui-Hsiu Jao
  • Patent number: 11410908
    Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Reinhard Mahnkopf, Sonja Koller, Andreas Wolter
  • Patent number: 11393801
    Abstract: A decoupling capacitor includes a first insulating layer extending in a horizontal direction, a storage plate arranged on the first insulating layer, a top plate facing the storage plate, a second insulating layer interposed between the storage plate and the top plate and having a plurality of through holes, a capacitor block including a plurality of capacitor structures in the plurality of through holes, a wiring structure covering the top plate, a first conductive pad arranged on the wiring structure and configured to be electrically connected to the storage plate through a first conductive path of the wiring structure, and a second conductive pad spaced apart from the first conductive pad in the horizontal direction in the same plane as the first conductive pad and configured to be electrically connected to the top plate through a second conductive path of the wiring structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghun Shin, Jaejune Jang, Dukseo Park, Sunwoo Park, Howoo Park
  • Patent number: 11355579
    Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: June 7, 2022
    Assignee: Hua Hong Semiconductor (Wuxi) Limited
    Inventor: Junwen Liu
  • Patent number: 11355616
    Abstract: A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Huang Huang, Ming-Jhe Sie, Yih-Ann Lin, An Chyi Wei, Ryan Chia-Jen Chen
  • Patent number: 11302774
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a conductive pattern, a first conductive layer, and a dielectric layer. The conductive pattern extends upwardly from the substrate. The conductive pattern has a hollow structure. The first conductive layer covers the conductive pattern. The dielectric layer at least covers the first conductive layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 12, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Hyunyoung Kim, Dowon Kwak, Kang-Won Seo
  • Patent number: 11302534
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 12, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11296116
    Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Chen Chang, Kuo-Chi Tu, Tzu-Yu Chen, Sheng-Hung Shih
  • Patent number: 11293093
    Abstract: Processing methods comprising exposing a substrate to a first reactive gas comprising an ethylcyclopentadienyl ruthenium complex or a cyclohexadienyl ruthenium complex and a second reactive gas comprising water to form a ruthenium film are described.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 5, 2022
    Assignee: Applied Materials Inc.
    Inventors: Feng Q. Liu, Feng Chen, Jeffrey W. Anthis, David Thompson, Mei Chang
  • Patent number: 11282922
    Abstract: In a first cell region of a semiconductor substrate, a first semiconductor element is formed. In a second cell region of semiconductor substrate, a second semiconductor element is formed. First semiconductor element includes a first electrode and a first p region. Second semiconductor element includes a second electrode and a second p region. First electrode and second electrode are separated from each other. First p region and second p region are separated from each other.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Makoto Kawano
  • Patent number: 11257813
    Abstract: A semiconductor device includes: semiconductor layer having surface and rear surface; insulating film formed on the surface; first and second surface electrode layers formed on the insulating film; rear electrode layer formed on the rear surface; active region set in region of the surface covered with the first surface electrode layer; capacitor region set in region of the surface covered with the second surface electrode layer; first trench formed in the active region; first insulating film formed on inner surface of the first trench; first embedded electrode embedded in the first trench and controlling ON/OFF of current flowing between the first surface electrode layer and the rear electrode layer; second trench formed in the capacitor region; second insulating film formed on inner surface of the second trench; and second embedded electrode embedded in the second trench and electrically connected to the first surface electrode layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Kenta Suganuma
  • Patent number: 11251053
    Abstract: An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics (Grolles 2) SAS
    Inventors: Joel Schmitt, Bilel Saidi, Sylvain Joblot
  • Patent number: 11251077
    Abstract: A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 15, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara Tapily
  • Patent number: 11217591
    Abstract: The present application discloses a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first fin structure and a second fin structure disposed over a semiconductor substrate, and a first word line disposed across the first fin structure and the second fin structure. The semiconductor device structure also includes a first source/drain (S/D) structure disposed over the first fin structure and adjacent to the first word line, and a second S/D structure disposed over the second fin structure and adjacent to the first word line. The first S/D structure and the second S/D structure have an air gap therebetween.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Nanya Technology Corporation
    Inventor: Chin-Te Kuo
  • Patent number: 11205712
    Abstract: A method of manufacturing a low temperature polysilicon thin film includes: forming a buffer layer on a substrate; forming a first silicon layer on the buffer layer; forming a second silicon layer on the first silicon layer, and forming a substrate impurity barrier interface between the first silicon layer and the second silicon layer, wherein the second silicon layer is thicker than the first silicon layer; and annealing the first silicon layer and the second silicon layer to form a polysilicon layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 21, 2021
    Assignee: HKC CORPORATION LIMITED
    Inventor: Huailiang He
  • Patent number: 11195946
    Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Romain Esteve, Roland Rupp
  • Patent number: 11183503
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
  • Patent number: 11145662
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • Patent number: 11139304
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 5, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 11121241
    Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, a first region formed in a surface layer of the first main surface, a drift layer disposed adjacent to the first region, a charge accumulation region having a higher concentration than the drift region, and a trench gate including a trench penetrating the first region and the charge accumulation region, and a gate electrode formed in the trench. The trench gate includes a main trench having a gate electrode to which a gate voltage is applied, and a dummy trench having a gate electrode to which a voltage different from the main trench is applied. The main trench and the dummy trench sandwiches the charge accumulation region, and a contact area S1 between the dummy trench and the charge accumulation region is larger than a contact area S2 between the main trench and the charge accumulation region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 14, 2021
    Assignee: DENSO CORPORATION
    Inventor: Hiromitsu Tanabe
  • Patent number: 11101271
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11094655
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Chang-Jung Hsueh, Chin-Wei Kang, Hui-Min Huang, Wei-Hung Lin, Cheng-Jen Lin, Ming-Da Cheng, Chien-Chun Wang
  • Patent number: 11094360
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 17, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi
  • Patent number: 11075265
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Zhen Zhang
  • Patent number: 11069688
    Abstract: Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing a bulk substrate with a first doped layer thereon, depositing a first hard mask over the substrate, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, where the grown second polysilicon material and epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 11062989
    Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 11053601
    Abstract: A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 6, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Adam M. Rowen, Robert K. Grubbs, Jonathan Joseph Coleman
  • Patent number: 11049932
    Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Steven M. Shank, Mark David Levy, Bruce W. Porth
  • Patent number: 11049862
    Abstract: A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: June 29, 2021
    Assignee: HeFeChip Corporation Limited
    Inventors: John Zhang, Yanzun Li, GuoLiang Zhu, Tongqing Chen, Huang Liu
  • Patent number: 11043496
    Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen W. Russell, Stephen H. Tang
  • Patent number: 11037942
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 11031460
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Patent number: 10991698
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 27, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10985173
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 10978368
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an insulating film, and a photo sensitive film. The substrate includes a semiconductor chip region and a scribe line region disposed along an edge of the semiconductor chip region. The insulating film includes a first portion disposed on the semiconductor chip region, a second portion disposed on the scribe line region and connected with the first portion, and a third portion disposed on the scribe line region and protruded in a first direction from the second portion. The photo sensitive film is disposed on the insulating film and has a sidewall exposed on the second portion of the insulating film. A first width of the third portion in a second direction perpendicular to the first direction decreases as a distance from the semiconductor chip region increases.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho Sung Cho, Sang Kweon Lee, Sang Young Kim
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10943979
    Abstract: The disclosure relates to a semiconductor device having a SiC semiconductor body. The SiC semiconductor body includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region is electrically contacted at a first surface of the SiC semiconductor body and forms a pn junction with the second semiconductor region. The first semiconductor region and the second semiconductor region are arranged one above the other in a vertical direction perpendicular to the first surface. The first semiconductor region has a first dopant species and a second dopant species.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Rainer Stegner, Hans-Joachim Schulze
  • Patent number: 10910321
    Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
  • Patent number: 10903216
    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoung Kim, Daewon Kim, Dongjin Lee
  • Patent number: 10847602
    Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu
  • Patent number: 10840854
    Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: November 17, 2020
    Assignee: Circuit Seed, LLC
    Inventors: Robert C. Schober, Susan Marya Schober
  • Patent number: 10840189
    Abstract: Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Jye-Yen Cheng
  • Patent number: 10784338
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 10784267
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao
  • Patent number: 10770454
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 10763118
    Abstract: Techniques for tight pitch patterning of fins using a cyclic selective deposition process are provided. In one aspect, a method of patterning fins in a wafer includes: forming at least one mandrel on the wafer; forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel; removing the at least one mandrel; removing either the first dielectric or the second dielectric; and patterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks. A finFET device and method for forming a finFET device are also provided.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Zhenxing Bi, Juntao Li, Dexin Kong
  • Patent number: 10748907
    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 10727107
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Hermann Gruber, Markus Muellauer, Matthias Stecher