Capacitor In Trench Patents (Class 257/301)
  • Patent number: 10312321
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Zhen Zhang
  • Patent number: 10304839
    Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10297613
    Abstract: Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed by using a first etching liquid; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned by using a second etching liquid different from the first etching liquid. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed. An etching speed of each of the insulating film and the insulating layer due to the first etching liquid is smaller than an etching speed of the semiconductor layer by using the first etching liquid.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama
  • Patent number: 10297545
    Abstract: The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric layer, and a plurality of vias. The substrate has a plurality of first regions and a plurality of second regions arranged in a staggered manner along a first direction. The first wires are embedded in the substrate and extended along the first direction. The first wires include a conductive layer and a cap layer located on the conductive layer, and the upper surface of the cap layer has a groove. The etch-stop layers are located on the cap layer and filled in the groove. The dielectric layer is located on the substrate and has a plurality of via openings in the first regions. The via openings expose the substrate and the etch-stop layer. The vias are filled in the via openings and electrically connected to the substrate. The invention further provides a manufacturing method of a memory device.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 21, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Shu-Mei Lee
  • Patent number: 10290637
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix Beaudoin, Stephen M. Lucarini, Xinhui Wang, Xinlin Wang
  • Patent number: 10276672
    Abstract: A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 30, 2019
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada
  • Patent number: 10269804
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10249528
    Abstract: An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: April 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Hung-Chan Lin, Yu-Chun Chen
  • Patent number: 10242726
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Patent number: 10217825
    Abstract: A semiconductor device containing a metal-insulator-semiconductor (MIS) contact and method of forming are described. The method includes providing a semiconductor substrate containing a contact region, depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing TiO2 and at least one additional metal oxide. The method further includes depositing a metal-containing electrode layer abutting the insulator film to form a MIS structure, and heat-treating the MIS structure to scavenge oxygen from the TiO2 to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO2. According to one embodiment the at least one additional metal oxide is selected from HfO2, ZrO2, Al2O3, and combinations thereof, and the metal-containing electrode layer is selected from the group consisting of Ti metal, Al metal, Hf metal, Zr metal, Ta metal, Nb metal, and a combination thereof.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Toyko Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 10211348
    Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsushi Amo
  • Patent number: 10199166
    Abstract: A capacitor includes: a substrate including a plurality of trenches and a capacitance formation portion, and a margin portion disposed around the capacitance formation portion; dielectric layers disposed on one surface of the substrate and filling the trenches; a plurality of first electrode layers each disposed on one surface of the dielectric layer and each including a first lead portion led out from the capacitance formation portion to the margin portion; and a plurality of second electrode layers each disposed on one surface of the dielectric layer to face the first electrode layer with each of the dielectric layers interposed therebetween, and each including a second lead portion led out from the capacitance formation portion to the margin portion, wherein the first and second lead portions of the plurality of first and second electrode layers are stacked in a stepped shape inclined in a direction from the margin portion to the capacitance formation portion.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: No Il Park, Byeong Cheol Moon, Il Ro Lee, Hyun Ho Shin, Seung Mo Lim, In Young Kang
  • Patent number: 10192887
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Patent number: 10192791
    Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman, Charlotte Adams, Jinping Liu, Keith Tabakman
  • Patent number: 10186524
    Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
  • Patent number: 10163896
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10157913
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed radially inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed radially inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10157784
    Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 18, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Manabu Oie, Kaoru Maekawa, Cory Wajda, Gerrit J. Leusink, Yuuki Kikuchi, Hiroaki Kawasaki, Hiroyuki Nagai
  • Patent number: 10153027
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Patent number: 10147877
    Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: December 4, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
  • Patent number: 10128292
    Abstract: A method can be used to manufacture a charge storage cell with a first trench and a second trench in a substrate material. The first trench is filled with a doped material. The second trench is filled with a second trench material. The method includes causing the dopant to diffuse from the first trench to thereby provide a doped region adjacent to the first trench. The material from the first and second trenches is removed and at least one of the trenches is filled with a capacitive deep trench isolation material to provide capacitive deep trench isolation.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Laurence Stark
  • Patent number: 10115792
    Abstract: A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: October 30, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Shinya Yamazaki, Ryotaro Yagi
  • Patent number: 10103143
    Abstract: An electronic device is provided. The electronic device comprises a fin transistor formed over a substrate which is structured to include a device isolation region and an active region, the fin transistor including: a layer formed over the substrate and having a trench crossing the device isolation region and the active region; a gate filled in the trench; a first fin formed over and overlapping the active region and protruding over the device isolation region; and second fins formed on both sidewalls of the first fin in a direction of the trench.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: October 16, 2018
    Assignee: SK hynix Inc.
    Inventor: Hubert Alexandre
  • Patent number: 10084050
    Abstract: A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10084078
    Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: September 25, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Hiroshi Kawaguchi
  • Patent number: 10083967
    Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Eduard A. Cartier, Herbert L. Ho, Donghun Kang
  • Patent number: 10079248
    Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven M. Shank, Mark D. Jaffe, John J. Pekarik
  • Patent number: 10079277
    Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tri-Rung Yew, Hung-Chan Lin, Li-Wei Feng, Chien-Ting Ho, Chia-Lung Chang
  • Patent number: 10049890
    Abstract: The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10049941
    Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
  • Patent number: 10043878
    Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporations
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10037998
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
  • Patent number: 10032778
    Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye Ram Kim, Won Chul Lee
  • Patent number: 10014227
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 3, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 9991155
    Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Steven M. Shank, Michel Abou-Khalil
  • Patent number: 9960285
    Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chung-Yen Chou, Po-ken Lin, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9954166
    Abstract: A memory cell with a composite top electrode is provided. A bottom electrode is disposed over a substrate. A switching dielectric having a variable resistance is disposed over the bottom electrode. A capping layer is disposed over the switching dielectric. A composite top electrode is disposed over and abutting the capping layer. The composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer. By having the disclosed composite top electrode, an interfacial oxidized layer is eliminated or less formed when exposing the composite top electrode for top electrode via formation, thereby improving RC properties between the top electrode and the top electrode via. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Yao-Wen Chang
  • Patent number: 9947766
    Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9941276
    Abstract: A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 9935110
    Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9917147
    Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Min Lee, Hyongsoo Kim, Jongryul Jun
  • Patent number: 9911751
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Woo June Kwon, Jong Hoon Kim, Chan Sun Hyun
  • Patent number: 9911597
    Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
  • Patent number: 9893157
    Abstract: Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Max G. Levy, BethAnn Lawrence
  • Patent number: 9865457
    Abstract: There is provided a method of forming a nitride film, including: repeating a cycle including an adsorption process of adsorbing a film forming precursor gas onto a substrate having a surface in which a fine recess is formed, the film forming precursor gas containing an element and chlorine constituting a nitride film to be formed; and a nitriding process of nitriding the adsorbed film forming precursor gas with nitriding active species, to form the nitride film in the fine recess. The nitriding process includes: generating NH* active species and N* active species as a nitriding active species; and controlling concentrations of the NH* active species and the N* active species to vary an area where the film forming precursor gas is adsorbed in the fine recess.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 9, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Akira Shimizu
  • Patent number: 9865400
    Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 ?m or more at ½ of a depth of the at least one groove.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ken Ito, Noriyuki Inoue, Koichi Kanryo
  • Patent number: 9865539
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hua Chen, Tai-I Yang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin, Tien-I Bao
  • Patent number: 9853055
    Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
  • Patent number: 9831304
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes determining a guard ring width within an integrated circuit design layout, where a guard ring with the guard ring width surrounds an active area in the integrated circuit design layout. A deep trench location is calculated for replacing the guard ring, where the deep trench location depends on the guard ring width. The guard ring in the integrated circuit design layout is replaced with a deep trench having the deep trench location. The deep trench is formed within a substrate at the deep trench location, where the deep trench surrounds the active area.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Mun Tat Yap, Shiang Yang Ong, Namchil Mun, Tat Wei Chua, Raj Verma Purakh, Jeoung Mo Koo
  • Patent number: 9825037
    Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Takanori Matsuzaki, Shuhei Nagatsuka