Abstract: A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t

Abstract: A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: The semiconductor device includes an active region, a recess channel region, a storage node junction region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate, wherein a lower part of sidewalls of the active region is recessed. The recess channel is formed in the semiconductor substrate under the active region, wherein the recess channel has a vertical channel region and a horizontal channel region. The storage node junction region is formed over the device isolation structure and the semiconductor substrate. The gate insulating film is formed over the active region including the recess channel region. The gate electrode is formed over the gate insulating film to fill up the recess channel region.

Abstract: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

Abstract: A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison.

Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.

Abstract: A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

Abstract: Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench.

Abstract: A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.

Abstract: Memory cells and semiconductor memory devices using the same. A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive layer is disposed on the substrate and comprises a bit line and a complementary bit line electrically connected to second terminals of the first and second pass-gate transistors respectively. A second conductive layer is disposed on the first conductive layer and comprises two first power lines covering the bit line and the complementary bit line respectively, wherein the first power lines, the bit line and the complementary bit line are parallel.

Abstract: A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low elevation regions of a hemispherical grain polysilicon layer may remain on the upper surface of the storage electrode. The storage electrode or portions thereof may be lined or coated with dielectric material. The dielectric material may space a cell electrode of the high surface area capacitor structure apart from the storage electrode. One or both of the storage electrode and the cell electrode may be formed from polysilicon. Intermediate structures, which include mask material over contiguous low elevation regions of a layer of hemispherical grain polysilicon, which may have a maze-like appearance, and apertures located laterally between the low elevation regions of the layer of hemispherical grain polysilicon, are also disclosed.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

Abstract: A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

Abstract: A semiconductor device includes a semiconductor substrate, a storage pad and a bit line pad on the semiconductor substrate, a first interlayer insulating layer covering the bit line pad and including a bit line contact hole having a width greater than a width of the bit line pad, a barrier insulating layer on sidewalls of the first interlayer insulating layer and upper portions of sidewalls of the bit line pad that are exposed by the bit line contact hole, a bit line plug in the bit line contact hole and on the barrier insulating layer; and a storage plug penetrating the first interlayer insulating layer and contacting the storage pad.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.

Abstract: A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

Abstract: A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the source separated from the drain by a channel; and (ii) a diffused deep n-well (DNW) formed by a long, high temperature drive-in step. The DNW forms a drain-extension region for the NMOS transistor surrounding the drain and extending a predetermined distance into the channel. The drain extension region has a doping concentration lower than the source and drain to deplete during reverse biasing of the transistor, thereby raising a breakdown voltage of the transistor. Preferably, the circuit further includes a DE p-channel MOS (PMOS) transistor in which the DNW forms a well tub for the PMOS transistor, and a p-well in DNW forms a DE region therefore. Other embodiments are also disclosed.

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract: A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

Abstract: A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.

Abstract: A semiconductor memory device includes a first word-line, a first non-inverted bit-line, a first inverted bit-line, a first global interconnection layer, a first memory capacitor having a first storage electrode, a first counter electrode, and a first oxide dielectric film, a second memory capacitor having a second storage electrode, a second counter electrode, and a second oxide dielectric film, a first local interconnection layer including a first contact portion, a second contact portion, and a first non-contact portion, a first hydrogen barrier layer covering at least the first contact portion and the second contact portion of the first local interconnection layer, a first switching transistor having a first gate electrode, a second switching transistor having a second gate electrode, and a third switching transistor having a third gate electrode.

Abstract: The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

Abstract: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract: The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same may be provided. The semiconductor memory device may include a substrate, at least a pair of fins protruding from the semiconductor substrate and facing each other with a gap between fins of the pair of fins, an insulating layer formed between the pair of the fins, a storage node formed on the pair of fins and/or a surface of a portion of the insulating layer, and/or a gate electrode formed on the storage node.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to provide a method which smoothing surface can be achieved without a polishing treatment by CMP method or a smoothing process by depositing a SOG film, a substrate material is not chosen, and the smoothing is simple and easy. In the semiconductor device in which a plurality of different layers are formed, smoothing surface can be achieved without the polishing treatment by the CMP method or the smoothing process by depositing the SOG film to a dielectric film formed on a dielectric film and a wring (electrode) or a semiconductor layer in a manner that an aperture portion is formed in the dielectric film, the wring (electrode) or the semiconductor layer is formed in the aperture portion.

Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0-3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.

Abstract: Methods for fabricating contacts to semiconductor structures are provided. A method comprises forming two members extending from a semiconductor substrate and separated by a portion of the substrate. First and second semiconductor devices are formed in and on the substrate and each comprise a common impurity doped region that is disposed within the portion of the substrate. A dielectric layer is deposited overlying the members, the semiconductor devices, and the common impurity doped region to a thickness such that a depression overlying the impurity doped region is formed. A fill material is deposited to substantially fill the depression and a portion of the dielectric layer is etched. A masking layer is deposited and a portion of the masking layer is removed to expose the fill material. A via is formed by etching the fill material and dielectric layer and a conductive material is deposited therein.

Abstract: A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a gate electrode disposed through a gate insulator on a surface of the semiconductor substrate of the channel region, a capacitor connected to the channel region, a first wiring line electrically connected to the gate electrode, and a second wiring line electrically connected to the drain.