Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: A semiconductor device having a memory cell portion and a peripheral circuit portion is provided which achieves suppression of reduction of punch-through margin of transistors in the peripheral circuit portion and offers ensured short margin and enhanced current driving capability. After a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to improve burying characteristics after formation of an interlayer insulating film, and also after a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to enhance refresh characteristics after formation of contact plugs in the memory cell portion, a silicon oxide film and insulating film formed on a semiconductor substrate in the peripheral circuit portion are removed by anisotropic dry-etching, leaving the insulating film as sidewall insulating films on sides of sidewall nitride films.

Abstract: A memory device with multi-bit memory cells and method of making the same uses self-assembly to provide polymer memory cells on the contacts to a transistor array. Employing self-assembly produces polymer memory cells at the precise locations of the contacts of the transistor array. The polymer memory cells change resistance values in response to electric current above a specified threshold value. The memory cells retain the resistivity values over time.

Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: On a semiconductor substrate, a transistor and a capacitor electrically connected to the transistor are formed, the capacitor having two electrodes made of metal and a capacitor dielectric layer between the two electrodes made of oxide dielectric material. A temporary protective film is formed over the capacitor, the temporary protective film covering the capacitor. The semiconductor substrate with the temporary protective film is subjected to a heat treatment in a reducing atmosphere. The temporary protective film is removed. The semiconductor substrate with the temporary protective film removed is subjected to a heat treatment in an inert gas atmosphere or in a vacuum state. A protective film is formed over the capacitor, the protective film covering the capacitor. With these processes, leak current of the capacitor can be reduced.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: A semiconductor device includes a MOS transistor, an interlayer insulating film, a contact plug, a capacitor lower electrode, a ferroelectric film and two capacitor upper electrodes. The MOS transistor is formed on a semiconductor substrate. The interlayer insulating film covers the MOS transistor. The contact plug is connected to an impurity diffusion layer of the MOS transistor. The capacitor lower electrode is formed on the contact plug. The two capacitor upper electrodes are formed on the capacitor lower electrode with the ferroelectric film interposed therebetween. A contact area between the contact plug and the capacitor lower electrode is greater than a contact area between each of the two capacitor upper electrodes and the ferroelectric film. At least a part of a gate electrode of the MOS transistor is located just below a region of the contact plug, which region is in contact with the capacitor lower electrode.

Abstract: A method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer. The spacer is formed along a profile containing the bit line and the hard mask. A first inter-layer insulation layer is deposited on an entire surface of the bit line structure. A storage node contact plug is formed on the substrate by passing through the inter-layer insulation layer and having a partially etched portion. A second inter-layer insulation layer is formed on a partial portion of the first inter-layer insulation layer and the storage node contact plug.

Abstract: A semiconductor device having self-aligned contact pads and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate and an isolation layer formed on the semiconductor substrate. The semiconductor substrate defines a plurality of active regions that each have a major axis and a minor axis. A plurality of gates are formed to cross the plurality of active regions and extend in the direction of the minor axis. First and second source/drain regions are formed in active regions at either side of each of the gates. First and second self-aligned contact pads (SACs) are formed to contact the top surfaces of the first and second source/drain regions, respectively.

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.

Abstract: A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Abstract: There a provided a first insulating layer formed over a semiconductor substrate, a cell plate line formed on the first insulating layer and having a slit that divides a region except a contact area into both sides, a capacitor dielectric layer formed on the cell plate on both sides of the slit and having a clearance over the slit, and a plurality of capacitor upper electrodes formed on the capacitor dielectric layer in one column on both sides of the slit.

Abstract: A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A P+ polysilicon gate electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells within the nitride layer are erased simultaneously.

Abstract: A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.

Abstract: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

Abstract: A semiconductor device includes a diffusion region in a semiconductor substrate, a gate insulation film on the semiconductor substrate, a gate electrode on the gate insulation film, an interlayer insulation film on the semiconductor substrate covering the gate electrode, and a capacitor on the interlayer insulation film. The capacitor includes a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion region, the gate electrode, and the lower electrode are connected to one another by a common contact in the interlayer insulation film.

Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract: An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

Abstract: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Abstract: The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

Abstract: Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

Abstract: A ferromagnetic thin-film based digital memory having a plurality of bit structures electrically interconnected with information storage and retrieval circuitry that avoids information loss in one bit structure because of operating the others through this circuitry. Each of these bit structures formed of a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof with a pair of memory films of an anisotropic ferromagnetic material each on a corresponding one of said relative orientation maintenance intermediate layer major surfaces. The relative orientation maintenance intermediate layer is of a material and a selected thickness so as to maintain magnetizations of said memory films oriented in substantially opposite directions.

Abstract: The present invention provides a capacitor formed in a dynamic random access memory (DRAM) semiconductor device, the capacitor comprising: a polysilicon layer to making contact with a diffusion region of an access device; a TiN comprising layer overlying the polysilicon layer; the TiN comprising layer and the polysilicon layer are patterned to serve as a bottom capacitor plate; a layer of dielectric material overlying the patterned TiN comprising layer; and a top capacitor plate. A method for forming the capacitor comprises the steps of: providing a opening to a diffusion region in an underlying substrate of a wordline activated transistor; forming a TiN comprising layer to make contact with the diffusion via the opening; patterning the TiN comprising layer into an individual bottom capacitor plate; forming a layer of dielectric material; and forming a top capacitor plate.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: A method for fabricating a semiconductor device, and a semiconductor device, having storage node contact plugs whereby by a first interlayer dielectric layer (ILD) film having a greater etch rate is formed on a surface of a structure, and then a second ILD film having a smaller etch rate is formed on the first ILD film. After storage node contact holes having narrow width are formed by dry etching the ILD films, the width is increased by wet etching the ILD films. Since the first ILD film has a greater etch rate and is etched faster than the second ILD film, the lower width of each of the storage node contact holes is increased relatively more than the upper width. Insulating layer spacers are then formed on the internal walls of the storage node contact holes, and storage node contact plugs are formed by burying a conductive material therein.

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Abstract: An impurity diffusion layer serving as the source or the drain of a transistor is formed in a semiconductor substrate, and a protection insulating film is formed so as to cover the transistor. A capacitor lower electrode, a capacitor dielectric film of an oxide dielectric film and a capacitor upper electrode are successively formed on the protection insulating film. A plug for electrically connecting the impurity diffusion layer of the transistor to the capacitor lower electrode is buried in the protection insulating film. An oxygen barrier layer is formed between the plug and the capacitor lower electrode. The oxygen barrier layer is made from a composite nitride that is a mixture or an alloy of a first nitride having a conducting property and a second nitride having an insulating property.

Abstract: A method and structure is disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes a insulated sleeve structure. A lower bulk insulator layer, a capacitor dielectric layer, a cell plate conductor layer, and an upper bulk insulator layer are formed upon a semiconductor substrate. An etch removes the cell plate conductor layer, the capacitor dielectric layer, and the lower bulk insulator layer so as to form an opening terminating within the lower bulk insulator layer. A sleeve insulator layer is deposited upon the upper bulk insulator layer and within the opening. Another etch removes the sleeve insulator layer from the bottom surface within the lower bulk insulator layer. A still further etch creates a contact hole that expose a contact. The contact can be upon a transistor gate, a capacitor storage node, or an active region on the semiconductor substrate.

Abstract: The present invention provides a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug comprises a diffusion barrier layer and a seed layer for forming a lower electrode of a capacitor. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, whereby the leakage current may be reduced, and the capacitance of the capacitor may be increased.

Abstract: A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Abstract: Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The ferroelectric capacitor residing over the first and second circuit elements, and first and second contacts, has a conductive plate that may be used as a local interconnect layer. The conductive plate extends between and electrically couples first and second circuit elements directly through first and second contacts of the ferroelectric memory device. Methods are also provided for forming the local interconnect layer within the conductive plate of the ferroelectric capacitor.

Abstract: A capacitor includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode. The lower electrode includes a conductive barrier layer that prevents diffusion of oxygen, and an insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.

Abstract: A stacked DRAM cell capacitor having HSG silicon only on a top portion of a storage node, not on a bottom portion thereof. The storage node has a double layer structure including a bottom layer and a top layer. The bottom layer is made of a conductive material that suppresses the growth of HSG seeds. Accordingly, electrical bridges between adjacent storage nodes, particularly at a bottom portion, can be prevented.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: There is provided such a structure that a first insulating layer, a conductive pattern, a second insulating layer, a capacitor Q, a third insulating layer, and a lower electrode leading wiring are formed sequentially on a semiconductor substrate, and a lower electrode of the capacitor is connected to an upper surface of the conductive pattern, and the lower electrode leading wiring is also connected electrically to the conductive pattern from its upper side.

Abstract: A method for use with the formation of a capacitor includes providing a capacitor structure by forming a first electrode on a portion of a substrate assembly, forming a high dielectric material over at least a portion of the first electrode, and forming a second electrode over the high dielectric material. An additional layer may be formed over at least a portion of the second electrode. The portion of the substrate assembly on which the first electrode is formed and/or the layer formed over the second electrode are formed of an excess oxygen containing material.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

Abstract: A semiconductor device which includes a capacitor wherein the capacitance of the capacitor can be prevented from being lowered even in the case that the capacitor is miniaturized. A core insulating film having the core of the capacitor formed above a semiconductor substrate, a capacitor lower electrode formed so as to cover side surfaces of this core insulating film, a capacitor dielectric film formed so as to cover the surface of this capacitor lower electrode and the upper surface of the core insulating film and a capacitor upper electrode formed so as to cover the surface of this core insulating film are provided so that the bottom surface of the core insulating film is positioned lower than the bottom surface of the capacitor lower electrode.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: The invention is to provide a novel non-volatile memory capable of recording multi-bit data. The invention is a non-volatile memory which has: first and second source-drain regions SD1, SD2 at the surface of a semiconductor substrate; and a non-conductive trapping gate TG, and a conductive control gate CG, formed on a channel region there between via an insulating film. Further, the non-volatile memory has a first or second state in which, by applying a voltage between the first and second source-drain regions SD1, SD2, hot electrons produced in the vicinity of the first or second source-drain region are locally captured in a first or second trapping gate region TSD1, TSD2 in the vicinity of them; and, a third state in which, by applying a voltage between the control gate and the channel region, electrons (or charge) are (is) injected into the entire trapping gate.

Abstract: A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dishe

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells.

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 &mgr;m or more.

Abstract: A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.