Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.

Abstract: A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer.

Abstract: A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Abstract: One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.

Abstract: In a semiconductor memory device, such as a flash memory device, a conductor layer of metal or metal compound having high refractoriness, such as titanium nitride, is formed on a conductor or wiring formed by a buried diffusion layer to reduce resistance thereof. In the present invention, such conductor layer is formed by using small number of process steps and without using photolithography process. For example, after forming the buried diffusion layer for source and drain regions by ion implantation using each floating gate and dummy gate as a mask, titanium nitride is deposited throughout a substrate. Thereafter, by using oxide film growth and etching back process, an oxide film layer remaining on the titanium nitride layer between the floating gate and the dummy gate is fabricated. Then, the titanium nitride layer on the floating gate and on the dummy gate is removed by using this remained oxide film layer as a mask, without using any photolithography process.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

Abstract: A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess.

Abstract: The invention proposes a simple method to lower the threshold voltage of UV erased EPROM and OTP memories. During the erasure, a voltage is applied to the control gate (10) or wordline (2) which is on-chip generated as a photovoltage by means of photodiode (12) irradiated by radiation (15) during erasure. Because the wordlines are coupled to further zones forming photosensitive pn-junctions in the semiconductor body, measures are taken to prevent that, due to charge transport across said junctions, the generated photovoltage is decreased too strongly.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

Abstract: A semiconductor memory device in which a stored information can be simply erased only by an electric signal so as to be rewritten is provided. The semiconductor memory device includes (a) a semiconductor chip having an array of memory cells, stored information in the memory cells being erasable by light irradiation; (b) a light emitting element irradiating a light into the memory cells portion of the semiconductor chip; and (c) a package in which the semiconductor chip and the light emitting element are encapsulated with a resin in one body.

Abstract: A semiconductor device includes first and second elements, a light-shielding member, and a comparator. The first and second elements are formed on the same substrate, change in electrical characteristics upon irradiation of ultraviolet rays, and hold the changed states. The first element has the same arrangement as that of the second element. The light-shielding member is formed on the first element to shield ultraviolet rays. The comparator compares the electrical characteristics of the first and second elements and outputs an abnormality detection signal on the basis of the comparison results.

Abstract: A nonvolatile semiconductor memory device has a plurality of p well regions in a memory cell array region. P well region is independently provided for each erase block. Each p well region is connected to a common well/source line driver, respectively. Well/source line driver is connected to a well/source power supply and a well/block decoder. Therefore, a nonvolatile semiconductor memory device which can inhibit a well disturbance in erase operation can be provided.

Abstract: An oxide layer is formed with covering the surface of floating gates and the surface of a substrate. Control gates are formed on the oxide layer only at the portion aligning to the upper surface and at least a part of the side surface of the floating gate. By this, up to the portion in parallel to the substrate from the side surface portion of the floating gate, the control gate is not extended. Even when an interval between adjacent memory cells is reduced, opening dimension of the contact hole formed between the memory cells can be made greater. Contact resistance can be reduced. Also, the size of the memory cell can be made smaller to permit increasing of package density.

Abstract: A semiconductor memory device in which a stored information can be simply erased only by an electric signal so as to be rewritten is provided. The semiconductor memory device includes: (a) a semiconductor chip having an array of memory cells, stored information in the memory cells being erasable by light irradiation; (b) a light emitting element irradiating a light into the memory cells portion of the semiconductor chip; and (c) a package in which the semiconductor chip and the light emitting element are encapsulated with a resin in one body.

Abstract: The failure rate of semiconductor devices containing UPROM transistors is improved by erasing the UPROM transistors using X-rays. The semiconductor devices are subsequently exposed to UV radiation to erase other transistors charged during X-ray exposure.

Abstract: According to the present invention, a nonvolatile semiconductor storage device for applying to each word line either one of a selected voltage and a non-selected voltage, corresponding to a selection state and a non-selection state, respectively, is provided. The selection state or the non-selection state is selected in accordance with an address signal in each operational mode.

Abstract: A semiconductor device comprises a lower conductive layer formed on a semiconductor substrate, a first insulation film layer formed at least on side faces of the lower conductive layer, a second insulation film layer formed around the lower conductive layer on which the first insulation film layer has been formed, a contact hole formed on the second insulation film layer in the vicinity of a side face of the lower conductive layer, and an upper conductive layer formed in the contact hole and over the second insulation film. The first insulation film layer is of a three-film structure comprising a first oxide film, a nitride film and a second oxide film.

Abstract: A semiconductor device in which patterning is effected using a silicon oxynitride (SiON) based thin film as an anti-reflection film and in which electrical properties are prohibited from being deteriorated by hydrogen contained in the SiON based thin film. The semiconductor device has a substrate, a gate insulating film formed on the surface of the substrate, a gate electrode formed on the gate insulating film, and a first antireflection film having a pattern in common with the gate electrode. The semiconductor device also has a hydrogen permeation prohibiting film formed between the gate insulating film and the first antireflection film. The first antireflection film contains hydrogen and is formed on the gate electrode.

Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.

Abstract: A non-volatile semiconductor device comprises a memory cell having a P-type silicon substrate, an N-type diffusion region formed in the substrate and serving as a word line, N-type diffusion region one serving as a source and the other as a drain of the cell transistor, a floating gate extending from a region above the diffusion region over a region above between diffusion regions, and a bit line connected to the diffusion regions. Such a memory cell is characterized in that a passivation film is formed on an interlayer insulation film insulating the floating gate and the bit lines from each other, and that a contaminant shut-off layer is provided between the passivation film and the floating gate. With this structure, the route carrying contaminants into the cell can be shut off even during manufacture thereof, achieving a high reliability of the product.

Abstract: A CCD solid state imaging device has an overflow mechanism to discharge excess electric charges at the sensor section. An overflow level can be stabilized without adjustment. The CCD solid state imaging device includes an overflow barrier region for determining an amount of electric charges handled by a sensor section, and an overflow drain region for discharging excess electric charges at the sensor section adjacent to the sensor section. An intermediate region having the same potential as that of the sensor portion is provided between the overflow barrier region and the overflow drain region. Also, a CCD solid state imaging device includes linear sensors provided in a plurality of lines and vertical transfer registers provided at end of the linear sensors in the charge transfer direction of the horizontal transfer registers. When signal charges are overflowed in a part of the horizontal transfer register, signals of all pixels can be avoided from being destroyed.

Abstract: An integrated circuit unerasable memory cell which includes at least one memory cell consisting of a floating gate transistor with drain, source, and gate terminals, and a metallic shield embedded in the semiconductor substrate and covering the cell. Also provided are a diffused region defining a closed loop path on the substrate surface all around the transistor, and having said shield connected peripherally thereto in an unbroken fashion, and first and second wells extending in the substrate from the transistor to outside the diffused region, the first of said wells being connected directly to the gate terminal of the transistor. A contact inside the shield connects the shield's top surface to the cell's source. A protection diode (inside the shield) prevents charging of the floating gate during manufacture.

Abstract: An integrated circuit (106) having an optically erasable portion (114) is joined to a substrate (102) such that the optically erasable portion faces the substrate. The substrate (102) includes an aperture (104) that exposes the optically erasable portion (114) of the integrated circuit providing erasing capability to the integrated circuit (106). A plug (110) impermeable to light may be inserted into the aperture (104) to provide a sealed window to the optically erasable portion (114) of the integrated circuit (106).

Abstract: A memory cell is formed in the main surface area of a semiconductor substrate. An inter-level insulation film is formed on the substrate to cover the memory cell. An opening is formed in the inter-level insulation film to reach the memory cell. An internal wiring layer is electrically connected to the memory cell via the opening. A protection film is formed on the inter-level insulation film to cover the internal wiring layer. The protection film is formed of a material containing at least silicon and oxygen and the refractive index thereof is set within a range of 1.48 to 1.65.

Abstract: An unerasable memory cell (10) is formed in the face of a layer (22) of semiconductor of a first conductivity type and includes an erasable read-only memory cell (12) having a first source/drain region (16) and a second source/drain region (18) of a second conductivity type opposite the first conductivity type. First source/drain region (16) is spaced from second source/drain region (18) by a channel area (24). A floating gate conductor (20) is disposed insulatively adjacent channel area (24) and a control gate conductor (22) disposed insulatively adjacent floating gate conductor (20). A heavily doped moat (32) of the second conductivity type laterally surrounds memory cell (12). A load device (14/66) couples moat (32) with first source/drain region (16) of a memory cell (12).

Abstract: A floating-gate MOS transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32.times.32 synaptic cell array using standard VLSI CMOS technology.

Abstract: A non-volatile memory includes a sheet-shaped source line consisting of a conductive layer. The source line includes an opening at an area including a bit contact area above a drain diffusion layer. The bit contact is formed through self-alignment to the opening of the source line and a control gate electrode. In such a structure, a pitch of the bit contact in the direction parallel to the control gate electrode can be set to be a value twice of the minimum size in design.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.