High Temperature (i.e., >30o Kelvin) Patents (Class 257/33)
  • Patent number: 11552238
    Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: January 10, 2023
    Assignee: New York University
    Inventors: Javad Shabani, Kasra Sardashti
  • Patent number: 11522116
    Abstract: A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana
  • Patent number: 11321626
    Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 3, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Leo Bourdet, Louis Hutin, Yann-Michel Niquet, Maud Vinet
  • Patent number: 11271533
    Abstract: A wireless Josephson-junction-based amplifier is described that provides improved tunability and increased control over both a quality factor Q and participation ratio p of the amplifier. The device may be fabricated on a chip and mounted in a waveguide. No wire bonding between the amplifier and coaxial cables or a printed circuit board is needed. At least one antenna on the chip may be used to couple energy between the waveguide and wireless JBA. The amplifier is capable of gains greater than 25 dB.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 8, 2022
    Assignee: Yale University
    Inventors: Anirudh Narla, Katrina Sliwa, Michael Hatridge, Shyam Shankar, Luigi Frunzio, Robert J. Schoelkopf, III, Michel Devoret
  • Patent number: 11069849
    Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt
  • Patent number: 10879906
    Abstract: A quantum charge parametron (QCP) includes a load capacitor; two quantum phase-slip junctions (QPSJs) coupled to each other through the load capacitor so as to define two charge islands, each charge island being located between the load capacitor and a respective one of the two QPSJs; at least one input voltage source coupled to the two QPSJs so that the two QPSJs, the load capacitor and the at least one input voltage source define a loop; and an excitation voltage source coupled to the two charge islands through first and second capacitors, respectively.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 29, 2020
    Assignee: AUBURN UNIVERSITY
    Inventors: Michael C. Hamilton, Uday S. Goteti
  • Patent number: 10700256
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 30, 2020
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 10396269
    Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 27, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
  • Patent number: 10366924
    Abstract: A chip carrier includes a redistribution structure, wherein the redistribution structure includes: a dielectric layer extending in a horizontal direction; a first electrically conductive layer arranged over the dielectric layer and extending in the horizontal direction; a trench arranged in the dielectric layer and extending in the horizontal direction; and a filling material filling the trench, wherein the filling material is different from the material of the dielectric layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Steffen Jordan
  • Patent number: 10361354
    Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt
  • Patent number: 9953269
    Abstract: A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry M. Chow, Jay M. Gambetta, Mary B. Rothwell, James R. Rozen
  • Patent number: 9768371
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 19, 2017
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 9666783
    Abstract: An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 30, 2017
    Assignee: Forschungszentrum Juelich GmbH
    Inventor: Mikhail Faley
  • Patent number: 9432024
    Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jerry M. Chow, Jay M. Gambetta, Seth T. Merkel, Chad T. Rigetti, Matthias Steffen
  • Patent number: 9260289
    Abstract: An optical-microwave-quantum transducer can include a tapered optical fiber configured to transmit and receive optical signals. The optical-microwave-quantum transducer can also include a cantilever that can include an optical cavity that includes a nanophotonic crystal. The optical cavity can be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons emitted from the tapered optical fiber. The cantilever can also include a mechanical coupler that is configured to induce electrical modulation onto a superconducting cavity in response to the mechanical excitation. The mechanical coupler can also be configured to provide mechanical excitation in response to electromagnetic excitation induced by photons from the superconducting cavity. The optical cavity can further be configured to provide electromagnetic excitation that induces optical modulation on the tapered optical fiber in response to the mechanical excitation.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 16, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Jae I. Park
  • Patent number: 9136046
    Abstract: Impurities are reduced in an oxide superconducting layer and in an interface between the oxide superconducting layer and an intermediate layer. A superconducting wire rod 1 has a structure including a substrate (10), an intermediate layer (20) formed on the substrate (10), a reaction suppressing layer (28) formed on the intermediate layer (20) and mainly containing polycrystalline SrLaFeO4+?1 or CaLaFeO4+?2, in which the ?1 and the ?2 each represent an amount of non-stoichiometric oxygen, and an oxide superconducting layer (30) formed on the reaction suppressing layer (28) and mainly containing an oxide superconductor.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: September 15, 2015
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hiroyuki Fukushima, Yuko Hayase, Yoshikazu Okuno, Eiji Kojima
  • Patent number: 9035283
    Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first conductive layer is disposed in the first trench. A first insulating layer is disposed between the first conductive layer and the epitaxial layer. A second conductive layer is disposed on a sidewall of the second trench. A second insulating layer is disposed between the second conductive layer and the body layer, and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills up the second trench. Two doped regions are disposed in the body layer respectively beside the second trench.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 19, 2015
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chien-Ling Chan, Chi-Hsiang Lee
  • Patent number: 8796181
    Abstract: The invention pertains to creating new extremely low resistance (“ELR”) materials, which may include high temperature superconducting (“HTS”) materials. In some implementations of the invention, an ELR material may be modified by depositing a layer of modifying material unto the ELR material to form a modified ELR material. The modified ELR material has improved operational characteristics over the ELR material alone. Such operational characteristics may include operating at increased temperatures or carrying additional electrical charge or other operational characteristics. In some implementations of the invention, the ELR material is a cuprate-perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Digital Signal Corporation
    Inventors: Douglas J. Gilbert, Timothy S. Cale
  • Patent number: 8754469
    Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, John Lin
  • Patent number: 8648331
    Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described. The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 11, 2014
    Assignee: Microsoft Corporation
    Inventors: Parsa Bonderson, Roman Lutchyn
  • Patent number: 8507320
    Abstract: One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 13, 2013
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Henrik Ewe, Klaus Schiess, Manfred Mengel
  • Patent number: 8330145
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 11, 2012
    Assignees: The Chugoku Electric Power Co., Inc., Hitachi Ltd., Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
  • Patent number: 8243769
    Abstract: A semiconductor light emitting device downsized by devising arrangement of connection pads is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has a stripe-shaped semiconductor layer formed on a second substrate on the side facing to a first substrate, a stripe-shaped p-side electrode supplying a current to the semiconductor layer, stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting device and electrically connected to the p-side electrodes of the first light emitting device, connection pads respectively and electrically connected to the respective opposed electrodes, and a connection pad electrically connected to the p-side electrode. The connection pads are arranged in parallel with the opposed electrodes.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 14, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Furushima, Abe Hiroaki, Kudou Hisashi, Fujimoto Tsuyoshi, Kentaro Aoshima
  • Patent number: 8211833
    Abstract: The invention pertains to creating new extremely low resistance (“ELR”) materials, which may include high temperature superconducting (“HTS”) materials. In some implementations of the invention, an ELR material may be modified by depositing a layer of modifying material unto the ELR material to form a modified ELR material. The modified ELR material has improved operational characteristics over the ELR material alone. Such operational characteristics may include operating at increased temperatures or carrying additional electrical charge or other operational characteristics. In some implementations of the invention, the ELR material is a cuprate-perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 3, 2012
    Assignee: Ambature, LLC
    Inventors: Douglas J. Gilbert, Timothy S. Cale
  • Patent number: 8200304
    Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 12, 2012
    Assignee: Japan Science and Technology Agency
    Inventors: Atsutaka Maeda, Espinoza Luis Beltran Gomez
  • Patent number: 8055318
    Abstract: A new family of superconducting materials with critical temperature up to 55 K have recently been discovered, comprising a crystal structure with atomic layers of iron and arsenic alternating with atomic layers of rare-earth oxide or alkaline earth. The present invention identifies structures for integrated circuit elements (including Josephson junctions) in these and related materials. These superconducting circuit elements will operate at a higher temperature than low-temperature superconductors such as niobium, and may be easier to manufacture than prior-art high-temperature superconductors based on copper-oxides.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 8, 2011
    Assignee: Hypres, Inc.
    Inventor: Alan M. Kadin
  • Patent number: 8032196
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: October 4, 2011
    Assignees: Chugoku Electric Power Co., Inc., International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7910916
    Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: March 22, 2011
    Assignee: Kyocera Corporation
    Inventors: Koichiro Niira, Hirofumi Senta, Hideki Hakuma
  • Patent number: 7579699
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 25, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7566896
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: July 28, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7525202
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 28, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7474010
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: January 6, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7453162
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: November 18, 2008
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7411187
    Abstract: A micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. A single 111Cd+ ion is confined, laser cooled, and the heating measured in an integrated radiofrequency trap etched from a doped gallium arsenide (GaAs) heterostructure. Single 111Cd+ qubit ions are confined in a radiofrequency linear ion trap on a semiconductor chip by applying a combination of static and oscillating electric potentials to integrated electrodes. The electrodes are lithographically patterned from a monolithic semiconductor substrate, eliminating the need for manual assembly and alignment of individual electrodes. The scaling of this structure to hundreds or thousands of electrodes is possible with existing semiconductor fabrication technology.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: August 12, 2008
    Assignee: The Regents of the University of Michigan
    Inventors: Christopher Monroe, Daniel Stick, Martin Madsen, Winfried Hensinger, Keith Schwab
  • Patent number: 7372067
    Abstract: Refractive index changing apparatus includes quantum dots each having discrete energy levels including ground level and excited level, the excited level being higher than the ground level even if energy due to ambient temperature is provided on the quantum dots, barrier structure unit formed of dielectric which surrounds the quantum dots, injection unit configured to inject an electron into position of the ground level in each quantum dot via the barrier structure unit, utilizing tunneling effect, or to prevent injection of an electron into the position, injecting the electron or preventing injection of the electron controlled by changing an energy level of the injection unit, source which emits, to the quantum dots, first light beam having first energy for exciting electrons from the ground level to the excited level, and source which emits, to the quantum dots, second light beam having second energy different from the first energy.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Todori, Reiko Yoshimura, Fumihiko Aiga, Tsukasa Tada
  • Publication number: 20080051292
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7319258
    Abstract: A semiconductor-on-insulator device includes a silicon active layer with a <100> crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a <110> crystal direction. Transistors oriented on a <100> direction are formed on the silicon active layer.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: January 15, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Liang Yang, Yee-Chia Yeo, Hung-Wei Chen, Tim Tsao, Chenming Hu
  • Patent number: 7312182
    Abstract: Rare earth metal containing compounds of the formula Sr2LuSbO6 and Sr2LaSbO6 have been prepared as high critical temperature thin film superconductor structures, and can be used in other ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: December 25, 2007
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Arthur Tauber, Robert D. Finnegan, William D. Wilber, Steven C. Tidrow, Donald W. Eckart, William C. Drach
  • Patent number: 7091515
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 15, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 7012275
    Abstract: A layered article of manufacture and a method of manufacturing same is disclosed. A substrate has a biaxially textured MgO crystalline layer having the c-axes thereof inclined with respect to the plane of the substrate deposited thereon. A layer of one or more of YSZ or Y2O3 and then a layer of CeO2 is deposited on the MgO. A crystalline superconductor layer with the c-axes thereof normal to the plane of the substrate is deposited on the CeO2 layer. Deposition of the MgO layer on the substrate is by the inclined substrate deposition method developed at Argonne National Laboratory. Preferably, the MgO has the c-axes thereof inclined with respect to the normal to the substrate in the range of from about 10° to about 40° and YBCO superconductors are used.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: March 14, 2006
    Assignee: The University of Chicago
    Inventors: Uthamalingam Balachandran, Beihai Ma, Dean Miller
  • Patent number: 6999806
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 14, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6995390
    Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 7, 2006
    Inventor: Katsuyuki Tsukui
  • Patent number: 6987282
    Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: January 17, 2006
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Alexandre Blais
  • Patent number: 6984846
    Abstract: A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, David P. DiVincenzo, Roger H. Koch, Glenn J. Martyna, Jim Rozen, Chang Chyi Tsuei
  • Patent number: 6979836
    Abstract: A superconducting structure that can operate, for example, as a qubit or a superconducting switch is presented. The structure includes a loop formed from two parts. A first part includes two superconducting materials separated by a junction. The junction can, for example, be a 45° grain boundary junction. The second part can couple the two superconducting materials across the junction. The second part includes a superconducting material coupled to each of the two superconducting materials of the first part through c-axis junctions. Further embodiments of the invention can be as a coherent unconventional superconducting switch, or a variable phase shift unconventional superconductor junction device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 27, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre M. Zagoskin, Alexander Ya. Tzalenchuk, Jeremy P. Hilton
  • Patent number: 6919579
    Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 19, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Alexandre Blais
  • Patent number: 6911665
    Abstract: A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: June 28, 2005
    Assignees: National Institute of Advanced Industrial Science and Technology, PI R&D Co., Ltd.
    Inventors: Masahiro Aoyagi, Hiroshi Nakagawa, Kazuhiko Tokoro, Katsuya Kikuchi, Hiroshi Itatani, Sigemasa Segawa
  • Patent number: 6815708
    Abstract: An optic superconducting circuit element (10) is disclosed that is operable to transmit and receive on an identical chip an electromagnetic wave having frequencies in an extended frequency band ranging from microwave to THz frequency bands and with high sensitivity. The optic superconducting circuit element (10) includes the chip (3), and a superconducting electromagnetic wave oscillating (generating and transmitting) source (16) and a superconducting Josephson junction device (14) disposed in close vicinity to each other on the chip (3), the superconducting Josephson junction device (14) detecting the electromagnetic wave transmitted from the superconducting electromagnetic wave oscillating (generating and transmitting) source (16).
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: November 9, 2004
    Assignee: Japan Science and Technology Agency
    Inventors: Ienari Iguchi, Eiji Kume
  • Publication number: 20040206952
    Abstract: An article including a substrate, a layer of an inert oxide material upon the surface of the substrate, a layer of an amorphous oxide or oxynitride material upon the inert oxide material layer, a layer of an oriented cubic oxide material having a rock-salt-like structure upon the amorphous oxide material layer, and a layer of a SrRuO3 buffer material upon the oriented cubic oxide material layer is provided together with additional layers such as a HTS top-layer of YBCO directly upon the layer of a SrRuO3 buffer material layer. With a HTS top-layer of YBCO upon at least one layer of the SrRuO3 buffer material in such an article, Jc's of up to 1.3×106 A/cm2 have been demonstrated with projected Ic's of over 200 Amperes across a sample 1 cm wide.
    Type: Application
    Filed: May 6, 2004
    Publication date: October 21, 2004
    Inventors: Quanxi Jia, Stephen R. Foltyn, Paul N. Arendt, James R. Groves
  • Patent number: 6790675
    Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignees: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Yoshihiro Ishimaru, Masahiro Horibe, Osami Horibe, Yoshinobu Tarutani, Keiichi Tanabe