Weak Link (e.g., Narrowed Portion Of Superconductive Line) Patents (Class 257/34)
  • Patent number: 10461445
    Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating superconducting circuits. In one aspect, an electric circuit includes: (1) a first superconducting component having a first terminal, a second terminal, and a constriction region between the first terminal and the second terminal; (2) a second superconducting component having a third terminal and a fourth terminal; and (3) a first electrically-insulating component that thermally couples the first superconducting component and the second superconducting component such that heat produced at the constriction region is transferred through the first component to the second superconducting component.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 29, 2019
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Qiaodan Jin Stone
  • Patent number: 10367134
    Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt
  • Patent number: 9748391
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Patent number: 9646259
    Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 9, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
  • Patent number: 9559284
    Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Josephine B. Chang, Paul Chang, Guy M. Cohen, Michael A. Guillorn
  • Patent number: 9344092
    Abstract: A technique relates to a superconductor tunable notch filter. A Josephson junction filter array is connected to a coupling pad and connected to ground. The Josephson junction filter array includes a filter inductance. The Josephson junction filter array connected to the coupling pad forms a filter capacitance. A Josephson junction bias array is connected to the coupling pad and connected to a current source. The Josephson junction bias array includes a bias inductance. A transmission line is connected to the coupling pad in which connection of the transmission line and the coupling pad forms a coupling capacitance, such that the filter inductance and the filter capacitance connect to the transmission line through the coupling capacitance. The Josephson junction filter array includes a notch filter frequency that is tunable according to a magnitude of a current bias from the current source.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, Jerry M. Chow, Jay M. Gambetta, Nicholas A. Masluk, Matthias Steffen
  • Publication number: 20150069331
    Abstract: An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 12, 2015
    Inventor: Mikhail Faley
  • Patent number: 8852959
    Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Northrup Grumman Systems Corporation
    Inventors: John J. Talvacchio, Erica C. Folk, Sean R. McLaughlin, David J. Phillips
  • Patent number: 8829523
    Abstract: The present invention provides a thin film transistor (TFT) manufacturing method and a TFT, a source electrode or drain electrode of the TFT is electrically connected to a data line directly during a forming process by providing a through hole in a surface above the data line of the TFT, so as to save the process cost. Further, the source electrode and drain electrode of the TFT are also manufactured with poly-silicon rather than metal material used in prior art, processing steps are simplified, thereby further saving the process cost.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Shijian Qin, Chengming He
  • Patent number: 8822979
    Abstract: Disclosed is an arrangement including a support and a super-conductive film which is arranged thereon. The film has a plurality of holes in order to form a perforated grating. The holes are optionally round holes having increasing sizes, triangular holes, or holes which are arranged in a meandering manner in the film, and which produce improved properties in relation to signal conversion by a vortex diode and/or in a filter. A DC signal is directly removed therein without additional electronics.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 2, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventor: Roger Woerdenweber
  • Patent number: 8759133
    Abstract: A back panel for a flat panel display apparatus includes: a pixel electrode disposed on a substrate; a first gate electrode layer of a thin-film transistor (TFT) disposed on the substrate; a second gate electrode layer disposed on the first gate electrode layer and including a semiconductor material; a third gate electrode layer disposed on the second gate electrode layer and including a metal material; a first insulating layer disposed on the third gate electrode layer; an active layer disposed on the first insulating layer and including a transparent conductive oxide semiconductor; a second insulating layer disposed on the active layer; source and drain electrodes disposed connected to the active layer through the second insulating layer; and a third insulating layer covering the source and drain electrodes. The first gate electrode layer and the pixel electrode include a transparent conductive oxide.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Ii Park, Chaun-Gi Choi, Tae-Kyung Ahn
  • Patent number: 8742508
    Abstract: A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.
    Type: Grant
    Filed: July 16, 2011
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8654578
    Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 18, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rupert M. Lewis, Ofer Naaman
  • Patent number: 8510618
    Abstract: Systems and methods are provided for performing a quantum error correction. An error correction is performed on each of a plurality of qubit sets restore a desired basis state of the qubit set. Each qubit set corresponds to an associated logical qubit. A number of corrected qubits at each of the plurality of qubit sets are recorded. A first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state are determined. One of the first set of logical qubits and the second set of logical qubits are corrected according to the recorded numbers of corrected qubits.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Aaron A. Pesetski, James E. Baumgardner
  • Patent number: 8437168
    Abstract: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a ?-junction (6) and a 0-junction (7); and a quantum state detecting member (20) constituted by a superconducting quantum interference device arranged outside of the superconducting ring member, wherein a bonding and an antibonding state brought about by a tunneling effect between a |?> and a |?> state as two states degenerate in energy of the superconducting ring member (10) are regarded as quantum bits. The bonding and antibonding states as the quantum bits are read out by the quantum state detecting member (20). The two bit controlled NOT gate operation can be performed by the two quantum bits comprising said quantum bits.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 7, 2013
    Assignee: Japan Science and Technology Agency
    Inventors: Sadamichi Maekawa, Taro Yamashita, Saburo Takahashi
  • Patent number: 8362561
    Abstract: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: January 29, 2013
    Assignee: NXP B.V.
    Inventors: Sebastien Nuttinck, Gilberto Curatola
  • Patent number: 8330145
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 11, 2012
    Assignees: The Chugoku Electric Power Co., Inc., Hitachi Ltd., Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
  • Patent number: 8284585
    Abstract: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a ?-junction (6) and a 0-junction (7); and a quantum state detecting member (20) constituted by a superconducting quantum interference device arranged outside of the superconducting ring member, wherein a bonding and an antibonding state brought about by a tunneling effect between a |?> and a |?> state as two states degenerate in energy of the superconducting ring member (10) are regarded as quantum bits. The bonding and antibonding states as the quantum bits are read out by the quantum state detecting member (20). The two bit controlled NOT gate operation can be performed by the two quantum bits comprising said quantum bits.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: October 9, 2012
    Assignee: Japan Science and Technology Agency
    Inventors: Sadamichi Maekawa, Taro Yamashita, Saburo Takahashi
  • Patent number: 8200304
    Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 12, 2012
    Assignee: Japan Science and Technology Agency
    Inventors: Atsutaka Maeda, Espinoza Luis Beltran Gomez
  • Patent number: 8076221
    Abstract: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 13, 2011
    Assignee: Au Optronics Corporation
    Inventor: Chin-Kuo Ting
  • Patent number: 7979101
    Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 12, 2011
    Assignee: National Institute of Information and Communications Technology, Incorporated Administrative Agency
    Inventors: Toshiaki Matsui, Hiroshi Ohta, Akira Kawakami
  • Patent number: 7923717
    Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 12, 2011
    Inventor: Katsuyuki Tsukui
  • Patent number: 7858966
    Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 28, 2010
    Assignee: Microsoft Corporation
    Inventor: Alexei Kitaev
  • Patent number: 7579699
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 25, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7566896
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: July 28, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7525202
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 28, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7522078
    Abstract: The length portion of part of a multiband superconductor line 10 is used as a closed circuit line part Rc that constitutes part of a closed circuit allowing passage of an electric current Io generated by an electric current source 12. Meantime, the line part extending and continuing into the closed circuit line part Rc is used as an open circuit line part Ro adapted to serve as an open circuit regarding the electric current source 12. By keeping the multiband superconductor line 10 under a temperature environment falling short of the critical soliton temperature and injecting a nonequilibrium electric current Io from the electric current source 12 into the closed circuit line part of the multiband superconductor line, it is rendered possible to induce generation of an interband phase different soliton So. The generated interband phase difference soliton So is forwarded as separated from the electric current Io to the open circuit line part Ro and is made to run therein.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: April 21, 2009
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yasumoto Tanaka, Akira Iyo, Adrian Crisan, Kazuyasu Tokiwa, Tsuneo Watanabe, Norio Terada
  • Patent number: 7479652
    Abstract: This invention concerns quantum computers in which the qubits are closed systems, in that the particle or particles are confined within the structure. A “site” can be produced by any method of confining an electron or other quantum particle, such as a dopant atom, a quantum dot, a cooper pair box, or any combination of these. In particular the invention concerns a closed three-site quantum particle system. The state in the third site is weakly coupled by coherent tunneling to the first and second states, so that the third state is able to map out the populations of the first and second states as its energy is scanned with respect to the first and second states. In second and third aspects it concerns a readout method for a closed three-state quantum particle system.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 20, 2009
    Assignee: Qucor Pty. Ltd.
    Inventors: Andrew D. Greentree, Alexander Rudolf Hamilton, Frederick Green, Lloyd Christopher Leonard Hollenberg
  • Patent number: 7474010
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: January 6, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7453162
    Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: November 18, 2008
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 7451292
    Abstract: Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision, the input data, preferably a qubit, is collapsed to a point value within the quantum gap based on a software instruction. After collapse the input data is restructured at the destination, wherein dynamics of restructuring are governed by a plurality of gap factors as follows: computational self-awareness; computational decision logic; computational processing logic; computational and network protocol and logic exchange; computational and network components, logic and processes; provides the basis for excitability of the Gap junction and its ability to transmit electronic and optical impulses, integrates them properly, and depends on feedback loop logic; computational and network component and system interoperability; and embodiment substrate and network computational physical topology.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: November 11, 2008
    Inventor: Thomas J Routt
  • Patent number: 7449769
    Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: November 11, 2008
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventor: Tsunehiro Hato
  • Patent number: 7335909
    Abstract: A quantum computing structure comprising a superconducting phase-charge qubit, wherein the superconducting phase-charge qubit comprises a superconducting loop with at least one Josephson junction. The quantum computing structure also comprises a first mechanism for controlling a charge of the superconducting phase-charge qubit and a second mechanism for detecting a charge of the superconducting phase-charge qubit, wherein the first mechanism and the second mechanism are each capacitively connected to the superconducting phase-charge qubit.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: February 26, 2008
    Assignee: D-Wave Systems Inc.
    Inventors: Mohammad H. S. Amin, Jeremy P. Hilton, Geordie Rose
  • Patent number: 7332738
    Abstract: A method for reading out the state of a mesoscopic phase device. In the method the mesoscopic phase device is coherently coupled to a mesoscopic charge device using a phase shift device and the quantum state of the mesoscopic charge device is measured. A method for reading out the quantum state of a qubit in a heterogeneous quantum register. The heterogeneous quantum register includes a first plurality of phase qubits and a second plurality of charge qubits. In the method a first phase qubit or a first charge qubit in the heterogeneous quantum register is selected. The first phase qubit or the first charge qubit is coherently connected to a mesoscopic charge device for a duration tc. The quantum state of the mesoscopic charge device is read out after the duration tc has elapsed.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: February 19, 2008
    Assignee: D-Wave Systems Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton
  • Patent number: 7323711
    Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: January 29, 2008
    Assignees: FUJITSU Limited, International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Hideo Suzuki, Masahiro Horibe, Keiichi Tanabe
  • Patent number: 7307275
    Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 11, 2007
    Assignees: D-Wave Systems Inc., The University of Toronto
    Inventors: Daniel Lidar, Lian-Ao Wu, Alexandre Blais
  • Patent number: 7224019
    Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 29, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Daisuke Hagishima
  • Patent number: 7091515
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 15, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 7087925
    Abstract: In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a further embodiment, the spacing between adjacent rows is less than the spacing between shapes within a row.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: August 8, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Gordon M. Grivna
  • Patent number: 7075171
    Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 11, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center
    Inventor: Tsunehiro Hato
  • Patent number: 6995390
    Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 7, 2006
    Inventor: Katsuyuki Tsukui
  • Patent number: 6987282
    Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: January 17, 2006
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Alexandre Blais
  • Patent number: 6984846
    Abstract: A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, David P. DiVincenzo, Roger H. Koch, Glenn J. Martyna, Jim Rozen, Chang Chyi Tsuei
  • Patent number: 6958487
    Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A ?/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: October 25, 2005
    Assignee: Utsunomiya University
    Inventors: Akinobu Irie, Ginichiro Oya
  • Patent number: 6919579
    Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 19, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Alexandre Blais
  • Patent number: 6839578
    Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristics conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: January 4, 2005
    Assignee: National Institute for Materials Science
    Inventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
  • Patent number: 6838694
    Abstract: A superconducting quantum-bit device based on Josephson junction has a charge as a first principal degree of freedom assigned to writing and a phase as a second principal degree of freedom assigned to reading. The device comprises a Cooper-pair box comprising first and second Josephson junctions defining a charge island of the Cooper-pair box closing up onto a superconducting loop. A read circuit comprises a read Josephson junction JL inserted into the superconducting loop and having a Josephson energy Ej at least 50 times greater than the Josephson energy of each of the first and second Josephson junctions.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: January 4, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Daniel Esteve, Denis Vion, Michel Devoret, Cristian Urbina, Philippe Joyez, Hughes Pothier, Pierre-Francois Orfila, Abdelhahim Aassime, Audrey Cottet
  • Publication number: 20040232405
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Application
    Filed: March 26, 2004
    Publication date: November 25, 2004
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6822255
    Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: November 23, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
  • Publication number: 20040222411
    Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.
    Type: Application
    Filed: April 16, 2004
    Publication date: November 11, 2004
    Inventors: Petar B. Atanackovic, Larry R. Marshall