Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.

Abstract: Various fabrication method are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.

Abstract: A method of making a Josephson junction in a superconducting qubit includes providing a substrate having a convex structure with a first face and a second face meeting at an edge; depositing a first layer of superconducting material on the first face; oxidizing the first layer to form a layer of oxide material on a surface of the first layer; and depositing a second layer of the superconducting material on the second face. A portion of the second layer is in contact with a portion of the layer of oxide material at or in the vicinity of the edge such that the portion of the layer of oxide material is sandwiched between a portion of the first layer and the portion of the second layer to define a Josephson junction at or in the vicinity of the edge.

Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Abstract: A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending along a first direction. The method further includes depositing, on the distinct instances of the first conductive material, a set of device layers. The method further includes electrically isolating distinct instances of the device layers to form spin orbit torque magnetic random access memory (SOT-MRAM) devices positioned on distinct instances of the first conductive material. The method further includes depositing, on the distinct instances of the device layers, a layer of a second conductive material and electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction. The second direction is different from the first direction.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating superconducting circuits. In one aspect, an electric circuit includes: (1) a first superconducting component having a first terminal, a second terminal, and a constriction region between the first terminal and the second terminal; (2) a second superconducting component having a third terminal and a fourth terminal; and (3) a first electrically-insulating component that thermally couples the first superconducting component and the second superconducting component such that heat produced at the constriction region is transferred through the first component to the second superconducting component.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.

Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.

Abstract: A technique relates to a superconductor tunable notch filter. A Josephson junction filter array is connected to a coupling pad and connected to ground. The Josephson junction filter array includes a filter inductance. The Josephson junction filter array connected to the coupling pad forms a filter capacitance. A Josephson junction bias array is connected to the coupling pad and connected to a current source. The Josephson junction bias array includes a bias inductance. A transmission line is connected to the coupling pad in which connection of the transmission line and the coupling pad forms a coupling capacitance, such that the filter inductance and the filter capacitance connect to the transmission line through the coupling capacitance. The Josephson junction filter array includes a notch filter frequency that is tunable according to a magnitude of a current bias from the current source.

Abstract: An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy.

Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.

Abstract: The present invention provides a thin film transistor (TFT) manufacturing method and a TFT, a source electrode or drain electrode of the TFT is electrically connected to a data line directly during a forming process by providing a through hole in a surface above the data line of the TFT, so as to save the process cost. Further, the source electrode and drain electrode of the TFT are also manufactured with poly-silicon rather than metal material used in prior art, processing steps are simplified, thereby further saving the process cost.

Abstract: Disclosed is an arrangement including a support and a super-conductive film which is arranged thereon. The film has a plurality of holes in order to form a perforated grating. The holes are optionally round holes having increasing sizes, triangular holes, or holes which are arranged in a meandering manner in the film, and which produce improved properties in relation to signal conversion by a vortex diode and/or in a filter. A DC signal is directly removed therein without additional electronics.

Abstract: A back panel for a flat panel display apparatus includes: a pixel electrode disposed on a substrate; a first gate electrode layer of a thin-film transistor (TFT) disposed on the substrate; a second gate electrode layer disposed on the first gate electrode layer and including a semiconductor material; a third gate electrode layer disposed on the second gate electrode layer and including a metal material; a first insulating layer disposed on the third gate electrode layer; an active layer disposed on the first insulating layer and including a transparent conductive oxide semiconductor; a second insulating layer disposed on the active layer; source and drain electrodes disposed connected to the active layer through the second insulating layer; and a third insulating layer covering the source and drain electrodes. The first gate electrode layer and the pixel electrode include a transparent conductive oxide.

Abstract: A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: Systems and methods are provided for performing a quantum error correction. An error correction is performed on each of a plurality of qubit sets restore a desired basis state of the qubit set. Each qubit set corresponds to an associated logical qubit. A number of corrected qubits at each of the plurality of qubit sets are recorded. A first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state are determined. One of the first set of logical qubits and the second set of logical qubits are corrected according to the recorded numbers of corrected qubits.

Abstract: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a ?-junction (6) and a 0-junction (7); and a quantum state detecting member (20) constituted by a superconducting quantum interference device arranged outside of the superconducting ring member, wherein a bonding and an antibonding state brought about by a tunneling effect between a |?> and a |?> state as two states degenerate in energy of the superconducting ring member (10) are regarded as quantum bits. The bonding and antibonding states as the quantum bits are read out by the quantum state detecting member (20). The two bit controlled NOT gate operation can be performed by the two quantum bits comprising said quantum bits.

Abstract: A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a ?-junction (6) and a 0-junction (7); and a quantum state detecting member (20) constituted by a superconducting quantum interference device arranged outside of the superconducting ring member, wherein a bonding and an antibonding state brought about by a tunneling effect between a |?> and a |?> state as two states degenerate in energy of the superconducting ring member (10) are regarded as quantum bits. The bonding and antibonding states as the quantum bits are read out by the quantum state detecting member (20). The two bit controlled NOT gate operation can be performed by the two quantum bits comprising said quantum bits.

Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.

Abstract: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.

Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: The length portion of part of a multiband superconductor line 10 is used as a closed circuit line part Rc that constitutes part of a closed circuit allowing passage of an electric current Io generated by an electric current source 12. Meantime, the line part extending and continuing into the closed circuit line part Rc is used as an open circuit line part Ro adapted to serve as an open circuit regarding the electric current source 12. By keeping the multiband superconductor line 10 under a temperature environment falling short of the critical soliton temperature and injecting a nonequilibrium electric current Io from the electric current source 12 into the closed circuit line part of the multiband superconductor line, it is rendered possible to induce generation of an interband phase different soliton So. The generated interband phase difference soliton So is forwarded as separated from the electric current Io to the open circuit line part Ro and is made to run therein.

Abstract: This invention concerns quantum computers in which the qubits are closed systems, in that the particle or particles are confined within the structure. A “site” can be produced by any method of confining an electron or other quantum particle, such as a dopant atom, a quantum dot, a cooper pair box, or any combination of these. In particular the invention concerns a closed three-site quantum particle system. The state in the third site is weakly coupled by coherent tunneling to the first and second states, so that the third state is able to map out the populations of the first and second states as its energy is scanned with respect to the first and second states. In second and third aspects it concerns a readout method for a closed three-state quantum particle system.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision, the input data, preferably a qubit, is collapsed to a point value within the quantum gap based on a software instruction. After collapse the input data is restructured at the destination, wherein dynamics of restructuring are governed by a plurality of gap factors as follows: computational self-awareness; computational decision logic; computational processing logic; computational and network protocol and logic exchange; computational and network components, logic and processes; provides the basis for excitability of the Gap junction and its ability to transmit electronic and optical impulses, integrates them properly, and depends on feedback loop logic; computational and network component and system interoperability; and embodiment substrate and network computational physical topology.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: A quantum computing structure comprising a superconducting phase-charge qubit, wherein the superconducting phase-charge qubit comprises a superconducting loop with at least one Josephson junction. The quantum computing structure also comprises a first mechanism for controlling a charge of the superconducting phase-charge qubit and a second mechanism for detecting a charge of the superconducting phase-charge qubit, wherein the first mechanism and the second mechanism are each capacitively connected to the superconducting phase-charge qubit.

Abstract: A method for reading out the state of a mesoscopic phase device. In the method the mesoscopic phase device is coherently coupled to a mesoscopic charge device using a phase shift device and the quantum state of the mesoscopic charge device is measured. A method for reading out the quantum state of a qubit in a heterogeneous quantum register. The heterogeneous quantum register includes a first plurality of phase qubits and a second plurality of charge qubits. In the method a first phase qubit or a first charge qubit in the heterogeneous quantum register is selected. The first phase qubit or the first charge qubit is coherently connected to a mesoscopic charge device for a duration tc. The quantum state of the mesoscopic charge device is read out after the duration tc has elapsed.

Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.

Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.

Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.

Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.

Abstract: In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a further embodiment, the spacing between adjacent rows is less than the spacing between shapes within a row.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.

Abstract: A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.

Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A ?/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.