Weak Link (e.g., Narrowed Portion Of Superconductive Line) Patents (Class 257/34)
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Patent number: 6919579Abstract: A solid-state quantum computing qubit includes a multi-terminal junction coupled to a superconducting loop where the superconducting loop introduces a phase shift to the superconducting order parameter. The ground state of the supercurrent in the superconducting loop and multi-terminal junction is doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents in the superconducting loop create qubits for quantum computing. The quantum states can be initialized by applying transport currents to the external leads. Arbitrary single qubit operations may be performed by varying the transport current and/or an externally applied magnetic field. Read-out may be performed using direct measurement of the magnetic moment of the qubit state, or alternatively, radio-frequency single electron transistor electrometers can be used as read-out devices when determining a result of the quantum computing.Type: GrantFiled: April 20, 2001Date of Patent: July 19, 2005Assignee: D-Wave Systems, Inc.Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Alexandre Blais
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Patent number: 6839578Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristics conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.Type: GrantFiled: June 9, 2003Date of Patent: January 4, 2005Assignee: National Institute for Materials ScienceInventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
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Patent number: 6838694Abstract: A superconducting quantum-bit device based on Josephson junction has a charge as a first principal degree of freedom assigned to writing and a phase as a second principal degree of freedom assigned to reading. The device comprises a Cooper-pair box comprising first and second Josephson junctions defining a charge island of the Cooper-pair box closing up onto a superconducting loop. A read circuit comprises a read Josephson junction JL inserted into the superconducting loop and having a Josephson energy Ej at least 50 times greater than the Josephson energy of each of the first and second Josephson junctions.Type: GrantFiled: September 16, 2002Date of Patent: January 4, 2005Assignee: Commissariat a l'Energie AtomiqueInventors: Daniel Esteve, Denis Vion, Michel Devoret, Cristian Urbina, Philippe Joyez, Hughes Pothier, Pierre-Francois Orfila, Abdelhahim Aassime, Audrey Cottet
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Publication number: 20040232405Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.Type: ApplicationFiled: March 26, 2004Publication date: November 25, 2004Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
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Patent number: 6822255Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.Type: GrantFiled: January 23, 2003Date of Patent: November 23, 2004Assignee: D-Wave Systems, Inc.Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
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Publication number: 20040222411Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.Type: ApplicationFiled: April 16, 2004Publication date: November 11, 2004Inventors: Petar B. Atanackovic, Larry R. Marshall
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Patent number: 6812484Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.Type: GrantFiled: January 23, 2003Date of Patent: November 2, 2004Assignee: D-Wave Systems, Inc.Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
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Patent number: 6784451Abstract: In one embodiment, a two-junction phase qubit includes a superconducting loop and two Josephson junctions separated by a mesoscopic island on one side and a bulk loop on another side. The material forming the superconducting loop is a superconducting material with an order parameter that violates time reversal symmetry. In one embodiment, a two-junction phase qubit includes a loop of superconducting material, the loop having a bulk portion and a mesoscopic island portion. The loop further includes a relatively small gap located in the bulk portion. The loop further includes a first Josephson junction and a second Josephson junction separating the bulk portion from the mesoscopic island portion. The superconducting material on at least one side of the first and second Josephson junctions has an order parameter having a non-zero angular momentum in its pairing symmetry. In one embodiment, a qubit includes a superconducting loop having a bulk loop portion and a mesoscopic island portion.Type: GrantFiled: December 17, 2002Date of Patent: August 31, 2004Assignee: D-Wave Systems Inc.Inventors: Mohammad H. S. Amin, Alexandre Zagoskin, Geordie Rose, Jeremy P. Hilton
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Patent number: 6734454Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.Type: GrantFiled: August 26, 2002Date of Patent: May 11, 2004Assignees: The Regents of the University of California, The Arizona Board of RegentsInventors: Theodore Van Duzer, Xiaoxan Meng, Nathan Newman, Lei Yu, Anupama Bhat Kaul
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Publication number: 20040000666Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.Type: ApplicationFiled: April 4, 2003Publication date: January 1, 2004Inventors: Daniel Lidar, Lian-Ao Wu, Alexandre Blais
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Patent number: 6670630Abstract: A superconducting structure that includes a mesoscopic phase device and a mesoscopic charge device. The superconducting structure further includes a mechanism for coupling the mesoscopic phase device and the mesoscopic charge device so that the quantum state of the mesoscopic phase device and the quantum state of the mesoscopic charge device interact. In another aspect, the superconducting structure includes a mechanism for reading out the quantum state of the mesoscopic charge device.Type: GrantFiled: April 12, 2002Date of Patent: December 30, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexandre Blais, Jeremy P. Hilton
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Patent number: 6627916Abstract: A solid state dc-SQUID includes a superconducting loop containing a plurality of Josephson junctions, wherein an intrinsic phase shift is accumulated through the loop. In an embodiment of the invention, the current-phase response of the dc-SQUID sits in a linear regime where directional sensitivity to flux through the loop occurs. Changes in the flux passing through the superconducting loop stimulates current which can be quantified, thus providing a means of measuring the magnetic field. Given the linear and directional response regime of the embodied device, an inherent current to phase sensitivity is achieved that would otherwise be unobtainable in common dc-SQUID devices without extrinsic intervention.Type: GrantFiled: March 31, 2001Date of Patent: September 30, 2003Assignee: D-Wave Systems, Inc.Inventors: Mohammad H. S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Jeremy P. Hilton
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Publication number: 20030173997Abstract: A superconducting structure that includes a mesoscopic phase device and a mesoscopic charge device. The superconducting structure further includes a mechanism for coupling the mesoscopic phase device and the mesoscopic charge device so that the quantum state of the mesoscopic phase device and the quantum state of the mesoscopic charge device interact. In another aspect, the superconducting structure includes a mechanism for reading out the quantum state of the mesoscopic charge device.Type: ApplicationFiled: April 12, 2002Publication date: September 18, 2003Inventors: Alexandre Blais, Jeremy P. Hilton
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Patent number: 6614047Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.Type: GrantFiled: December 17, 2001Date of Patent: September 2, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
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Patent number: 6605822Abstract: A method for performing a quantum computing entanglement operation between a phase qubit and a charge qubit. A coherent connection between the phase qubit and the charge qubit is provided. The coherent connection allows the quantum state of the phase qubit and the quantum state of the charge qubit to interact with each other. The coherent connection is modulated for a duration te. The phase qubit is connected to the charge qubit during at least a portion of the duration te in order to controllably entangle the quantum state of the phase qubit and the quantum state of the charge qubit.Type: GrantFiled: April 12, 2002Date of Patent: August 12, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexandre Blais, Jeremy P. Hilton
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Patent number: 6580102Abstract: Quantum computing systems and methods that use opposite magnetic moment states read the state of a qubit by applying current through the qubit and measuring a Hall effect voltage across the width of the current. For reading, the qubit is grounded to freeze the magnetic moment state, and the applied current is limited to pulses incapable of flipping the magnetic moment. Measurement of the Hall effect voltage can be achieved with an electrode system that is capacitively coupled to the qubit. An insulator or tunnel barrier isolates the electrode system from the qubit during quantum computing. The electrode system can include a pair of electrodes for each qubit. A readout control system uses a voltmeter or other measurement device that connects to the electrode system, a current source, and grounding circuits. For a multi-qubit system, selection logic can select which qubit or qubits are read.Type: GrantFiled: June 5, 2001Date of Patent: June 17, 2003Assignee: D-Wave Systems, Inc.Inventors: Zdravko Ivanov, Alexander Tzalentchuk, Jeremy P. Hilton, Alexander Maassen van den Brink
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Publication number: 20030094606Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.Type: ApplicationFiled: May 16, 2002Publication date: May 22, 2003Inventors: Dennis M. Newns, Chang C. Tsuei
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Patent number: 6476413Abstract: A high temperature superconducting Josephson junction device with ramp-edge geometry in which silver is combined in a composite with YBa2Cu3O7, yttrium-barium-copper-oxide, to form the electrodes, or PrBa2Cu3O7, praseodymium-barium-copper-oxide, to form the weak link.Type: GrantFiled: April 24, 1998Date of Patent: November 5, 2002Assignee: The Regents of the University of CaliforniaInventors: Quanxi Jia, Xin Di Wu, Steven R. Foltyn, David W. Reagor
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Publication number: 20020084453Abstract: A hybrid oxide heterostructure device is disclosed. The device includes a substrate, and formed monolithically on the substrate, by atomic layer-by-layer molecular-beam epitaxy, successive metal oxide layers forming a high-temperature superconducting (HTS) structure and a multi-layer magnetic memory/storage structure. The HTS structure includes one or more HTS metal oxide layers formed on the substrate, and electrical contacts formed on the one or more HTS layers. The magnetic-memory structure includes one or more metal oxide magnetic layers formed monolithically on, below, or between the layer(s) of the HTS device, and having electrical contacts formed on one or more of the magnetic layers. Application of current or voltage to an HTS structure, under conditions effective to establish a superconducting current in the HTS structure, is effective to alter read or write characteristics of the memory-storage structure.Type: ApplicationFiled: September 27, 2001Publication date: July 4, 2002Inventor: Ivan Bozovic
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Publication number: 20020074626Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.Type: ApplicationFiled: October 30, 2001Publication date: June 20, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshihiko Nagano, Jiro Yoshida
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Patent number: 6403977Abstract: A double-sided high-temperature superconducting flux-flow transistor is provided by advantageously placing a control line assembly and a weak-link assembly on opposite sides of a dielectric substrate to form a double-sided assembly that controls line current on the input side of the substrate that causes generation of vortices on the weak link structure patterned on the substrate's output side. Placing the two assemblies on opposite sides of the same substrate provides the operator with significant modulating capability for applications such as an amplifier or a mixer. Each side of the substrate is patterned and chemically etched to provide a control-line assembly opposed by a weak-link assembly, with the control-line assembly being patterned on the thicker substrate side.Type: GrantFiled: June 13, 2001Date of Patent: June 11, 2002Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Shapur Sahba
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Patent number: 6384423Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.Type: GrantFiled: February 7, 2000Date of Patent: May 7, 2002Assignee: TRW Inc.Inventors: George L. Kerber, Michael Leung
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Patent number: 6384424Abstract: A superconducting thin film pattern (20) formed from an oxide superconducting thin film is formed on a sapphire substrate (10) having a step (11) via a CeO2 buffer layer, and the step (11) and superconducting thin film pattern (20) are formed such that the step (11) crosses a predetermined portion of a square thin film pattern (22) having an opening portion (23) at the central portion. Step-edge Josephson junctions (26, 27) are formed at the portion crossed by the step (11), and a SQUID is obtained. The sapphire substrate is relatively inexpensive, and a large substrate can be used.Type: GrantFiled: October 11, 2000Date of Patent: May 7, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hirokazu Kugai, Yasuyuki Matsui, Tatsuoki Nagaishi, Hideo Itozaki
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Patent number: 6344659Abstract: The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus forming a double barrier quantum well, and first and second superconducting gate electrodes to control the source-drain current. The base electrode comprises a ferromagnetic material enabling resonant tunneling of source-drain electrons when there are bound states within the quantum well structure matching the energy of said source-drain electrons. The invention also relates to a logical element comprising such an interferometer arrangement and to a method of controlling the conductance of an interferometer.Type: GrantFiled: November 24, 1999Date of Patent: February 5, 2002Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Zdravko Ivanov, Robert Shekhter, Anatoli Kadiqrobov, Tord Claeson, Mats Jonson, Erland Wikborg
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Patent number: 6265752Abstract: The device includes a N+ buried layer in a substrate. A P-well is formed in an epitaxial layer on the buried layer. N-wells surround the P-well are also formed in the epitaxial layer. One of the N-well regions acts as a drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. Drain contact is formed in the N-well for drain. The source region of the device is formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate. The method includes forming a N+ buried layer in a P substrate. A P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. A plurality of field oxide (FOX) regions are created to define the active area.Type: GrantFiled: May 25, 1999Date of Patent: July 24, 2001Assignee: Taiwan Semiconductor Manufacturing, Co., Inc.Inventors: Kou-Chio Liu, Jyh-Min Jiang, Chen-Bau Wu, Ruey-Hsin Liou
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Patent number: 6239431Abstract: A system and method for using one or more localized weak-link structures, and damping on the electrical bias circuit, to improve the performance of superconducting transition-edge sensors (TES). The weak links generally consist of an area or areas having a reduction in cross-sectional geometry in an otherwise uniform bilayer TES applied to a substrate. The weak links control the dissipation of power in the sensor, making it quieter and making its electrical response smoother and less hysteretic. The TES response is also made smoother by implementing a damping circuit on the electrical output of the TES.Type: GrantFiled: November 24, 1998Date of Patent: May 29, 2001Assignee: The United States of America as represented by the Secretary of CommerceInventors: Gene Hilton, Kent David Irwin, John Martinis, David Wollman
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Patent number: 6229154Abstract: An ultra high speed and high sensitivity photo detecting element is fabricated by laminating thin film layers of superconducting material and ferromagnetic material on a substrate. A photo detecting element composed of a photo detecting portion formed on a substrate by laminating alternately at least a thin film layer of ferromagnetic material and at least a thin film layer of high temperature superconducting material between which a thin film layer of insulating material is sandwiched and electrodes connected to the photo detecting portion.Type: GrantFiled: March 25, 1999Date of Patent: May 8, 2001Assignee: Sharp Kabushiki KaishaInventors: Hideo Nojima, Kenji Nakanishi
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Patent number: 6225800Abstract: An arrangement for coupling an rf-SQUID magnetometer to a superconductive tank circuit on a substrate is constructed in such a way that the two components are fully integrated into each other. Such integration increases the quality of the tank circuit by a factor of 2 to 3 as opposed to an arrangement obtainable by the flip-chip technology. Furthermore, the integrated arrangement permits simple assessment of coupling “k” between the SQUID and the tank circuit.Type: GrantFiled: September 25, 1998Date of Patent: May 1, 2001Assignee: Forschungszentrum Jülich GmbHInventors: Yi Zhang, Jürgen Schubert, Willi Zander, Helmut Soltner, Marko Banzet
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Patent number: 6188084Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.Type: GrantFiled: March 11, 1999Date of Patent: February 13, 2001Assignee: TRW Inc.Inventors: George L. Kerber, Lynn A. Abelson, Raffi N. Elmadjian, Eric G. Ladizinsky
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Patent number: 6121630Abstract: A high-temperature superconducting thin film of compound oxide selected from the group consisting of:Y.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Ho.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Lu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Sm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Nd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Gd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Eu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Er.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Dy,Ba.sub.2 Cu.sub.3 O.sub.7-x,Tm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Yb.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x La.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,(La, Sr).sub.2 CuO.sub.4-x,which is deposited on a substrate of sapphire, with the outer surface of the high-temperature superconducting thin film being covered with a protective crystalline film of SrTiO.sub.3.Type: GrantFiled: May 20, 1998Date of Patent: September 19, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideo Itozaki, Saburo Tanaka, Nobuhiko Fujita, Shuji Yazu, Tetsuji Jodai
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Patent number: 6111268Abstract: The invention relates to an inverted JOFET with an at least bicrystalline electrically conductive substrate-layer bearing an insulating element and a superconductive element with a Josephson-junction. The substrate-layer is connected to a control-element. The invention further relates to a method for making such a JOFET. The grain boundary in the substrate-layer thereby maps into the Josephson-junction in the superconductive element.Type: GrantFiled: July 17, 1998Date of Patent: August 29, 2000Assignee: International Business Machines CorporartionInventors: Jochen Mannhart, Bernd Mayer
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Patent number: 6069369Abstract: Superconducting device include a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.Type: GrantFiled: October 24, 1997Date of Patent: May 30, 2000Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
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Patent number: 6023072Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.Type: GrantFiled: March 27, 1997Date of Patent: February 8, 2000Assignee: TRW Inc.Inventor: Arnold H. Silver
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Patent number: 6016433Abstract: Any oxide superconductor Josephson junction element having an oxide superconductor oriented in the c-axis direction with respect to a substrate, and a needle-like, a-axis (or b-axis) oriented oxide superconductor. Both sides of the needle-like, a-axis (or b-axis) oriented oxide superconductor are sandwiched between the c-axis oriented superconductors. The crystal boundary sections between the needle-like, a-axis (or b-axis) oriented oxide superconductor and each of the c-axis oriented superconductors form a weak link of the Josephson junction. The needle-like, a-axis (or b-axis) oriented oxide superconductor is grown such that the c-axis direction thereof is oriented in the (110) direction which is inclined at an angle of 45 degrees with respect to the (100) direction or (010) direction of the c-axis oriented superconductors.Type: GrantFiled: September 2, 1997Date of Patent: January 18, 2000Assignees: International Superconductivity Technology Center, Sharp Kabushiki KaishaInventors: Yuuji Mizuno, Yoshihiro Ishimaru, Youichi Enomoto
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Patent number: 5986280Abstract: A magnetic sensor comprises a SQUID made of a superconducting thin film. The superconducting thin film has a washer pattern and a terminal portion. The washer pattern has a non-square one hole pattern and a pair of slit patterns. The hole pattern has rectangle shape and includes the center of the washer pattern. The slit patterns having a straight shape growing parallel to the long side of the hole pattern, from the outside edge of the washer pattern toward the inside of the washer pattern. This outside edge of the washer pattern is the nearest to the hole pattern. There is an artificial grain boundary in the domain that spacing between the hole pattern and the slit pattern is narrowest. There is no artificial grain boundary in the other domain at all.Type: GrantFiled: September 3, 1997Date of Patent: November 16, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hirokazu Kugai
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Patent number: 5965900Abstract: The invention relates to a detector cell comprising tunnel-effect superconductive devices organized in a two-dimensional array and placed on a common substrate, each superconductive device comprising a tunnel-effect superconductive junction and being electrically connected to a bottom connection area and to a top connection area. The superconductive devices are separated from one another by trenches extending down to and including the bottom connection area and defining individual bottom connection areas disposed between each of said junctions and the substrate. At least one individual bottom connection area is electrically connected to at least one bottom connection area of an adjacent superconductive device by a localized bridge region.Type: GrantFiled: December 4, 1998Date of Patent: October 12, 1999Assignee: Agence Spatiale EuropeenneInventors: Anthony Peacock, Robert Venn
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Patent number: 5962865Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.Type: GrantFiled: April 11, 1997Date of Patent: October 5, 1999Assignee: TRW Inc.Inventors: George L. Kerber, Lynn A. Abelson, Raffi N. Elmadjian, Eric G. Ladizinsky
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Patent number: 5942765Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).Type: GrantFiled: November 20, 1997Date of Patent: August 24, 1999Assignee: International Superconductivity Technology CenterInventors: Kazunori Miyahara, Yoichi Enomoto, Shoji Tanaka
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Patent number: 5925892Abstract: A Josephson junction element having a substrate of a single crystal having a V-shaped notch formed in a surface of the substrate and a wiring pattern of an oxide superconductor formed on the surface of the substrate and crossing the notch to form a weak link region in the pattern at a position above the notch. The notch is defined by first and second walls joining with each other at the bottom of the notch and has first and second corners at which the first and second walls meet the surface of the substrate. The first and second corners have radii of curvature of 5-50 nm and 50-500 nm, respectively, provided that the difference in radius of curvature between the first and second corners is not smaller than 10 nm. The notch is formed by obliquely irradiating a predetermined portion of the substrate with a focused ion beam.Type: GrantFiled: June 12, 1997Date of Patent: July 20, 1999Assignees: International Superconductivity Technology Center, Sharp Kabushiki Kaisha, NEC CorporationInventors: Yuji Mizuno, Katsumi Suzuki, Youichi Enomoto
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Patent number: 5889289Abstract: High temperature superconductor composite thin film devices with easily moved Josephson vortices are described having high T.sub.c and good magnetic vortex properties. A preferred composite material was YBCO/CeO.sub.2 thin film on a MgO substrate. The superconductor composites were preferably formed by off-axis co-sputtering. A surprising recovery in properties was seen after plasma etching with oxygen.Type: GrantFiled: August 28, 1997Date of Patent: March 30, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Edward J. Cukauskas, Laura H. Allen
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Patent number: 5877122Abstract: An oxide superconductor element, produced by forming a damaged region on a substrate surface by the Ga.sup.+ focusing ion beam method and then depositing an oxide superconductor thin-film over it, is characterized in that a NdBa.sub.2 Cu.sub.3 O.sub.7-y (0.ltoreq.y.ltoreq.0.5) oxide superconductor is used in a tunnel junction having a tunneling barrier region with weak superconductivity.Type: GrantFiled: May 17, 1996Date of Patent: March 2, 1999Assignees: Fujitsu Ltd., Sharp Kabushiki Kaisha, NEC Corp., International Superconductivity Technology CenterInventors: Yoshihiro Ishimaru, Yuuji Mizuno, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
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Patent number: 5872368Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.Type: GrantFiled: November 30, 1995Date of Patent: February 16, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael Osofsky, Robert J. Soulen, Jr., Raymond Auyeung, James S. Horwitz, Doug B. Chrisey, Mark Johnson
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Patent number: 5869846Abstract: A superconducting junction device which is easily manufactured, multifunctional, and utilizes the superconducting Josephson effects is described. A first junction (Josephson junction) and a second junction (Josephson junction) are disposed o a substrate across a coupling portion of a dielectric. The first junction comprises a first upper electrode, a first barrier layer and a first lower electrode. The second junction comprises a second upper electrode, a second barrier layer and a second lower electrode. The first lower electrode and the second lower electrode are connected in series via a connecting electrode. A superconducting reflecting wall which is connected via the connecting electrode is provided around the two Josephson junctions including the coupling portion.Type: GrantFiled: March 22, 1996Date of Patent: February 9, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidetaka Higashino, Masahiro Sakai, Kentaro Setsune
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Patent number: 5863868Abstract: A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16.Type: GrantFiled: September 25, 1997Date of Patent: January 26, 1999Assignee: TRW Inc.Inventors: Hugo Wai-Kung Chan, Kenneth P. Daly, James M. Murduck
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Patent number: 5849669Abstract: A high critical temperature superconducting Josephson device includes a bicrystal substrate formed of a first single crystal substrate and a second single crystal substrate, with end faces of the first and second single crystal substrates having different crystal orientations and being joined to each other. A first superconducting electrode formed of a first film of a high critical temperature superconductor material is located on the first single crystal substrate, whereas a second superconducting electrode formed of a second film of a high critical temperature superconductor material is located on the second single crystal substrate. A bridge is formed of a third film of a high critical temperature superconductor material and located on the bicrystal substrate across a joint between said first and said second single crystal substrates.Type: GrantFiled: May 30, 1996Date of Patent: December 15, 1998Assignee: Oki Electric Industry Co., Ltd.Inventor: Zhongmin Wen
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Patent number: 5831279Abstract: A device with weak links (Josephson junctions) in a superconducting film has two single crystals connected through an interconnecting arrangement that may have one or more sublayers. At least two grain boundaries or at least one barrier are/is formed in the substrate.Type: GrantFiled: May 3, 1995Date of Patent: November 3, 1998Assignee: Telefonktiebolaget LM EricssonInventors: Erland Wikborg, Evgeni Stepantsov, Zdravko Ivanov, Tord Claeson
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Patent number: 5821556Abstract: A superconductive junction (10) comprises a first track (22) of YBa.sub.2 Cu.sub.3 O.sub.7 surmounted by a second track (28) also of YBa.sub.2 Cu.sub.3 O.sub.7. An interconnect (26) in the form of a superconductive mesa electrically connects the first track to the second track and acts as a microbridge. When cooled below a critical temperature, the junction (10) shows Josephson-like behaviour. A non-superconductive layer (24) of PrBa.sub.2 Cu.sub.3 O.sub.7 separates the first track and the second track, with the interconnect extending through the PrBa.sub.2 Cu.sub.3 O.sub.7 layer in the form of an island. The junction (10) is fabricated by electron beam evaporation, optical lithography, and ion beam milling.Type: GrantFiled: September 23, 1996Date of Patent: October 13, 1998Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern IrelandInventors: Nigel Gordon Chew, Simon Wray Goodyear, Richard George Humphreys, Julian Simon Satchell
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Patent number: 5821557Abstract: A Josephson junction includes a substrate, a first superconducting layer, a second superconducting layer transversely overlaid on the first layer with an insulating layer interposed therebetween, the insulating layer is an oxide or a nitride of the superconducting material, and the insulating layer including a low oxygen- or nitrogen-concentrated area in contact with each of the first and second layers. A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.Type: GrantFiled: July 8, 1996Date of Patent: October 13, 1998Assignee: Shimadzu CorporationInventors: Shinji Nagamachi, Masahiro Ueda, Kei Shinada, Mitsuyoshi Yoshii
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Patent number: 5757243Abstract: An effective high frequency oscillator is made of a plurality of Josephson devices. A high frequency converter as a high frequency circuit is made of the high frequency oscillator, nonlinear superconductor devices, and transmission line. Josephson devices are connected in parallel to make a superconductor module. Then superconductive modules are connected in series for high frequency via a phase locking circuit such as a thin film type capacitor to make the high frequency oscillator. Consequently, the high frequency oscillator is used as a local oscillator for a frequency converter. The high frequency system comprises a high frequency package housing a high frequency circuit, a cooling unit including a low temperature stage in thermal contact with the high frequency package, and a shielding case for housing the high frequency circuit and the low temperature stage. The high frequency system of the present invention provides a small-sized and power-saving high frequency circuit having operational stability.Type: GrantFiled: May 13, 1996Date of Patent: May 26, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Mizuno, Akira Enokihara, Hidetaka Higashino, Kentaro Setsune
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Patent number: RE37587Abstract: A SQUID includes a substrate and a superconducting current path of a patterned oxide superconductor material thin film formed on a surface of the substrate. A c-axis of an oxide crystal of the oxide superconductor material thin film is oriented in parallel to the surface of the substrate.Type: GrantFiled: March 6, 1998Date of Patent: March 19, 2002Assignee: Sumitomo Electric Industries Ltd.Inventors: Takashi Matsuura, Saburo Tanaka, Hideo Itozaki