All Contacts On Same Surface (e.g., Lateral Structure) Patents (Class 257/343)
  • Patent number: 10964861
    Abstract: The invention relates to a method for producing a plurality of optoelectronic semiconductor components, comprising the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: March 30, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Pindl, Thomas Schwarz, Frank Singer, Sandra Sobczyk
  • Patent number: 10950600
    Abstract: Provided are a semiconductor device capable of preventing erroneous operation and providing a field plate effect, and a method of manufacturing the semiconductor device. In a diode, a gate electrode, a p+ source region, and an n-type body region are electrically coupled to one another. A contact region is disposed between the n-type body region and the p+ source region in a first surface of a semiconductor substrate.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuji Ishii
  • Patent number: 10916648
    Abstract: An integrated circuit device includes a bulk substrate including a first conductivity type well and a second conductivity type drift region, a stack pattern disposed on the bulk substrate and including a buried insulation pattern on the second conductivity type drift region and a semiconductor body pattern on the buried insulation pattern, a gate insulation layer on an upper surface of the first conductivity type well and on a sidewall and an upper surface of the stack pattern, and a gate electrode on the gate insulation layer. The gate electrode includes a first gate portion opposite to the first conductivity type well with the gate insulation layer therebetween and a second gate portion opposite to the second conductivity type drift region with the gate insulation layer and the stack pattern therebetween.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-young Kim, Aliaksei Ivaniukovich, Hui-chul Shin, Mi-jin Han
  • Patent number: 10910493
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first body region disposed in a substrate and having a first conductivity type, a second body region disposed on the first body region and having the first conductivity type and a portion protruding in a channel length direction, a source region disposed in the second body region and having a second conductivity type, a drain region spaced apart from the protruding portion of the second body region in the channel length direction and having the second conductivity type, a well region configured to electrically connect the protruding portion of the second body region and the drain region and having the second conductivity type, and a gate structure disposed on the protruding portion of the second body region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 2, 2021
    Assignee: DB HITEK CO., LTD.
    Inventor: Choul Joo Ko
  • Patent number: 10903340
    Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Budong You, Hui Yu, Meng Wang, Yicheng Du, Chuan Peng, Xianguo Huang
  • Patent number: 10840371
    Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
  • Patent number: 10833185
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 10, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wen-Chia Liao, Ying-Chen Liu, Chen-Ting Chiang
  • Patent number: 10790388
    Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Koshimizu, Komaki Inoue, Hideki Niwayama
  • Patent number: 10770396
    Abstract: A semiconductor structure includes a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer having a protruding portion that is higher than the epitaxial layer, and a diffusion barrier layer disposed on sidewalls of the conductive feature.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 8, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Fang-Ming Lee, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 10749079
    Abstract: An LED module 101 is provided with an LED chip 200 that includes a sub-mount substrate 210 made of Si and a semiconductor layer 220 laminated on the sub-mount substrate 210. The module also includes white resin 280 that does not transmit light from the semiconductor layer 220 and that covers at least part of a side of the sub-mount substrate 210, where the side is connected to the surface on which the semiconductor layer 220 is laminated. These arrangements enhance the brightness of the LED module 101.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 18, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Masahiko Kobayakawa
  • Patent number: 10707345
    Abstract: An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm2, a gate charge (Qg) of about 1.9-2.0 nC/mm2, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventor: David Snyder
  • Patent number: 10686104
    Abstract: The invention relates to a method for producing a plurality of optoelectronic semiconductor components, comprising the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 16, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Markus Pindl, Thomas Schwarz, Frank Singer, Sandra Sobczyk
  • Patent number: 10680072
    Abstract: The reliability of resistive field plate part-containing semiconductor device is improved. In peripheral region of semiconductor chip, the outer circumference end of internal circulation wire is separated from outer circumference end of first conductor pattern of resistive field plate part toward element region. Inner circumference end of external circulation wire is separated from inner circumference end of second conductor pattern of resistive field plate part toward outer circumference of the chip. First conductor pattern of resistive field plate part is partially extended to over thin insulation film to form first lead-out part, and internal circulation wire and first lead-out part of first conductor pattern are electrically coupled via first coupling hole.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS COPORATION
    Inventor: Sho Nakanishi
  • Patent number: 10672903
    Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP USA, INC.
    Inventors: Xin Lin, Saumitra Raj Mehrotra, Ronghua Zhu
  • Patent number: 10672703
    Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Hernan Rueda, Humayun Kabir
  • Patent number: 10636896
    Abstract: A method for manufacturing the semiconductor structure, including: providing a substrate including a first doping region, wherein a field oxide film is disposed on a top surface of the first doping region, a first pattern layer is disposed on a top surface of the field oxide film, and the first pattern layer exposes a portion of the top surface of the field oxide film; etching the field oxide film with the first pattern layer as a mask until a top surface of the substrate is exposed; forming a second doping region in the first doping region with the first pattern layer and the field oxide film as a mask; and forming a plurality of gate structures on a portion of a top surface of the second doping region, a spacer of the field oxide film and a portion of the top surface of the field oxide film.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Xianzhou Liu
  • Patent number: 10629475
    Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 10615199
    Abstract: An imaging device according to the present disclosure includes: a photoelectric converter that generates signal charge; a semiconductor substrate including a first semiconductor layer containing an impurity of a first conductivity type and an impurity of a second conductivity type; and a first transistor including a first impurity region of the second conductivity type in the first semiconductor layer. The first semiconductor layer includes: a charge accumulation region of the second conductivity type, for accumulating the signal charge; and a blocking structure between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of the first conductivity type, a third impurity region of the second conductivity type, and a fourth impurity region of the first conductivity type, which are arranged in that order in a direction from the first impurity region toward the charge accumulation region, at the surface of the first semiconductor layer.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 7, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Hirase, Yoshinori Takami, Yoshihiro Sato
  • Patent number: 10566198
    Abstract: A first dose of first dopants is introduced into a semiconductor body having a first surface. A thickness of the semiconductor body is increased by forming a first semiconductor layer on the first surface of the semiconductor body. While forming the first semiconductor layer a final dose of doping in the first semiconductor layer is predominantly set by introducing at least 20% of the first dopants from the semiconductor body into the first semiconductor layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: February 18, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Johannes Baumgartl, Helmut Oefner
  • Patent number: 10529810
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 7, 2020
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Patent number: 10510776
    Abstract: A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Jiann-Tyng Tzeng, Chih-Liang Chen, Chew-Yuen Young, Sing-Kai Huang, Ching-Fang Huang
  • Patent number: 10510748
    Abstract: A transistor includes a first doping well, a second doping well, a first doping area, a second doping area, a gate layer, and at least one compensation capacitor. The first doping well and the second doping well are formed in a structure layer. The first doping area and the second doping area are formed in the first doping well and have a first conductivity type, the second doping well has a second conductivity type, and the first doping area is used for transmitting the signal. The at least one compensation capacitor is used for adjusting a voltage drop of a parasitic junction capacitor between the first doping area and the first doping well, a voltage drop of a parasitic junction capacitor between the first doping well and the second doping well, or a voltage drop of a parasitic junction capacitor between the second doping well and the structure layer.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 17, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tsung-Han Lee, Chang-Yi Chen
  • Patent number: 10504984
    Abstract: A light emitting circuit and a driving method thereof, an electronic device, a double-gate thin film transistor and a manufacture method thereof are provided. The light emitting circuit includes a double-gate thin film transistor and a light emitting component, the double-gate thin film transistor includes a first gate electrode, a second gate electrode, a first electrode and a second electrode, and where only both the first gate electrode and the second gate electrode receive turn-on signals simultaneously, the double-gate thin film transistor is turned on to drive the light emitting component.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Pengfei Gu
  • Patent number: 10374077
    Abstract: A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 6, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Yong Keon Choi
  • Patent number: 10347621
    Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 9, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Sunglyong Kim, David LaFonteese, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 10340339
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. The substrate includes a first region, a second region and a third region. An isolation structure is formed on the substrate in the first and the second region. A removing process is performed to remove the isolation structure in the first region, so as to form a first opening exposing a top surface of the substrate. A gate structure is formed on the substrate, covering a part of the substrate in the first region and a part of the isolation structure in the second region. A first doped region of a first conductive type is formed at one side of the gate structure in the first region, and a second doped region of the first conductive type is formed in the substrate in the third region.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 2, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Chin-Han Pan, Yao-Feng Huang
  • Patent number: 10340334
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 10332942
    Abstract: An OLED touch display device includes a first electrode layer, a second electrode layer facing the first electrode layer, a light-emitting layer between the first electrode layer and the second electrode, and a third electrode layer on a side of the first electrode layer. The first electrode layer functions as a cathode of the light-emitting layer, and the second electrode layer functions as an anode of the light-emitting layer. The first electrode layer and the third electrode layer cooperatively form a capacitive force sensing element. The first electrode layer also functions as touch sensing electrode.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 25, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Patent number: 10290579
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 10236350
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
  • Patent number: 10217853
    Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chen-Wei Pan
  • Patent number: 10186576
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 10164100
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10121878
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10074644
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 11, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul Kim, Hee Baeg An, In Chul Jung, Jung Hwan Lee, Kyung Ho Lee
  • Patent number: 10002960
    Abstract: Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: June 19, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 9978867
    Abstract: A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee
  • Patent number: 9929689
    Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 27, 2018
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Nagasato
  • Patent number: 9923059
    Abstract: In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 20, 2018
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 9905428
    Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew D Strachan, Alexei Sadovnikov, Christopher Boguslaw Kocon
  • Patent number: 9847293
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 9837541
    Abstract: A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Wei Chang, Chun-Hsiung Wang, Chih-Wei Chen
  • Patent number: 9837386
    Abstract: A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 5, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
  • Patent number: 9825021
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Patent number: 9805476
    Abstract: A pixel of a distance sensor includes a photosensor that generates photocharges corresponding to light incident in a first direction. The photosensor includes a plurality of first layers having a cross-sectional area increasing along the first direction after a first depth and at least one transfer gate which receives a transfer control signal for transferring the photocharges to a floating diffusion node. A strong electric field is formed in the direction in which the photocharges move horizontally or vertically in the pixel, thereby accelerating the photocharges, allowing for increased sensitivity and demodulation contrast.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric Fossum, Tae Yon Lee
  • Patent number: 9799763
    Abstract: One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has first and second surfaces. A first insulator is formed over a first portion of the channel, and which has a first thickness. A second insulator is formed over the second portion of the channel, and which has a second thickness that is less than the first thickness. A first gate is formed over the first insulator. A second gate is formed over the second insulator. A body region of a second conductivity type is formed above or in the substrate.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Dev Alok Girdhar
  • Patent number: 9799770
    Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Yao Lin, Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 9780084
    Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.
    Type: Grant
    Filed: February 28, 2016
    Date of Patent: October 3, 2017
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Yonghai Hu, Meng Dai, Zhongyu Lin, Guangyang Wang
  • Patent number: 9768292
    Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 19, 2017
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shu Zhang, Guangtao Han, Guipeng Sun
  • Patent number: 9768283
    Abstract: A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 19, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho, Yu-Lung Chin