All Contacts On Same Surface (e.g., Lateral Structure) Patents (Class 257/343)
  • Patent number: 10374077
    Abstract: A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 6, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Yong Keon Choi
  • Patent number: 10347621
    Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 9, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Sunglyong Kim, David LaFonteese, Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 10340339
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. The substrate includes a first region, a second region and a third region. An isolation structure is formed on the substrate in the first and the second region. A removing process is performed to remove the isolation structure in the first region, so as to form a first opening exposing a top surface of the substrate. A gate structure is formed on the substrate, covering a part of the substrate in the first region and a part of the isolation structure in the second region. A first doped region of a first conductive type is formed at one side of the gate structure in the first region, and a second doped region of the first conductive type is formed in the substrate in the third region.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 2, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Chin-Han Pan, Yao-Feng Huang
  • Patent number: 10340334
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 10332942
    Abstract: An OLED touch display device includes a first electrode layer, a second electrode layer facing the first electrode layer, a light-emitting layer between the first electrode layer and the second electrode, and a third electrode layer on a side of the first electrode layer. The first electrode layer functions as a cathode of the light-emitting layer, and the second electrode layer functions as an anode of the light-emitting layer. The first electrode layer and the third electrode layer cooperatively form a capacitive force sensing element. The first electrode layer also functions as touch sensing electrode.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 25, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Patent number: 10290579
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 10236350
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
  • Patent number: 10217853
    Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chen-Wei Pan
  • Patent number: 10186576
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 10164100
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10121878
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10074644
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 11, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul Kim, Hee Baeg An, In Chul Jung, Jung Hwan Lee, Kyung Ho Lee
  • Patent number: 10002960
    Abstract: Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: June 19, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 9978867
    Abstract: A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee
  • Patent number: 9929689
    Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 27, 2018
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Nagasato
  • Patent number: 9923059
    Abstract: In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 20, 2018
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 9905428
    Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew D Strachan, Alexei Sadovnikov, Christopher Boguslaw Kocon
  • Patent number: 9847293
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 9837541
    Abstract: A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Wei Chang, Chun-Hsiung Wang, Chih-Wei Chen
  • Patent number: 9837386
    Abstract: A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 5, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
  • Patent number: 9825021
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Tien-Hao Tang
  • Patent number: 9805476
    Abstract: A pixel of a distance sensor includes a photosensor that generates photocharges corresponding to light incident in a first direction. The photosensor includes a plurality of first layers having a cross-sectional area increasing along the first direction after a first depth and at least one transfer gate which receives a transfer control signal for transferring the photocharges to a floating diffusion node. A strong electric field is formed in the direction in which the photocharges move horizontally or vertically in the pixel, thereby accelerating the photocharges, allowing for increased sensitivity and demodulation contrast.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric Fossum, Tae Yon Lee
  • Patent number: 9799763
    Abstract: One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has first and second surfaces. A first insulator is formed over a first portion of the channel, and which has a first thickness. A second insulator is formed over the second portion of the channel, and which has a second thickness that is less than the first thickness. A first gate is formed over the first insulator. A second gate is formed over the second insulator. A body region of a second conductivity type is formed above or in the substrate.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Dev Alok Girdhar
  • Patent number: 9799770
    Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Yao Lin, Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 9780084
    Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.
    Type: Grant
    Filed: February 28, 2016
    Date of Patent: October 3, 2017
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Yonghai Hu, Meng Dai, Zhongyu Lin, Guangyang Wang
  • Patent number: 9768292
    Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 19, 2017
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shu Zhang, Guangtao Han, Guipeng Sun
  • Patent number: 9768283
    Abstract: A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 19, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho, Yu-Lung Chin
  • Patent number: 9761494
    Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A bulk pick-up region adjoins the source feature in the at least one lightly doped region. The bulk pick-up region has a second conductivity type.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
  • Patent number: 9762890
    Abstract: A pixel of a distance sensor includes a photosensor that generates photocharges corresponding to light incident in a first direction. The photosensor includes a plurality of first layers having a cross-sectional area increasing along the first direction after a first depth and at least one transfer gate which receives a transfer control signal for transferring the photocharges to a floating diffusion node. A strong electric field is formed in the direction in which the photocharges move horizontally or vertically in the pixel, thereby accelerating the photocharges, allowing for increased sensitivity and demodulation contrast.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eric Fossum, Tae Yon Lee
  • Patent number: 9761714
    Abstract: A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Mori
  • Patent number: 9755052
    Abstract: A semiconductor power device disposed on a semiconductor substrate comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 5, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yongping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
  • Patent number: 9704987
    Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and in direct contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: July 11, 2017
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 9698259
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a well region. The semiconductor device includes a source region in the well region. The semiconductor device includes a drain region. The semiconductor device includes a gate electrode that is between the source and drain regions, when viewed in a plan view. Moreover, the semiconductor device includes first and second patterns, in the source region, that are spaced apart from each other when viewed in the plan view.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JaeHyun Jung
  • Patent number: 9660020
    Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Lu, Purakh Raj Verma, Dongli Wang, Deyan Chen
  • Patent number: 9607839
    Abstract: An N-type Lateral Diffused Metal-Oxide-Semiconductor (NLDMOS) transistor is provided. The NLDMOS transistor comprises a P-type substrate; and a semiconductor layer having a deep N-type well region formed on the P-type substrate. Further, the NLDMOS transistor also includes at least a P-type body region and an N-type drift region formed in the deep N-type well region; and an N-type heavily doped drain region formed in the N-type drift region. Further, the NLDMOS transistor includes a P-type doped reverse type region formed below the N-type drift region in the deep N-type well region, being physically connected with the first P-type body region, and preventing carriers from escaping between the N-type source region and external devices.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Zheyun Feng, Ming Wang, Qiancheng Ma, Huifang Song, Yong Cheng
  • Patent number: 9601411
    Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Shih-Fen Huang, Hsin-Li Cheng, Felix Ying-Kit Tsui
  • Patent number: 9553188
    Abstract: A high-voltage semiconductor device includes a semiconductor substrate, a gate structure, a drain, an insulation structure, and a plurality of conductive structures. The insulation structure is disposed in the semiconductor substrate and disposed between the gate structure and the drain. The insulation structure includes a plurality of insulation units disposed separately from one another. Each of the conductive structures is embedded in one of the insulation units.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lingzi Li, Zhaobing Li, Hui Lu, Zhang Hu Sun
  • Patent number: 9520470
    Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 13, 2016
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 9513518
    Abstract: A display device includes a first substrate, a gate driver on array (GOA) circuit, a plurality of peripheral conductive wires, a second substrate, a sealant and a semi-transparent pattern. The GOA circuit is disposed in a gate driver region, and includes a plurality of thin film transistor devices. The peripheral conductive wires are disposed in a peripheral region of the first substrate, and the peripheral conductive wires are electrically connected to the GOA circuit. The sealant is disposed in at least a portion of the peripheral region and a portion of the gate driver region, and the sealant overlaps at least a portion of the peripheral conductive wires and a portion of the thin film transistor devices of the GOA circuit in a vertical direction. The semi-transparent pattern is disposed on the second substrate, and a transmittance of the semi-transparent pattern is between 10% and 80%.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 6, 2016
    Assignee: AU OPTRONICS CORP.
    Inventors: Chia-Fang Chen, Yu-Hao Chen, Po-Yuan Shen
  • Patent number: 9496283
    Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 15, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John Hongguang Zhang
  • Patent number: 9490360
    Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 8, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Shing Chen, Ming-Hui Chang, Wei-Ting Wu, Ying-Chou Lai, Horng-Nan Chern, Chorng-Lih Young, Chin-Sheng Yang
  • Patent number: 9490322
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Hongning Yang, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9478640
    Abstract: An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: October 25, 2016
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Wensheng Qian
  • Patent number: 9466601
    Abstract: A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
  • Patent number: 9461117
    Abstract: A high voltage semiconductor device includes a well region of a first conductive type formed at a surface portion of a substrate, a gate electrode disposed on the well region, a source region formed at a surface portion of the well region adjacent to the gate electrode, a drain region formed at a surface portion of the well region adjacent to the gate electrode, and a drift region of a second conductive type disposed under the drain region.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 4, 2016
    Assignee: DONGBU HITEK CO., LTD.
    Inventor: Choul Joo Ko
  • Patent number: 9461046
    Abstract: A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 ?m wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/?m.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 4, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd
  • Patent number: 9450076
    Abstract: An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: September 20, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Salvatore Cascino, Leonardo Gervasi, Antonello Santangelo
  • Patent number: 9425304
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 23, 2016
    Assignee: Vishay-Siliconix
    Inventors: Wenjie Zhang, Madhur Bobde, Qufei Chen, Kyle Terrill
  • Patent number: 9419130
    Abstract: A semiconductor device in a semiconductor substrate includes a first drain region and a second drain region, a first drift zone and a second drift zone, at least two gate electrodes in the semiconductor substrate, and a channel region between the gate electrodes. The first drift zone is arranged between the channel region and the first drain region, and the second drift zone is arranged between the channel region and the second drain region. The second drain region is disposed on a side of the gate electrode, the side of the gate electrode being remote from the side of the first drain region.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Franz Hirler, Peter Irsigler
  • Patent number: 9379236
    Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: June 28, 2016
    Assignee: Broadcom Corporation
    Inventors: Shom Surendran Ponoth, Akira Ito