With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) Patents (Class 257/344)
  • Patent number: 11489054
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 11424256
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 11367788
    Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 21, 2022
    Assignee: MEDIATEK INC.
    Inventors: Jing-Chyi Liao, Ching-Chung Ko, Zheng Zeng
  • Patent number: 11322363
    Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Borrel, Magali Gregoire
  • Patent number: 11315887
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ying-Cheng Chuang, Chung-Lin Huang
  • Patent number: 11289541
    Abstract: A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 29, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Frederick Chen
  • Patent number: 11270886
    Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: March 8, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Patent number: 11264237
    Abstract: A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yun Chin, Tzu-Hsiang Hsu, Yen-Ru Lee, Chii-Horng Li
  • Patent number: 11239082
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 11222978
    Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yul Lee, Yuri Masuoka
  • Patent number: 11217492
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 11211492
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin
  • Patent number: 11145554
    Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 11145545
    Abstract: A semiconductor device includes a semiconductor substrate, a source or drain layer provided in the semiconductor substrate, a gate insulation layer provided on a surface of the semiconductor substrate, and a gate electrode that is provided on the gate insulation layer. The semiconductor device further includes a first contact that is provided on the source or drain layer, the first contact including a stacked body in which a plurality of first layers and one or more second layers are alternately stacked, and a second contact that faces at least one of a side surface and an upper surface of the first contact disposed on the source or drain layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Minoru Oda
  • Patent number: 11133183
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11049954
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 11031305
    Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz Gardner, Seung Hoon Sung
  • Patent number: 11018259
    Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lo, Tung-Wen Cheng, Chia-Ling Chan, Mu-Tsang Lin
  • Patent number: 11004732
    Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
  • Patent number: 10991800
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10991688
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10923595
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1?x?yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin
  • Patent number: 10916652
    Abstract: Asymmetric transistors and related methods and devices are disclosed. A transistor includes a semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile with a halo region on a source side. The transistor also includes a source including a lightly doped drain (LDD) on the source side, and a drain having a doping profile of charge carriers of a second type graded in a decreasing manner toward the source side. A method includes applying a large angle tilt implant drain (LATID) process to a drain side, a halo implant process to a source side, and applying an LDD process on the source side. A memory device includes an asymmetric transistor. A computing device includes an asymmetric transistor.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventor: Yen Chun Lee
  • Patent number: 10916476
    Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Yoo, Sang-deok Kwon, Yuri Masuoka
  • Patent number: 10910261
    Abstract: A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoungdeog Choi, JungWoo Seo, Sangyeon Han, Hyun-Woo Chung, Hongrae Kim, Yoosang Hwang
  • Patent number: 10854506
    Abstract: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Sheng Liang, Wei-Chih Kao, Hsin-Che Chiang, Kuo-Hua Pan
  • Patent number: 10847630
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner, and gate spacer layers on side surfaces of the gate structure, the gate spacer layers having an upper surface at a lower height level than an upper surface of the gate electrode layer.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok Han Bae, Jin Wook Kim
  • Patent number: 10840254
    Abstract: A memory includes a plurality of levels of word lines interleaved with a plurality of levels of channel lines. Horizontal data storage levels are disposed between the plurality of levels of word lines and the plurality of levels of channel lines, the data storage levels including respective arrays of data storage regions in cross points of word lines and channel lines in adjacent levels of the plurality of levels of word lines and the plurality of levels of channel lines. Respective arrays of holes outside of the cross points are disposed in the channel line and word line levels. The channel lines and word lines have sides defined by undercut etch perimeters, along with air gaps or voids between the channel lines and word lines in each level. The word lines, bit lines and data storage nodes in each layer are vertically self-aligned.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 10833090
    Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Ming Chang, Kuo-Hsiu Hsu
  • Patent number: 10804105
    Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 13, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dae Sub Jung, De Yan Chen, Guang Li Yang
  • Patent number: 10784781
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
  • Patent number: 10763370
    Abstract: A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 1, 2020
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Patent number: 10720513
    Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10707080
    Abstract: A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first resist patterns on the hard mask layer; performing a tilt-angle ion implant process to form a first doped area and a second doped area in the hard mask layer between adjacent first resist patterns; removing the first resist patterns; coating a directed self-assembly (DSA) material layer onto the hard mask layer; performing a self-assembling process of the DSA material layer to form repeatedly arranged block copolymer patterns in the DSA material layer; removing undesired portions from the DSA material layer to form second patterns on the hard mask layer; transferring the second patterns to the hard mask layer to form third patterns; and etching the target layer through the third patterns.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 10700106
    Abstract: A display device including a semiconductor element is provided.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 10685886
    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
  • Patent number: 10672912
    Abstract: The disclosure provides an N-type thin film transistor, including a poly-silicon layer, a gate layer, a source and a drain. The poly-silicon layer includes a channel region, a source region and a drain region at two side of the channel region. The gate layer is on the channel region, a projection of the gate layer on the poly-silicon layer partially overlaps the source region and the drain region, and a thickness of the gate layer on the source region and the drain region are smaller than a thickness of the gate layer on the channel region. The source region and the drain region both include a heavily-doping region and a lightly-doping region connected to the heavily-doping region, the source and the drain are respectively on the heavily-doping region of the source region and the drain, and respectively electrically connects to the heavily-doping region of the source region and the drain.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 2, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 10658488
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Yen Tsai, Da-Yuan Lee
  • Patent number: 10629435
    Abstract: Methods and apparatuses for patterning substrates using a positive patterning scheme are described herein. Methods involve receiving a substrate having a patterned core material, depositing a doped spacer material conformally over the patterned core material, selectively etching the core material to the doped spacer material to form a spacer mask, and using the spacer mask to etch a target layer on the substrate. Spacer materials may be doped using any of boron, gallium, phosphorus, arsenic, aluminum, and hafnium. Embodiments are suitable for applications in multiple patterning applications.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 21, 2020
    Assignee: Lam Research Corporation
    Inventors: Shankar Swaminathan, Richard Phillips, Adrien LaVoie
  • Patent number: 10608011
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Patent number: 10580863
    Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
  • Patent number: 10573749
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Ziwei Fang, Shiu-Ko JangJian, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Patent number: 10541323
    Abstract: High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, gate-connected field plate, and source-connected field plate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 21, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Timothy E. Boles, Douglas Carlson, Anthony Kaleta
  • Patent number: 10535758
    Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang
  • Patent number: 10535512
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate. The method also includes forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process. The atomic layer deposition process includes alternately and sequentially introducing a first silicon-containing precursor gas and a second silicon-containing precursor gas over the sidewall of the gate stack to form the sealing layer. The second silicon-containing precursor gas has a different atomic concentration of carbon than that of the first silicon-containing precursor gas. The method further includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Yao Tu, Yu-Yun Peng
  • Patent number: 10515955
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10510542
    Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung
  • Patent number: 10497806
    Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 3, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10490459
    Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 10490651
    Abstract: A method for fabricating a semiconductor structure is disclosed. The method includes providing a substrate and forming a plurality of fin structures on the substrate. Each fin structure includes a first side and a second side opposite to the first side. The method further includes forming a first doped region containing first doping ions in a portion of the substrate on the first side of each gate structure, and forming a second doped region containing second doping ions in a portion of the substrate on the second side of each gate structure. The ion concentration of the second doping ions in the second doped region is smaller than the ion concentration of the first doping ions in the first doped region, and the atomic weight of the second doping ions is smaller than the atomic weight of the first doping ions.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 26, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Chao Zhang, Ru Ling Zhou, Qing Yong Zhang