With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) Patents (Class 257/344)
  • Patent number: 10355077
    Abstract: In an ESD protection element configured to protect a semiconductor device, a first N-type low concentration diffusion layer is formed, as an offset layer for easing electric field concentration, under a LOCOS oxide film formed at each end of the gate electrode, and a second N-type low concentration diffusion layer and a third low concentration diffusion layer are formed under an N-type high concentration diffusion layer on the drain side to set the point of breakdown at a level deep inside a substrate from a surface of the substrate. The hold voltage is thus raised to a voltage equal to or higher than the operating voltage and a noise can be relieved without increasing the element size of the ESD protection element even when the noise having a large amount of positive electric charge is applied to a Vdd supply terminal.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 16, 2019
    Assignee: ABLIC INC.
    Inventor: Yukimasa Minami
  • Patent number: 10347739
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10312379
    Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Ching-Chung Yang
  • Patent number: 10304963
    Abstract: The embodiments of the present disclosure provide a polysilicon thin film transistor and manufacturing method thereof, an array substrate, and a display panel. The method for manufacturing a polysilicon thin film transistor comprises: forming, on a substrate, a gate, a source and a drain, and an active layer. Forming the active layer comprises: forming a polysilicon layer on the substrate, which comprises a channel region and extension regions; performing ion injection process in the extension regions to form lightly-doped regions close to the channel region and a source region and a drain region; prior to or following the formation of the lightly-doped regions, employing halo ion injection process to form halo regions at the positions of the channel region which are close to the lightly-doped regions.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 28, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaoyong Lu, Dong Li, Zheng Liu, Shuai Zhang, Liang Sun, Chunping Long
  • Patent number: 10304960
    Abstract: An integrated circuit device includes a first wiring, a second wiring, a semiconductor member that is connected between the first and second wirings, an electrode, and an insulating film that is provided between the semiconductor member and the electrode. The semiconductor member includes a first semiconductor portion of a first conductivity type connected to the first wiring, a second semiconductor portion of the first conductivity type, a third semiconductor portion of the first conductivity type, a fourth semiconductor portion of the first conductivity type, a fifth semiconductor portion of a second conductivity type, and a sixth semiconductor portion of the first conductivity type in this order. A first edge of the electrode on a side of the first wiring overlaps the second, third, or fourth semiconductor portions.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masakazu Goto
  • Patent number: 10290718
    Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
  • Patent number: 10276569
    Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
  • Patent number: 10204931
    Abstract: The present disclosure provides an electrically conductive structure and a manufacturing method thereof, an array substrate, and a display device. The manufacturing method of the electrically conductive structure including: forming stacked layers of electrically conductive films on a substrate; performing patterning process to the layers of electrically conductive films to form an electrically conductive structure with a preset pattern, an edge of the electrically conductive structure being a step-shaped structure.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Na Zhao
  • Patent number: 10199459
    Abstract: A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 5, 2019
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
  • Patent number: 10181522
    Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
  • Patent number: 10176990
    Abstract: A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 10157743
    Abstract: A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first resist patterns on the hard mask layer; performing a tilt-angle ion implant process to form a first doped area and a second doped area in the hard mask layer between adjacent first resist patterns; removing the first resist patterns; coating a directed self-assembly (DSA) material layer onto the hard mask layer; performing a self-assembling process of the DSA material layer to form repeatedly arranged block copolymer patterns in the DSA material layer; removing undesired portions from the DSA material layer to form second patterns on the hard mask layer; transferring the second patterns to the hard mask layer to form third patterns; and etching the target layer through the third patterns.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 10147787
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one source drain structure, an insulating layer, and a gate. The semiconductor substrate includes a base portion and at least one fin. The fin is disposed on the base portion. The source drain structure is disposed on at least one sidewall of the fin. The insulating layer is disposed between the base portion and the source drain structure to isolate the base portion and the source drain structure. The gate is disposed on the fin.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10147817
    Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Ying Pang, Nabil G. Mistkawi
  • Patent number: 10128373
    Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 13, 2018
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10121897
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Patent number: 10079302
    Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10062757
    Abstract: A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 28, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabrizio Fausto Renzo Toia, Claudio Contiero, Elisabetta Pizzi, Simone Dario Mariani
  • Patent number: 10050118
    Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Ryan Ryoung-han Kim, Chanro Park, William James Taylor, Jr., John A. Iacoponi
  • Patent number: 10038010
    Abstract: A semiconductor device may include: a substrate; a first well region formed on the substrate; a second well region formed on the substrate, the first well region and the second well region extending in a first direction and being adjacent to each other in a second direction crossing the first direction; a first active region formed in the first well region; a first power region formed in the first well region, the first active region and the first power region being separate from each other in the first direction; a second active region array formed in the second well region; a second power region formed in the second well region, the second active region array and the second power region being separate from each other in the first direction; and a first dummy active region formed in the first well region between the first active region and the first power region, the first dummy active region being separate from the first active region and the first power region in the first direction.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yong-hoon Kim
  • Patent number: 10032524
    Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jagdish Sabde, Sagar Magia, Jayavel Pachamuthu
  • Patent number: 10026658
    Abstract: Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, De-Fang Chen, Huan-Just Lin
  • Patent number: 10014411
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9997601
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiuan-Jeng Lin, Shyh-Wei Cheng, Che-Jung Chu
  • Patent number: 9966467
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 8, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 9966430
    Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 8, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Xin Miao, Ruilong Xie, Tenko Yamashita
  • Patent number: 9953708
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 9954057
    Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-Jae Song, Jae-Hyun Yoo, In-Hack Lee, Seong-Hun Jang, Myoung-Kyu Park, Young-Mok Kim
  • Patent number: 9954118
    Abstract: The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 24, 2018
    Assignee: AMS AG
    Inventor: Martin Knaipp
  • Patent number: 9929267
    Abstract: The present disclosure provides N-type fin field-effect transistors and fabrication methods thereof. A method for fabricating an N-type fin field-effect transistor includes providing a semiconductor substrate; forming at least one fin having a first side surface and a second side surface over the semiconductor substrate; forming a gate structure crossing over the fin over the semiconductor substrate; performing an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure; performing a thermal annealing process to cause doping ions to diffuse to the other one of the first side surface and the second side surface of the fin; and forming a source region and a drain region on the fin at the two sides of the gate structure, respectively.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 27, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yong Li
  • Patent number: 9923076
    Abstract: A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multilayer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Elliot John Smith
  • Patent number: 9882016
    Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
  • Patent number: 9876109
    Abstract: Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. A transistor gate extends downwardly into the second semiconductor material. Gate dielectric material is along sidewalls and a bottom of the transistor gate. Source/drain regions are along the sidewalls of the transistor gate, and the gate dielectric material is between the source/drain regions and the transistor gate. A channel region extends between the source/drain regions and is under the bottom of the transistor gate. At least some of the channel region is within the strained region.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Satoru Mayuzumi, Mark Fischer
  • Patent number: 9859289
    Abstract: A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: January 2, 2018
    Inventors: Fethi Dhaoui, John McCollum
  • Patent number: 9853162
    Abstract: In accordance with some embodiments of the disclosed subject of matter, a TFT array substrate, a method for fabricating the TFT array substrate, and a display panel that comprises the TFT array substrate are provided. In some embodiments, the TFT array substrate comprises: a substrate; an active layer comprising a first region, a source region, a drain region, and a second region between the drain region and the first region; a gate electrode above the first insulating layer, wherein the gate electrode substantially covers the first region; and a first light-shielding layer that overlaps with the first region and substantially covers the second region.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 26, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lei Shi
  • Patent number: 9853116
    Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong
  • Patent number: 9810959
    Abstract: A liquid crystal display including first and second substrates with a liquid crystal layer therebetween. The first substrate includes a semiconductor layer electrode electrically connected to a first source line on a first side of a position where the semiconductor layer intersects with a gate wire in a second direction, and to a contact portion on a second side of the position. A contact portion is arranged nearer the gate line than the main pixel electrode. The main pixel electrode extends from the contact portion in the second direction and is located nearer the second side than the first side. The contact portion is connected to the main pixel electrode only by a first portion of the main pixel electrode.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Katsuhiro Hoshina, Tetsuya Iizuka, Masato Nakamura, Kazuya Daishi
  • Patent number: 9806189
    Abstract: A semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type body region in a semiconductor layer surface portion, a first conductivity type source region in a body region surface, apart from a peripheral edge of the body region, a first conductivity type drain region in the semiconductor layer surface portion apart from the body region, a gate electrode opposing the body region across a gate insulating film between the source and drain regions, an insulating layer on the semiconductor layer, resin on the insulating layer, a source electrode in the insulating layer, electrically connected to the source region, a drain electrode in the insulating layer, electrically connected to the drain region, and conductive shielding in the insulating layer, overlapping in a plan view from a direction normal to a semiconductor layer surface, the drain region and the gate electrode, and covering a region between them.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 31, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Kumano
  • Patent number: 9793335
    Abstract: There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Mai Osada
  • Patent number: 9780034
    Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 3, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Kota Funayama, Ryoichi Ehara, Youko Furihata, Zhenyu Lu, Tong Zhang, Tadashi Nakamura
  • Patent number: 9780209
    Abstract: A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fen Chen, Bang-Yu Huang, Chui-Ya Peng
  • Patent number: 9748290
    Abstract: Embodiments of mechanisms for forming an image sensor device structure are provided. The image sensor device structure includes a substrate and a transfer transistor formed on the substrate. The image sensor device structure also includes a floating node formed in the substrate and a photosensitive element formed in the substrate. The transfer transistor is formed between the floating node and the photosensitive element, and the photosensitive element includes a first doping region with a lateral doping gradient.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Tzo-Hung Luo
  • Patent number: 9741818
    Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chueh-Yang Liu, Yu-Ying Lin, I-cheng Hu, Tien-I Wu, Yu-Shu Lin, Yu-Ren Wang
  • Patent number: 9711622
    Abstract: Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 18, 2017
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Jun Tanaka, Nobuya Seko, Kenichi Hayashi
  • Patent number: 9660054
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Patent number: 9653561
    Abstract: A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 16, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 9620649
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 11, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Hai-Biao Yao, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin, Zhi-Biao Zhou
  • Patent number: 9608109
    Abstract: An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell finger including a source and a second nwell on an opposite side of the pwell finger includes a drain. A gate stack is over a channel region the pwell finger between the source and drain. A field dielectric layer is on the surface layer defining a first active area including a first active area boundary along the width direction (WD boundary) that has the channel region therein. A first p-type layer is outside the first active area at least a first minimum distance from the WD boundary and a second p-type layer is doped less and is closer to the WD boundary than the first minimum distance.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Shaoping Tang
  • Patent number: 9608011
    Abstract: The present invention discloses a thin-film transistor and a fabricating method thereof, an array substrate and a display apparatus. An active layer in the thin-film transistor comprises a first active layer and a second active layer which are stacked; wherein, an orthographic projection of the first active layer on the substrate covers orthographic projections of the source electrode, the drain electrode as well as a gap located between the source electrode and the drain electrode on the substrate, and covers an orthographic projection of the gate electrode on the substrate; the second active layer is located at the gap between the source electrode and the drain electrode, and an orthographic projection of the second active layer on the substrate is located in a region where the orthographic projection of the gate electrode on the substrate is located.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: March 28, 2017
    Assignees: Boe Technology Group Co., Ltd., Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Ying Zhang, Xin Li, Hong Zhu, Hongjun Yu
  • Patent number: 9607980
    Abstract: The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jhih-Ming Wang, Li-Cih Wang, Tien-Hao Tang