With Means (e.g., A Buried Channel Stop Layer) To Prevent Leakage Current Along The Interface Of The Semiconductor Layer And The Insulating Substrate Patents (Class 257/349)
  • Patent number: 10269810
    Abstract: A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10204981
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Ching-Ling Lin
  • Patent number: 10170068
    Abstract: The embodiments of the present disclosure provide a gate driving circuit, an array substrate, a display panel and a driving method. The gate driving circuit comprises: at least a Gate driver on Array (GOA) unit GOAn and a GOA unit GOAn+m, an output terminal of GOAn being connected to an input terminal of GOAn+m, an output terminal of GOAn+m is connected to a reset terminal of GOAn; and an electrical leakage compensation module having two input terminals connected to output terminals of GOAn and GOAn+m, respectively, a control terminal connected to a signal line, and an output terminal connected to a Pull-Up (PU) node of GOAn+m, and configured to compensate for a voltage at the PU node of GOAn+m in response to receipt of the electrical leakage compensation signal VLHB.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Qiujie Su, Feng Li
  • Patent number: 10164022
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • Patent number: 10121861
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Seiyon Kim, Kelin Kuhn, Willy Rachmady, Jack Kavalieros
  • Patent number: 10109630
    Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chia-Fu Hsu
  • Patent number: 9935196
    Abstract: The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 3, 2018
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 9886905
    Abstract: A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kouhei Toyotaka
  • Patent number: 9882600
    Abstract: According to various embodiments, a switching device may include: an antenna terminal; a switch including a first switch terminal and a second switch terminal, the first switch terminal coupled to the antenna terminal, the switch including at least one transistor at least one of over or in a silicon region including an oxygen impurity concentration of smaller than about 3×1017 atoms per cm3; and a transceiver terminal coupled to the second switch terminal, wherein the transceiver terminal is at least one of configured to provide a signal received via the antenna terminal or configured to receive a signal to be transmitted via the antenna terminal.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 30, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christian Kuehn, Martin Bartels, Henning Feick, Dirk Offenberg, Anton Steltenpohl, Hans Taddiken, Ines Uhlig
  • Patent number: 9842838
    Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phillip F. Chapman, David S. Collins, Steven H. Voldman
  • Patent number: 9842735
    Abstract: A method of manufacturing a low temperature polycrystalline silicon thin film and a thin film transistor, a thin film transistor, a display panel and a display device are provided. The method includes: forming an amorphous silicon thin film (01) on a substrate (1); forming a pattern of a silicon oxide thin film (02) covering the amorphous silicon thin film (01), a thickness of the silicon oxide thin film (02) located at a preset region being larger than that of the silicon oxide thin film (02) located at other regions; and irradiating the silicon oxide thin film (02) by using excimer laser to allow the amorphous silicon thin film (01) forming an initial polycrystalline silicon thin film (04), the initial polycrystalline silicon thin film (04) located at the preset region being a target low temperature polycrystalline silicon thin film (05). The polycrystalline silicon thin film has more uniform crystal size.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: December 12, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yanan Niu, Chao Liu, Zengsheng He, Lei Chen, Yujun Zhang
  • Patent number: 9755046
    Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 5, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang
  • Patent number: 9698059
    Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chia-Fu Hsu
  • Patent number: 9653476
    Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 16, 2017
    Assignees: Commissariate a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9627480
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony I. Chou, Judson R. Holt, Arvind Kumar, Henry K. Utomo
  • Patent number: 9608150
    Abstract: A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 28, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Tetsunobu Kochi
  • Patent number: 9583617
    Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang
  • Patent number: 9564443
    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim, Reinaldo A. Vega
  • Patent number: 9543297
    Abstract: A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Konstantin G. Korablev, Shesh Mani Pandey, Manfred Eller
  • Patent number: 9496373
    Abstract: A design structure for a semiconductor circuit structure, readable by a machine used in design, manufacture, or simulation of an integrated circuit, involves a fin, a footer, and an inlay. The fin includes a fin perimeter and a fin base with an overhang area. A footer with a first top side, a footer perimeter, and a plurality of footer perimeter sides can be made of an insulator layer also having an open area with a second top side outside the footer perimeter. The footer perimeter is within the fin perimeter, the fin base resting on the first top side with the overhang area being on the fin base between the fin perimeter and the footer perimeter. The design structure further involves an etch-resistant inlay, with an inlay thickness, on the second top side and touching the overhang area and each of the plurality of footer perimeter sides.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9478671
    Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Alexandru Romanescu
  • Patent number: 9431537
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Patent number: 9385234
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • Patent number: 9337302
    Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 10, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9324739
    Abstract: In one embodiment of the invention, a high electron mobility thin film transistor with a plurality of gate insulating layers and a metal oxynitride active channel layer is provided for forming a backplane circuit for pixel switching in an electronic display, to reduce unwanted ON state series resistance in the metal oxynitride active channel layer and minimize unwanted power dissipation in the backplane circuit. Another embodiment of the invention provides a high electron mobility thin film transistor structure with a plurality of metal oxynitride active channel layers and a gate insulating layer for forming a backplane circuit for pixel switching in an electronic display, to reduce unwanted ON state series resistance in the metal oxynitride active channel layer and to minimize unwanted power dissipation in the backplane circuit.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 26, 2016
    Inventors: Ishiang Shih, Andy Shih, Cindy Qiu, Julia Qiu, Yi-Chi Shih, Chunong Qiu
  • Patent number: 9293581
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9293466
    Abstract: A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9293562
    Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Yamamoto, Hiromi Sasaki, Tomotake Morita, Masashige Moritoki
  • Patent number: 9281215
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., LTD.
    Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
  • Patent number: 9263555
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches that define a fin, performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of the fin, removing the first, second and third layers of epi semiconductor material from above an upper surface of the fin so as to thereby expose the fin, selectively removing the fin relative to the first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of the first, second and third layers of epi semiconductor material, and forming a gate structure around a portion of at least one of the fin structures comprised of the first, second and third layers of epi semiconductor material.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Behtash Behin-Aein, Mehdi Salmani-Jelodar
  • Patent number: 9252385
    Abstract: An organic light emitting device includes a base substrate defining an active area and a pad area that surrounds the active area, an organic light emitting layer formed on the active area, a first protective layer formed to cover the active area, where the organic light emitting layer is formed, and the pad area, a second protective layer formed to cover the first protective layer, and a dam formed between the first protective layer and the second protective layer, wherein the dam is located at a boundary between the active area and the pad area and includes a groove that is positioned separate from an outer portion of the active area.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: February 2, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Tae-Kyung Kim, Byoung Chul Kim, Myoung Soo Lee
  • Patent number: 9177968
    Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 3, 2015
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventor: Paul A. Nygaard
  • Patent number: 9159824
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9142418
    Abstract: A method of forming double and/or multiple numbers of fins of a FinFET device using a Si/SiGe selective epitaxial growth process and the resulting device are provided. Embodiments include forming a Si pillar in an oxide layer, the Si pillar having a bottom portion and a top portion; removing the top portion of the Si pillar; forming a SiGe pillar on the bottom portion of the Si pillar; reducing the SiGe pillar; forming a first set of Si fins on opposite sides of the reduced SiGe pillar; removing the SiGe pillar; replacing the Si fins with SiGe fins; reducing the SiGe fins; forming a second set of Si fins on opposite sides of the SiGe fins; and removing the SiGe fins.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: InSoo Jung, Wonwoo Kim
  • Patent number: 9105718
    Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus, Robert R. Robison
  • Patent number: 9082646
    Abstract: A semiconductor device includes a source region disposed with a semiconductor substrate; a drain region disposed with the semiconductor substrate; a gate region disposed onto the semiconductor substrate and positioned between the source region and the drain region. The semiconductor device also includes a gate oxide region disposed onto the semiconductor substrate in contact with the gate region and a well region implanted onto the semiconductor substrate and under the gate region and the gate oxide region. The gate oxide region has a lower outer edge portion that contacts the well region.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: July 14, 2015
    Assignee: Broadcom Corporation
    Inventor: Akira Ito
  • Patent number: 9076813
    Abstract: A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: July 7, 2015
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven Brueck, Daniel Feezell
  • Publication number: 20150145046
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.
    Type: Application
    Filed: May 22, 2012
    Publication date: May 28, 2015
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 9034717
    Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jean-Pierre Colinge
  • Publication number: 20150129966
    Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Patent number: 9024392
    Abstract: Some embodiments relate to an integrated circuit including fin field effect transistors (FinFETs) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another. A gate dielectric layer is disposed over the first and second active fin regions. First and second gate electrodes are disposed over the first and second active fin regions, respectively. The first and second gate electrodes are also disposed over the gate dielectric layer. The first and second gate electrodes are electrically coupled together and are electrically separated from the first and second active fin regions by the gate dielectric layer. The first gate electrode is made of a first metal having a first workfunction, and the second gate electrode is made of a second metal having a second workfunction that differs from the first workfunction.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9024389
    Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, Balasubramanian S. Haran, David V. Horak
  • Patent number: 9006045
    Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Patent number: 8999792
    Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Stanley Seungchul Song
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8981480
    Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Lim, Satoru Yamada, Sung-Duk Hong
  • Patent number: 8975635
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8975697
    Abstract: A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8969155
    Abstract: Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Kern Rim
  • Patent number: 8969966
    Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 3, 2015
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc., Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu, Maud Vinet