Single Crystal Semiconductor Layer On Insulating Substrate (soi) Patents (Class 257/347)
  • Patent number: 11069679
    Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Chen Zhang, Kangguo Cheng, Tenko Yamashita, Joshua M. Rubin
  • Patent number: 11062908
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Patent number: 11063155
    Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kohei Ebisuno, Sungjun Kim, Donghyun Son, Jaesoo Jung, Sunghoon Moon, Jingoo Jung
  • Patent number: 11063559
    Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • Patent number: 11049861
    Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru, Donald W. Nelson, Stephen M. Cea
  • Patent number: 11043593
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Patent number: 11038044
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11037831
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 11038057
    Abstract: A semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; a first fin-shaped semiconductor layer spaced apart from the substrate, wherein the first semiconductor layer extends along a curved longitudinal extending direction; and a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 15, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11038028
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Patent number: 11037783
    Abstract: In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Yang Li, Lain-Jong Li, Chih-Piao Chuu
  • Patent number: 11037905
    Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin and a second VTFET stacked on the first VTFET. The second VTFET includes a second semiconductor fin that is separate and distinct from the first semiconductor fin. At least one insulating layer is disposed on a top surface of the first VTFET. The second VTFET is disposed on the at least one insulating layer. The method includes forming a first vertical VTFET on a first substrate and bonding a second substrate to and on top of the first VTFET. A second VTFET is formed on the second substrate.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Gen Tsutsui, Tenko Yamashita
  • Patent number: 11031470
    Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 8, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Patent number: 11031355
    Abstract: A semiconductor device includes an insulating substrate having a main surface, a semiconductor element, a case member, and a sealing resin as a sealing material. The case member includes a recess that is continuous with a connection portion of the case member connected to the insulating substrate, and that faces the internal region. The recess includes a facing surface as an inner wall portion facing the main surface of the insulating substrate. A distance from the main surface of the insulating substrate to the facing surface as the inner wall portion is greater than a distance from the main surface to an upper surface of the semiconductor element.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 8, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Kaji, Kozo Harada
  • Patent number: 11031248
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 8, 2021
    Assignee: Tessera, Inc.
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 11031296
    Abstract: A method for forming a semiconductor device includes flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure, and, after flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Albert M. Chu
  • Patent number: 11031320
    Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
  • Patent number: 11024711
    Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Patent number: 11024725
    Abstract: In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a metal oxide film over the second insulating film; a gate electrode over the metal oxide film; and a third insulating film over the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 1, 2021
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Junichi Koezuka, Tomonori Nakayama, Motoki Nakashima
  • Patent number: 11011643
    Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 11011515
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Patent number: 11004933
    Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 11, 2021
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11004937
    Abstract: A semiconductor device includes a substrate, a gate structure, a source/drain region, a contact opening, an etching stop layer, an interlayer dielectric layer, and a first contact structure. The substrate includes a buried insulation layer, a semiconductor layer, and an isolation structure. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The isolation structure and the source/drain region are disposed in the semiconductor layer. The contact opening penetrates at least a part of the substrate. The etching stop layer is disposed on the gate structure, the source/drain region, a sidewall of the contact opening, and a bottom of the contact opening. The interlayer dielectric layer is disposed on the etching stop layer. The first contact structure penetrates the interlayer dielectric layer and the etching stop layer in the contact opening.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Jian Shi
  • Patent number: 10998429
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 10998237
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 10998234
    Abstract: Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan Basker, Nicolas Loubet, Balasubramanian Pranatharthiharan
  • Patent number: 10991723
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order; a first transistor provided on the semiconductor layer; a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and an element separation film provided between the first transistor and the second transistor, in which the element separation film includes a second insulating layer embedded in an opening that penetrates the semiconductor layer and the first insulating layer and reaches an inside of the silicon substrate layer, and a portion of the second insulating layer constitutes a gate insulating film of the second transistor.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: April 27, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tetsuo Gocho
  • Patent number: 10985276
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Meng Zhao
  • Patent number: 10983117
    Abstract: Disclosed are devices that comprise a protein, such as an antibody, placed into electronic communication with a semiconductor material, such as a carbon nanotube. The devices are useful in assessing the presence or concentration of analytes contacted to the devices, including the presence of markers for prostate cancer and Lyme disease.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 20, 2021
    Assignees: The Trustees of the University of Pennsylvania, The Institute For Cancer Research
    Inventors: Alan T. Johnson, Jr., Mitchell Lerner, Matthew W. Robinson, Tatiana Pazina, Dustin Brisson, Jennifer Dailey, Brett R. Goldsmith
  • Patent number: 10985279
    Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu, Zhenxing Bi
  • Patent number: 10978500
    Abstract: Embodiments of the present invention provide a flexible base substrate and a fabrication method thereof. The flexible base substrate comprises: a first flexible film layer, having an upper surface and a lower surface opposite to each other, wherein a plurality of concave parts are arranged on the lower surface of the first flexible film layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 13, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tao Gao, Xue Mao, Weifeng Zhou
  • Patent number: 10978487
    Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: April 13, 2021
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Pascal Fonteneau
  • Patent number: 10978557
    Abstract: A method includes forming a plurality of first semiconductor layers and second semiconductor layers in an alternate manner over a substrate; etching the first semiconductor layers and second semiconductor layers to form a fin structure, in which the fin structure comprises a plurality of first nanowires and second nanowires alternately arranged, the first nanowires have respective remaining portions of the first semiconductor layers, and the second nanowires have respective remaining portions of second semiconductor layers; forming a dummy gate over the fin structure; forming a plurality of gate spacers on opposite sidewalls of the dummy gate, respectively; replacing the dummy gate with a metal gate; removing first portions of the second nanowires exposed by the metal gate and metal gate and the gate spacers suspended; and forming an epitaxy layer wrapping around the first portions of the first nanowires, in which opposite sidewalls of the epitaxy layer have zig-zag contour.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Christopher Holland, Mark Van Dal, Georgios Vellianitis, Blandine Duriez, Gerben Doornbos
  • Patent number: 10978340
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 13, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Patent number: 10971588
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10971633
    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10971493
    Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kam-Tou Sio, Shang-Wei Fang, Jiann-Tyng Tzeng, Chew-Yuen Young
  • Patent number: 10969637
    Abstract: An electrostatic discharge circuit and a display panel are provided. The electrostatic discharge circuit comprises a first discharge unit and an associated discharge unit. An output terminal of the first discharge unit is coupled to a common terminal. A control terminal of the first discharge unit is coupled to a high voltage terminal or a low voltage terminal. An input terminal of the first discharge unit is coupled to an electrostatic input terminal. An input terminal of the associated discharge unit is coupled to the electrostatic input terminal, and an output terminal of the associated discharge unit is coupled to the control terminal of the first discharge unit.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 6, 2021
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Yu-Jen Chen
  • Patent number: 10964773
    Abstract: An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 30, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Ryoichi Nozawa
  • Patent number: 10964910
    Abstract: A display device includes a substrate including a plastic layer, a barrier layer, and a display area in which an image is displayed. The display device further includes a light-emitting diode disposed in the display area, a planarization layer, and a pixel definition layer. The planarization layer and the pixel definition layer overlap the light-emitting diode. The display device further includes a thin film encapsulation layer disposed on the pixel definition layer. The thin film encapsulation layer includes at least one inorganic layer. The display device further includes an opening disposed in the display area and penetrating the substrate. The opening includes a protruded portion and a depressed portion, and the barrier layer overlaps at least one of the pixel definition layer and the planarization layer at the protruded portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Ho Yoon, Woo Yong Sung, Won Je Cho, Won Woo Choi
  • Patent number: 10964767
    Abstract: This organic-EL display apparatus comprises an organic-EL display panel including: a substrate that is provided with pixel drive circuits to drive respective pixels arranged in a matrix along each of a first direction and a second direction, and organic light-emitting elements being provided to each of the pixels and connected to any one of the pixel drive circuits. The organic-EL display panel comprises a signal output circuit to supply a signal to each of the pixel drive circuits arranged in a line along the first direction or the second direction. The signal output circuit includes thin film transistors and is formed around a display region on a surface of the substrate. The thin film transistors include a semiconductor layer including a region to be a channel between a source electrode and a drain electrode. The semiconductor layer is formed of amorphous silicon.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 30, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yukiya Nishioka, Katsuhiko Kishimoto
  • Patent number: 10964718
    Abstract: Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions. Further, the plurality of second memory portions is removed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 10957607
    Abstract: A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Sheng Yun, You-Ru Lin, Shao-Ming Yu
  • Patent number: 10957765
    Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pan-Jae Park, Jae-Seok Yang, Young-Hun Kim, Hae-Wang Lee, Kwan-Young Chun
  • Patent number: 10957230
    Abstract: A shift register unit provided according to embodiments of the present disclosure includes an input circuit, a pull-up circuit, a control circuit, and a first discharge circuit. The pull-up circuit is configured to control an output of the signal output terminal. The control circuit is configured to control a potential of the second node based on a second voltage signal of the second voltage terminal and a potential of the first node. The first discharge circuit is configured to control, after being turned on under the control of the potential of the second node, the first node and the signal output terminal by using the third voltage terminal, and discharging a pixel unit, the first node and the signal output terminal, the pixel unit being connected to the signal output terminal.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 23, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Liangliang Zheng, Tingting Jin, Tao Yu
  • Patent number: 10950726
    Abstract: The semiconductor device according to the present technology includes a hollow region or an insulating region. The hollow region or the insulating region is provided under a channel that is formed between a source of a first semiconductor type and a drain of the first semiconductor type in a body region of a second semiconductor type in a transistor, the body region being provided between the source and the drain.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 16, 2021
    Assignee: SONY CORPORATION
    Inventor: Yuki Yanagisawa
  • Patent number: 10948513
    Abstract: An electronic device is based on a single crystal semiconductor substrate. A cavity is formed in the semiconductor substrate. Further, a movably suspended mass is defined by one or more trenches extending from one side of the semiconductor substrate to the cavity. A first electrode layer is provided on the suspended mass. Further, a cover layer covering the suspended mass is provided. The cover layer includes a second electrode layer arranged opposite to the first electrode layer and spaced therefrom by a gap.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Patent number: 10950581
    Abstract: A 3D semiconductor device including: a first level including a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon, where the second layer includes radio frequency type circuits.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 16, 2021
    Assignee: MONOLITHIC 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10950727
    Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 16, 2021
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, R. Stockton Gaines
  • Patent number: 10950434
    Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin