Single Crystal Semiconductor Layer On Insulating Substrate (soi) Patents (Class 257/347)
  • Patent number: 10734525
    Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Julien Frougier, Christopher M. Prindle, Nigel G. Cave
  • Patent number: 10734516
    Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 4, 2020
    Assignee: NXP USA, Inc.
    Inventor: Venkata Naga Koushik Malladi
  • Patent number: 10734613
    Abstract: A method for manufacturing an organic light-emitting diode substrate is provided and includes: on a base substrate with a black matrix pattern, forming a conductive layer covering the black matrix pattern and a photoresist pattern that partially stacks on the conductive layer, through one patterning process by taking the black matrix pattern as a mask plate; and removing the photoresist pattern and portions of the conductive layer that stack on the photoresist pattern, thereby forming a patterned conductive layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 4, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xing Zhang, Wei Li, Quanhu Li, Xuehuan Feng, Jianye Zhang
  • Patent number: 10734040
    Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 4, 2020
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Ajay Bhatia
  • Patent number: 10734477
    Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
  • Patent number: 10734502
    Abstract: Semiconductor devices include semiconductor layers and a gate stack formed on and around the semiconductor layers. Spacers are formed between vertically adjacent semiconductor layers, each spacer having a first spacer layer and a second spacer layer. The first spacer layer is positioned between the gate stack and the second spacer layer. The second spacer layer of each spacer has a trapezoidal cross-section.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
  • Patent number: 10727133
    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
  • Patent number: 10727324
    Abstract: A bipolar junction transistor includes: an emitter region; a base region; and a collector region, wherein each of the emitter region, the base region, and the collector region comprises fin-shaped structures. Preferably, the emitter region, the base region, and the collector region are disposed along a first direction and the fin-shaped structures are disposed along a second direction, in which the first direction is orthogonal to the second direction.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Cho, Chen-Wei Pan
  • Patent number: 10727447
    Abstract: An electroluminescent display device includes a thin film transistor disposed on a substrate; a passivation layer disposed on the thin film transistor; a plurality of metallic patterns disposed to be spaced apart from each other on the passivation layer; a reflective electrode disposed conforming to the shapes of the plurality of metallic patterns and a top surface of the passivation layer and including a plurality of protruding portions; an overcoat layer disposed on the passivation layer and the reflective electrode and including an opening configured to expose a top surface of each of the plurality of protruding portions; a first electrode disposed on the reflective electrode and the overcoat layer and electrically connected to the reflective electrode; an light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 28, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Yong-Hoon Choi, Won-Hoe Koo, Woo-Ram Youn
  • Patent number: 10727426
    Abstract: A thin film transistor includes a gate electrode, an organic semiconductor overlapping the gate electrode, an insulator between the gate electrode and the organic semiconductor, and a source electrode and a drain electrode electrically connected to the organic semiconductor, respectively. The organic semiconductor is capable of being applied by a solution process, the insulator includes an inorganic insulating layer having a surface facing the organic semiconductor, and the surface includes a coating with a polysiloxane having an acrylic terminal group.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ajeong Choi, Eun Kyung Lee, Joo Young Kim, Jeong Il Park, Youngjun Yun
  • Patent number: 10726237
    Abstract: A fingerprint identification sensor, a method of fabricating the same, and a fingerprint identification apparatus are provided. The fingerprint identification sensor includes: a substrate; a plurality of sensor units on the substrate, each of the sensor units comprising a thin film transistor and a photosensitive device; wherein the thin film transistor comprises a source and a drain, an active layer and a gate, the source and the drain being arranged substantially in a direction perpendicular to the substrate surface.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: July 28, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiwei Liang, Yingwei Liu, Wenqian Luo, Qingzhao Liu, Muxin Di
  • Patent number: 10720090
    Abstract: A display apparatus includes a display panel including a display area and a non-display area, in which an image is displayed in the display area and a peripheral area is disposed adjacent to the display area in the non-display area. The display panel includes a plurality of gate lines extending in a first direction, a plurality of data lines extending a second direction which crosses the first direction, and a plurality of unit pixels which are electrically connected to each of the gate lines and the data lines. A gate driver generates a clock signal, and a gate signal generator receives the clock signal and outputs a generated gate signal to the gate line. A clock line transmits the clock signal to the gate signal generator, and a flexible film disposed adjacent to the gate signal generator in the first direction is connected to the display panel in the peripheral area. At least a portion of the clock line is formed on the flexible film.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang-Soo Lee, Byoungsun Na
  • Patent number: 10720502
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Patent number: 10714471
    Abstract: A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manfacturing International (Shanghai) Corporation
    Inventors: Yihua Shen, Yunchu Yu, Jian Pan, Fenghua Fu
  • Patent number: 10714409
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion, disposed on the substrate; a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and a radiating metal sheet, disposed on the dielectric portion; wherein the active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 14, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10714564
    Abstract: An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Ryoichi Nozawa
  • Patent number: 10707334
    Abstract: A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Yee-Chia Yeo
  • Patent number: 10707352
    Abstract: Certain aspects of the present disclosure generally relate to a transistor having an implant region for reducing a net doping concentration below an edge of a gate region of the transistor. One example transistor generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the first semiconductor region being between and having a different doping type than the second semiconductor region and the third semiconductor region. In certain aspects, the transistor also includes a gate dielectric layer disposed above the first semiconductor region, a non-insulative region disposed above the gate dielectric layer, and an implant region disposed above the second semiconductor region, the implant region having a different doping type than the second semiconductor region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Ranadeep Dutta
  • Patent number: 10700173
    Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang, Ruilong Xie, Haiting Wang, Hui Zhan, Yong Jun Shi
  • Patent number: 10692987
    Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang
  • Patent number: 10692716
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10693016
    Abstract: A display apparatus includes a thin film transistor on a first base substrate, the thin film transistor including a gate electrode disposed on the first base substrate, an active pattern disposed on the first base substrate and including a semiconductor layer including of amorphous silicon and an ohmic contact layer which is on the semiconductor layer, a drain electrode disposed on the ohmic contact layer and having a first thickness, and a source electrode disposed on the ohmic contact layer and having a second thickness which is greater than the first thickness.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Pil Soon Hong, Hyunyoung Jung, Chulwon Park, Gwui-Hyun Park, Jeongmin Park
  • Patent number: 10692974
    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier, Jaya P. Gupta
  • Patent number: 10685882
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 10673430
    Abstract: Provided is a semiconductor device for radio frequency switch that includes an SOI substrate and a gate electrode. The SOI substrate includes a buried oxide film and a semiconductor layer on a carrier substrate. The gate electrode is provided on the semiconductor layer. The semiconductor layer includes a first area below the gate electrode and a second area other than the first area. A third area is provided in at least part of the second area. A fourth area is provided in at least part of the first area. The fourth area has a different thickness from a thickness of the third area.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 2, 2020
    Assignee: SONY CORPORATION
    Inventor: Atsushi Kuranouchi
  • Patent number: 10672646
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 10670474
    Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Kegler, Johannes Georg Laven, Hans-Joachim Schulze, Guenther Ruhl, Joachim Mahler
  • Patent number: 10672742
    Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang Wu, Chun-Fu Cheng, Chung-Cheng Wu, Yi-Han Wang, Chia-Wen Liu
  • Patent number: 10672795
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Patent number: 10665667
    Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anupam Dutta, John J. Ellis-Monaghan
  • Patent number: 10665697
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 10665698
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. The method includes forming a channel region comprising a channel region semiconductor material having a first energy band gap characteristic. A source region is formed communicatively coupled to the channel region. A drain region is formed communicatively coupled to the channel region. A gate region is formed communicatively coupled to the channel region. An enhanced band gap region is positioned substantially positioned at an interface between the channel region and the drain region. The enhanced band gap region includes an enhanced band gap region semiconductor material having a second band gap energy characteristic. The first energy band gap is less than the second energy band gap.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10658418
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface on one side thereof and a second surface on an opposite side thereof, and having an element therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at the one side of the first surface of the first semiconductor layer, an insulating layer disposed on the first surface of the first semiconductor layer, and a charge-attracting layer configured to attract electrical charges generated in the insulating layer when a predetermined voltage is supplied to the charge-attracting layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 19, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroki Kasai
  • Patent number: 10658259
    Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 19, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Patent number: 10658386
    Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: May 19, 2020
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Richard James Dowling, Hiroshi Yamada, Alain Duvallet, Ronald Eugene Reedy
  • Patent number: 10658491
    Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Ming-Ching Chang, Chan-Lon Yang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10658490
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10658509
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 10651285
    Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 12, 2020
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yingming Liu, Yu Bao, Haifeng Zhou, Jingxun Fang
  • Patent number: 10643995
    Abstract: A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Jayeol Goo, Sang Gil Kim
  • Patent number: 10644167
    Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 5, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu
  • Patent number: 10644129
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Patent number: 10643901
    Abstract: A field-effect transistor includes a gate electrode to apply a gate voltage, a source electrode and a drain electrode to take electric current out, a semiconductor layer disposed adjacent to the source electrode and the drain electrode, and a gate insulating layer disposed between the gate electrode and the semiconductor layer, wherein the gate insulating layer includes an oxide including silicon and one or two or more alkaline earth metal elements.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 5, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventors: Ryoichi Saotome, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Sadanori Arae, Minehide Kusayanagi
  • Patent number: 10629431
    Abstract: A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Juntao Li
  • Patent number: 10629527
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Patent number: 10629703
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10629528
    Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
  • Patent number: 10629532
    Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Josef S. Watts
  • Patent number: 10629705
    Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern includes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaybum Kim, Seryeong Kim, Junhyung Lim, Taesang Kim
  • Patent number: 10629621
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard