Single Crystal Semiconductor Layer On Insulating Substrate (soi) Patents (Class 257/347)
  • Patent number: 10354584
    Abstract: A display device is provided in which each subpixel includes a driving TFT, an organic light-emitting diode, and at least one switching TFT for driving the subpixel. At least one of the driving TFT and the switching TFT is formed as a double-gate TFT having a first gate node and a second gate node, and each subpixel comprises a compensation circuit that senses a threshold voltage of the double-gate TFT and applies the same to the first gate node or the second gate node of the double-gate TFT.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Namyong Gong, Sohee Choi
  • Patent number: 10355249
    Abstract: A manufacturing method of an organic EL display device according to an embodiment of the present invention includes: disposing a first organic substrate having flexibility on a glass substrate; disposing a barrier layer on the first organic substrate; disposing a second organic substrate having flexibility on the barrier layer such that a thickness of a terminal section area is thinner than a thickness of a pixel section area, or at least a part of the terminal section area is not covered; disposing a pixel control section on the terminal section area of the second organic substrate and a pixel generating section on the pixel section area, respectively; disposing a circuit section at least on the terminal section area, the circuit section having a thin film transistor, wherein the circuit section is formed directly on the second organic substrate.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 16, 2019
    Assignee: Japan Display Inc.
    Inventors: Hiroki Nakaie, Toshihiko Itoga
  • Patent number: 10347736
    Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Nexgen Power Systems, Inc.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 10347537
    Abstract: A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10345696
    Abstract: A photomask (2) for optical alignment and an optical alignment method. By aligning the tail ends of first light-transmission patterns (313) which form a first photomask figure (3), and aligning the front ends of second light-transmission patterns (413), which form a second photomask figure (4) in the photomask (2), the un-exposed or underexposed areas do not exist at the tail ends of first substrate units (11) and the front end of second substrate units (12) during the process of optical alignment, thereby the problem existed in the traditional optical alignment manufacture process, that the brightness of a display is not uniform due to existing unexposed or underexposed areas, is solved, meanwhile, the reduction of the distance between the first substrate units (11) and the second substrate units (12) on a substrate is facilitated, thereby the utilization rate of the substrate is improved.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 9, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Bing Han
  • Patent number: 10340366
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
  • Patent number: 10340191
    Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10340454
    Abstract: A display device includes a display panel and a first protective substrate positioned under the display panel and including a first sub-region and a second sub-region positioned at a side of the first sub-region. A thickness of the first protective substrate in the first sub-region is greater than a thickness of the first protective substrate in the second sub-region.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Geun Woo Yug
  • Patent number: 10340384
    Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ken Lin, Chun Te Li, Chih-Peng Hsu
  • Patent number: 10332951
    Abstract: A display device includes a plurality of pixels, wherein a first pixel of the plurality of pixels includes: a scan line extending in a first direction; a data line and a driving voltage line extending in a second direction crossing the first direction; a switching thin film transistor connected to the scan line and the data line; a driving thin film transistor connected to the switching thin film transistor; a first shielding layer overlapping the data line; and a second shielding layer overlapping the data line, the second shielding layer being spaced apart from the first shielding layer in the second direction such that the first shielding layer and the second shielding layer are spaced apart a predetermined distance apart from each other.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junwon Choi, Changsoo Pyon
  • Patent number: 10332880
    Abstract: Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET (Fin Field Effect Transistor) devices. For example, a semiconductor device includes a FinFET device and a vertical fin resistor device formed on a semiconductor substrate. The FinFET device includes a vertical semiconductor fin which includes a structural profile that is defined by dimensions of width W, height H, and length L. The vertical fin resistor device includes a vertical fin structure which is formed of a resistive material (e.g., polysilicon or amorphous silicon), and which has a structural profile that is defined by dimension of width W1, height H1, and length L1. The structural profiles of the vertical semiconductor fin of the FinFET device and the vertical fin structure of the vertical fin resistor device have at least one corresponding dimension that is substantially the same.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu
  • Patent number: 10332985
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 25, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Patent number: 10332870
    Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Jung-Ho Do, Woojin Rim, Jisu Yu, Jonghoon Jung
  • Patent number: 10325817
    Abstract: Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate, including a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region. The first and second semiconductor fins are formed of different types of semiconductor material, and are initially formed to have different widths and heights. A semiconductor fin trimming process is performed, which is selective to the semiconductor material of the second semiconductor fin, so that the fin trimming process results in the formation of semiconductor fins having substantially equal heights and equal widths across the device regions as a result of the fin trimming process. The semiconductor fins in different device regions are initially formed with non-uniform profiles (e.g., differential heights and widths) to compensate for micro-loading and etch rate variations during the fin trimming process.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10325811
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David P. Brunco, Wei Zhao, Haiting Wang
  • Patent number: 10326026
    Abstract: Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10326440
    Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventor: Venkata Naga Koushik Malladi
  • Patent number: 10326007
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt
  • Patent number: 10326017
    Abstract: In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • Patent number: 10326018
    Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a pair of the gate structures. A first capacitor is electrically coupled between the channel contact and the source terminal, and a second capacitor is electrically coupled between the channel contact and the drain terminal.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventor: Venkata Naga Koushik Malladi
  • Patent number: 10319642
    Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Ajey P. Jacob
  • Patent number: 10319833
    Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
  • Patent number: 10312375
    Abstract: A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 4, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Noriaki Ikeda, Makoto Nishizawa
  • Patent number: 10312160
    Abstract: A method of fabricating a transistor includes: forming an active device layer on a semiconductor substrate; patterning the active device layer to form fins; forming a first dielectric layer on an upper surface and sidewalls of the fins; forming a second dielectric layer on the first dielectric layer; forming openings through the first and second dielectric layers, exposing the underlying active device layer forming the fins; forming source/drain regions in the active device layer exposed through the respective openings; forming source/drain contacts on an upper surface of the source/drain regions; forming a second opening through the first and second dielectric layers, exposing the underlying active device layer adjacent to the source/drain regions; depositing a third dielectric layer in the second opening, on sidewalls and an upper surface of the fins; and forming a gate stack on the third dielectric layer.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10304945
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure. The method includes forming a hard mask layer over the gate structure. The hard mask layer has a first opening spaced apart from a first side of the gate structure by a first distance and a second opening spaced apart from a second side of the gate structure by a second distance that is different from the first distance. The method also includes removing the fin structure not covered by the hard mask layer. The method further includes forming a first source/drain feature in the fin structure and filling the first opening of the hard mask layer. The method further includes forming a second source/drain feature in the fin structure and filling the second opening of the hard mask layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Victor Chiang Liang, Chia-Chung Chen, Chi-Feng Huang, Shu-Fang Fu
  • Patent number: 10304722
    Abstract: The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 28, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Shawn George Thomas
  • Patent number: 10297662
    Abstract: The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom and sidewalls of the semiconductor island. The first dielectric isolation layer includes a first portion which is formed from a portion of the first semiconductor layer and extending along the bottom of the semiconductor island, and a second portion which is formed from a portion of the second semiconductor layer and extending along the sidewalls of the semiconductor island. The dielectrically isolated semiconductor devices needs no an SOI wafer and reduces manufacturing cost.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 21, 2019
    Assignees: HANGZHOU SILAN MICROELECTRONICS CO., LTD., HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Changjun Zhang, Feng Ji, Ping Wang, Zuyin Chen
  • Patent number: 10294100
    Abstract: A method for manufacturing a gas detector by a micro-electrical-mechanical systems (MEMS) process. The method includes providing a MEMS wafer including a plurality of mutually adjacent units; forming a gas sensing material layer on the MEMS wafer; bonding a structure reinforcing layer and the MEMS wafer through anode bonding; providing an adhesive tape; performing a cutting process to form a gas detection unit; and adhering the gas detection unit on a substrate by the adhesive tape to form a gas detector. The structure reinforcing layer is capable of enhancing the strength of a device and preventing edge collapsing, and hence enhancing the overall yield rate and reducing costs.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Carbon Nano Technology Corporation
    Inventors: Yu-Hsuan Liao, Fang-Song Tsai, Ya-Han Wu, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Patent number: 10297783
    Abstract: A display device includes a first inorganic insulating layer covering a display region; a first organic insulating layer on the first inorganic insulating layer; a second organic insulating layer covering the first organic insulating layer; and a second inorganic insulating layer covering the second organic insulating layer, the second inorganic insulating layer including a region in contact with the first inorganic insulating layer. An end of the first organic insulating layer and an end of the second organic insulating layer each have a tapering shape, the first organic insulating layer has a first side surface and a first bottom surface, the second organic insulating layer has a second side surface and a second bottom surface, and an angle made by the second side surface and the second bottom surface is smaller than an angle made by the first side surface and the first bottom surface.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Japan Display Inc.
    Inventor: Yusuke Sasaki
  • Patent number: 10290682
    Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 14, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 10290805
    Abstract: A method for manufacturing an emitter comprises providing a semiconductor substrate having a main surface, the semiconductor substrate comprising a cavity adjacent to the main surface. A portion of the semiconductor substrate arranged between the cavity and the main surface of the semiconductor substrate forms a support structure. The method comprises arranging an emitting element at the support structure, the emitting element being configured to emit a thermal radiation of the emitter, wherein the cavity provides a reduction of a thermal coupling between the emitting element and the semiconductor substrate.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: May 14, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Steffen Bieselt, Heiko Froehlich, Thoralf Kautzsch, Maik Stegemann, Mirko Vogt
  • Patent number: 10288962
    Abstract: A display device includes a first substrate and a pixel electrode on the first substrate. A thickness of the pixel electrode is about 40 nanometers (nm) or less.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yeo Geon Yoon, Jun Ho Song, Byeong Jae Ahn, Sung Ho Kang
  • Patent number: 10283592
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10284200
    Abstract: A process for fabricating a semiconductor die involves providing a semiconductor substrate, forming a first field-effect transistor on the semiconductor substrate, the first field-effect transistor having a source, a drain, a gate, and a body, forming a coupling path that couples the body of the first field-effect transistor to the gate of the first field-effect transistor, the coupling path including a diode, and forming an adjustable impedance network coupled between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 7, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ambarish Roy, Guillaume Alexandre Blin
  • Patent number: 10283642
    Abstract: Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, El Mehdi Bazizi, Luca Pirro
  • Patent number: 10283401
    Abstract: A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: May 7, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Osamu Ishikawa, Masahiro Kato
  • Patent number: 10276371
    Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 30, 2019
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
  • Patent number: 10276568
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Patent number: 10276692
    Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: You-Hua Chou
  • Patent number: 10276560
    Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bingwu Liu, Hui Zang
  • Patent number: 10269937
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Patent number: 10266963
    Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: April 23, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Neeraj Nepal, Virginia D. Wheeler, Charles R. Eddy, Jr., Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Rachael L. Myers-Ward, Sandra C. Hangarter
  • Patent number: 10269787
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Ming-Ching Chang, Shu-Yuan Ku, Ryan Chia-Jen Chen
  • Patent number: 10269974
    Abstract: The present invention discloses a method of manufacturing array substrate, comprising: A) defining a heavily doped region and a lightly doped region of a source electrode of an N-channel area, and a heavily doped region and a lightly doped region of a drain electrode of the N-channel area by using a first photomask having a first pattern; B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second photomask having a second pattern; C) defining a pixel region, a contact hole region by using a third photomask having a third pattern; and D) defining a metal electrode region by using a fourth photomask having a fourth pattern.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Macai Lu
  • Patent number: 10269961
    Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 23, 2019
    Assignee: SONY CORPORATION
    Inventors: Satoru Mayuzumi, Hitoshi Wakabayashi
  • Patent number: 10270405
    Abstract: A radio frequency (RF) switch apparatus includes a signal input terminal; a signal output terminal; a first transistor including a first input terminal connected to the signal input terminal, a first output terminal connected to the signal output terminal, a first gate terminal, and a first body terminal, wherein one of the first input terminal and the first output terminal is a source terminal and another one of the first input terminal and the first output terminal is a drain terminal; a first capacitor circuit connected between the first input terminal and the first body terminal; and a second capacitor circuit connected between the first body terminal and the first output terminal; wherein a first capacitance of the first capacitor circuit is greater than a second capacitance of the second capacitor circuit.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jeong Hoon Kim, Hyun Paek
  • Patent number: 10270430
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang-Jui Kao, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 10262998
    Abstract: A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-chul Sagong, Sang-woo Pae, Sung-young Yoon
  • Patent number: 10256230
    Abstract: A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10256293
    Abstract: A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Lars Bomholt