Single Crystal Semiconductor Layer On Insulating Substrate (soi) Patents (Class 257/347)
  • Patent number: 11404515
    Abstract: A display substrate and a manufacturing method thereof, and a display device, are disclosed. The display substrate includes a base substrate and a thin film transistor (TFT) array, including a plurality of TFTs. A first electrode in each TFT includes a first portion and a second portion, a height of the second portion being greater than a height of the first portion in a direction perpendicular to the base substrate, wherein the first portion forms a groove with respect to the second portion and a wall of the groove comprises the second portion of the first electrode of a thin film transistor adjacent to the TFT. A bottom of the groove is the first pixel electrode of a light emitting element, wherein an organic light emitting functional layer is deposited in the groove on the first pixel electrode, and the second pixel electrode on the organic light emitting functional layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 2, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD..
    Inventors: Wei Song, Ce Zhao, Yuankui Ding, Heekyu Kim, Ming Wang, Ning Liu, Yingbin Hu
  • Patent number: 11404410
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 11398475
    Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 26, 2022
    Assignee: SAMSUNG ELECTRONICC CO. LTD
    Inventors: Dongchan Suh, Dahye Kim
  • Patent number: 11398569
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes a plurality of capacitors.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 26, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11398476
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11393898
    Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu Kuan, Shahaji B. More, Chien Lin, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 11393717
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Patent number: 11393761
    Abstract: Disclosed herein is a circuit board that includes first and second conductor layers, an insulating layer positioned between the first and second conductor layers, and a via conductor formed inside a via penetrating the insulating layer and connecting the first and second conductor layers. The via has a shape in which a diameter thereof is reduced in a depth direction. The via has a first section positioned on the first conductor layer side and a second section positioned on the second conductor layer side. A reduction in the diameter per unit depth in the first section is greater than that in the second section.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: July 19, 2022
    Assignee: TDK Corporation
    Inventors: Kazutoshi Tsuyutani, Yoshihiro Suzuki
  • Patent number: 11387331
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting Fang, Chung-Hao Cai, Jui-Ping Lin, Chia-Hsien Yao, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11387364
    Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: July 12, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Avinash Lahgere, Prashanth Paramahans Manik, Peter Javorka, Ali Icel, Mohit Bajaj
  • Patent number: 11387367
    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woocheol Shin, Sunggi Hur, Sangwon Baek, Junghan Lee
  • Patent number: 11374106
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 28, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 11367723
    Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 11349028
    Abstract: A semiconductor device comprising a substrate with a first fin and a second fin disposed on the substrate. A gate electrode is over the first fin and the second fin. A gate-cut pedestal is positioned between the first fin and the second fin, the gate-cut pedestal having side surfaces and a top surface. A portion of the side surfaces of the gate-cut pedestal is covered by the gate electrode. The gate-cut pedestal has a height that is substantially similar to a height of the first fin or the second fin.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 31, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Jiehui Shu
  • Patent number: 11349007
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Patent number: 11342432
    Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Cory Weber, Willy Rachmady, Varun Mishra
  • Patent number: 11342327
    Abstract: An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Abhishek A. Sharma, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 11342448
    Abstract: Provided is a method of manufacturing a semiconductor device, the method including: forming an insulating layer on a substrate; forming a trench, which extends in a first direction parallel with the plane of the substrate, to a preset depth in the insulating layer in a second direction perpendicular to the plane of the substrate; forming a plurality of amorphous silicon strips, which extend from the inside of the trench in the second direction intersecting with the first direction, in parallel in a first direction; forming a spacer on a side of the amorphous silicon strip by using an insulating material layer; and crystallizing the amorphous silicon strip by heat treatment, wherein crystal nucleation sites are formed in the amorphous silicon layer in the trench, and a polycrystalline silicon layer is formed by lateral grain growth in a longitudinal direction of the amorphous silicon strip from the crystal nucleation site.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 24, 2022
    Inventor: Ying Hong
  • Patent number: 11335606
    Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
  • Patent number: 11328927
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 10, 2022
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 11329161
    Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 10, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Su Xing, Chung Yi Chiu, Hai Biao Yao
  • Patent number: 11329067
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 10, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Patent number: 11322410
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Patent number: 11322590
    Abstract: A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 3, 2022
    Inventors: Jongki Jung, Myungil Kang, Yoonhae Kim, Kwanheum Lee
  • Patent number: 11322616
    Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinwoo Jeong, Jaehyoung Lim
  • Patent number: 11315960
    Abstract: A thin film transistor structure and a manufacturing method thereof, a circuit structure, a display substrate and a display device are provided. The thin film transistor structure includes: a base plate, and a first thin film transistor and a second thin film transistor stacked on the base plate. The first thin film transistor and the second thin film transistor share a same active layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: April 26, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Can Yuan, Zhenfei Cai, Yongqian Li, Pan Xu, Zhidong Yuan, Meng Li, Xuehuan Feng
  • Patent number: 11315838
    Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Lin, Kun-Yu Lee, Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 11309262
    Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dong Wang, Xiao Yan Bao, Tian Hua Dong, Guang Ning Li
  • Patent number: 11302813
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material and a semiconductor channel material located on a substrate is provided. An additional dielectric spacer is formed on the dielectric spacer and within a gap. Dielectric spacer is removed. An epitaxial oxide layer is formed on the re-exposed recessed surfaces of the substrate. Germanium is formed on the epitaxial oxide layer. Sidewalls of each semiconductor channel material nanosheet are physically exposed. A source/drain is formed on a surface of the germanium. ILD material is formed above each source/drain and above an adjacent region. Portions of ILD material are removed such that sidewalls of the source/drain and germanium are exposed. The germanium is removed. A contact region is formed that wraps around the source/drain region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Xin Miao, Choonghyun Lee, Jingyun Zhang
  • Patent number: 11304251
    Abstract: Examples disclosed herein include a method performed by a wireless device for transmitting a Packet Data Convergence Protocol (PDCP) protocol data unit (PDU). The method comprises selecting one or both of a first path and a second path for transmitting the PDU to a destination based on a comparison of a first delay on the first path and a second delay on the second path, wherein the first delay includes a queueing delay and/or a processing delay on the first path, and/or the second delay includes a queueing delay and/or a processing delay on the second path. If both the first path and the second path are selected, the method comprises using carrier aggregation (CA) or dual connectivity (DC) to send the PDU to the destination on the first path using a first carrier and sending a duplicate of the PDU to the destination on the second path using a second carrier.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 12, 2022
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Torsten Dudda, Marek Sobe, John Camilo Solano Arenas
  • Patent number: 11296208
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 5, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 11296029
    Abstract: A semiconductor device includes an active pattern extending in a first horizontal direction on a substrate, a gate electrode extending in a second horizontal direction across the active pattern, and including a first portion, and a second portion protruding upward from the first portion in a vertical direction, a capping pattern extending in the second horizontal direction on the gate electrode, and a gate contact disposed on the second portion of the gate electrode, overlapping the active pattern, and penetrating the capping pattern to connect the gate electrode.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju Youn Kim, Deok Han Bae, Jin-Wook Kim, Ju Hun Park, Myung Yoon Um, In Yeal Lee
  • Patent number: 11296083
    Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 5, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Lixin Ge, Kwanyong Lim, Jun Chen
  • Patent number: 11289574
    Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11289573
    Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: March 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Dechao Guo, Ruqiang Bao, Junli Wang, Lan Yu, Reinaldo Vega, Adra Carr
  • Patent number: 11282935
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng
  • Patent number: 11282928
    Abstract: A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keunhwi Cho, Byounghak Hong, Myunggil Kang
  • Patent number: 11282452
    Abstract: Embodiments of the present disclosure provide a pixel circuitry. The pixel circuitry includes a data write-in circuit, an initialization circuit, a sense circuit, a first capacitor, a second capacitor, a drive transistor, and a data signal supply circuit. The data write-in circuit supplies a data signal to a first node according to a first control signal. The initialization circuit supplies an initialization signal to a sense line according to a second control signal. The sense circuit couples a second node to the sense line according to the first control signal. The data signal supply circuit reads the voltage of the sense line according to a third control signal, determines a threshold voltage of the drive transistor according to the read voltage, and corrects an original data signal according to the threshold voltage to supply the corrected original data signal to the data line.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 22, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xinshe Yin
  • Patent number: 11276687
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the third layer includes crystalline silicon; and at least one temperature sensor.
    Type: Grant
    Filed: September 12, 2021
    Date of Patent: March 15, 2022
    Assignee: MONOLITHIC 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11276845
    Abstract: A method of depositing a cathode on an organic light emitting diode (OLED) stack is provided. The method includes providing a substrate having at least a partial organic light emitting diode (OLED) stack disposed on a surface of the substrate. The method further includes depositing, on top of the partial OLED stack, a solution comprising a metal compound. The method further includes forming a conductive solid layer from the metal compound in the solution to form a cathode for the partial OLED stack.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 15, 2022
    Assignee: SINOVIA TECHNOLOGIES
    Inventors: Whitney Gaynor, Bang-Yan Liu
  • Patent number: 11276769
    Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11271106
    Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Brent A. Anderson, ChoongHyun Lee, Hemanth Jagannathan
  • Patent number: 11264477
    Abstract: Structures for field-effect transistors and methods of forming a structure for field-effect transistors. A semiconductor layer includes first and second channel regions, a first field-effect transistor has a first gate dielectric layer over the first channel region, and a second field-effect transistor has a second gate dielectric layer over the second channel region. The first and second channel regions are each composed of an undoped section of an intrinsic semiconductor material, the first gate dielectric layer contains a first atomic concentration of a work function metal, and the second gate dielectric layer contains a second atomic concentration of the work function metal that is greater than the first atomic concentration of the work function metal in the first gate dielectric layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Xiaoli He, Bingwu Liu, Tao Chu
  • Patent number: 11264508
    Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Wei Tsai, Yi-Bo Liao, Sai-Hooi Yeong, Hou-Yu Chen, Yu-Xuan Huang, Kuan-Lun Cheng
  • Patent number: 11264482
    Abstract: A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghyun Kim, Inhyun Song, Yeongmin Jeon, Sejin Park, Juyun Park, Jonghoon Baek, Taeyeon Shin, Sooyeon Jeong
  • Patent number: 11264380
    Abstract: A semiconductor device includes a substrate, a first active fin, a second active fin, a dummy fin and a first gate structure. The first and the second active fin are on the substrate and extend along a first direction. The dummy fin is disposed between the first active fin and the second active fin, and extends in the first direction. The dummy fin includes a plurality of layers, and each of the layers includes a material different from another layer. The first gate structure crosses over the dummy fin, the first and the second active fins.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hou-Ju Li, Chur-Shyang Fu, Chun-Sheng Liang, Jeng-Ya David Yeh
  • Patent number: 11256115
    Abstract: A waveguide structure includes a substrate, a waveguide core coupled to the substrate and including a first material characterized by a first index of refraction, and an isotope-enhanced cladding layer at least partially surrounding the waveguide core and including a second material characterized by a second index of refraction less than the first index of refraction and an isotope-enhanced Pockels effect.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 22, 2022
    Assignee: PSIQUANTUM, CORP.
    Inventor: Gary Gibson
  • Patent number: 11257821
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Si-Woo Lee
  • Patent number: 11257902
    Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lin-Chen Lu, Gulbagh Singh, Tsung-Han Tsai, Po-Jen Wang
  • Patent number: 11257736
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming an isolation layer on a substrate. The isolation layer includes an opening, and a bottom of the opening exposes the substrate. The method also includes forming a fin in the opening. The fin includes a heat-dissipation region and a channel region on the heat-dissipation region. Moreover, the fin includes forming an isolation structure by removing a thickness portion of the isolation layer. A surface of the isolation structure is coplanar with a surface of the heat-dissipation region of the fin. Further, the method includes forming a channel part from the channel region by performing a thinning process to reduce a width of the channel region of the fin using the isolation structure as a mask. The heat-dissipation region of the fin forms a heat-dissipation part.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: February 22, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou