With Additional Electrode To Control Conductive State Of Josephson Junction Patents (Class 257/36)
  • Patent number: 11005024
    Abstract: A superconducting quantum interference devices (SQUID) comprises a superconducting inductive loop with at least two Josephson junction, whereby a magnetic flux coupled into the inductive loop produces a modulated response up through radio frequencies. Series and parallel arrays of SQUIDs can increase the dynamic range, output, and linearity, while maintaining bandwidth. Several approaches to achieving a linear triangle-wave transfer function are presented, including harmonic superposition of SQUID cells, differential serial arrays with magnetic frustration, and a novel bi-SQUID cell comprised of a nonlinear Josephson inductance shunting the linear coupling inductance. Total harmonic distortion of less than ?120 dB can be achieved in optimum cases.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 11, 2021
    Assignee: SeeQC Inc.
    Inventors: Victor K. Kornev, Igor I. Soloviev, Nikolai V. Klenov, Oleg A. Mukhanov
  • Patent number: 10930750
    Abstract: The disclosed technology is directed to a method of forming a qubit device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 23, 2021
    Assignee: IMEC vzw
    Inventors: Clement Merckling, Nadine Collaert
  • Patent number: 10916690
    Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jerry M. Chow
  • Patent number: 10910545
    Abstract: A superconducting junction comprises: a first layer and a second layer of superconducting material; a tunneling layer of insulating material disposed between the first layer and the second layer of the superconducting material; and a layer of thermally conducting, non-superconducting material disposed between the first layer and the second layer of the superconducting material, the non-superconducting layer being in contact with either the first layer or the second layer of superconducting material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 2, 2021
    Assignee: TEKNOLOGIAN TUTKIMUSKESKUS VTT OY
    Inventor: Mikko Kiviranta
  • Patent number: 10879446
    Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Roman Caudillo, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
  • Patent number: 10840295
    Abstract: A fluxonium qubit includes a superinductor. The superinductor includes a substrate, and a first vertical stack extending in a vertical direction from a surface of the substrate. The first vertical stack includes a first Josephson junction and a second Josephson junction connected in series along the vertical direction. The superinductor includes a second vertical stack extending in a vertical direction from a surface of the substrate. The second vertical stack includes a third Josephson junction. The superinductor includes a superconducting connector connecting the first and second vertical stacks in series such that the first, second, and third Josephson junctions are connected in series. The fluxonium qubit further includes a shunted Josephson junction connected to the superinductor with superconducting wires such that the first, second, and third Josephson junctions of the superinductor that are in series are connected in parallel with the shunted Josephson junction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin O. Sandberg, Vivekananda P. Adiga, Rasit O. Topaloglu
  • Patent number: 10777263
    Abstract: A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include it Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 15, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Quentin P. Herr, Anna Y. Herr
  • Patent number: 10741744
    Abstract: A switchable Josephson junction is provided that includes a plurality of ferromagnetic insulators that are defined by their respective magnetic alignments. A first superconducting layer that is positioned between any two of the ferromagnetic insulators, wherein the conductive state is controlled by the relative magnetization orientation of the ferromagnetic insulators where the first superconducting layer is superconducting when the two magnetizations are aligned in antiparallel but it turns normally conducting when the magnetic alignment is parallel. A second superconducting layer is adjacent one of the ferromagnetic layers, wherein Josephson tunneling occurs between the first superconducting layer and second superconducting layer across one of the ferromagnetic layers.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 11, 2020
    Assignee: Massachusets Institute of Technology
    Inventors: Jagadeesh S. Moodera, Juan Pedro Cascales Sandoval, Yota Takamura
  • Patent number: 10636598
    Abstract: Electrical current and/or conductivity in an electrical current channel varies in response to spatiotemporal magnetic flux pattern and/or to variation in electromotive force (EMF). For example, a channel with time-varying electrical conductivity can have induced electrical current variation due to flux pattern resulting from electrical current in another channel or set of channels; the current variation can increase magnetic flux density. The electrical currents can be transient electrical currents, and can cascade to amplify a resulting electromagnetic waveform. A channel can include the channel of a zener or zener-like diode or of a transistor, as well as an extended conductive channel. Channels can be configured in electrical current loops and in various orientations and combinations to obtain current and/or conductivity variation. A transient electrical current can be triggered in a channel, e.g.
    Type: Grant
    Filed: January 1, 2017
    Date of Patent: April 28, 2020
    Inventor: James T. Beran
  • Patent number: 10236433
    Abstract: A thermal impedance amplifier includes: a resistive layer including: a resistance member; a first electrode in electrical communication with the resistance member; and a second electrode in electrical communication with the resistance member; a switch layer opposing the resistive layer and including: a switch member; a first switch electrode in electrical communication with the switch member; and a second switch electrode in electrical communication with the switch member, the switch member: switching from a first resistance to a second resistance in response to receiving phonons from the resistance member, being superconductive at the first resistance, and producing an amplified voltage in response to being at the second resistance; and a thermal conductor interposed between the resistance member and the switch member.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 19, 2019
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Adam McCaughan, Varun Verma, Sonia Buckley, Sae Woo Nam
  • Patent number: 10109673
    Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 23, 2018
    Assignee: Hypres, Inc.
    Inventor: Sergey K. Tolpygo
  • Patent number: 10097143
    Abstract: A Josephson-coupled resonator amplifier is provided. The Josephson-coupled resonator amplifier includes a first and a second resonator, each formed from respective lumped-element capacitance and respective lumped-element inductance. The Josephson-coupled resonator amplifier further includes one or more Josephson junctions coupling the first resonator to the second resonator, whereby a superconducting loop is formed from at least the lumped-element inductance of the resonators and the one or more Josephson junctions.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventor: Baleegh Abdo
  • Patent number: 9948254
    Abstract: A wireless Josephson-junction-based amplifier is described that provides improved tunability and increased control over both a quality factor Q and participation ratio p of the amplifier. The device may be fabricated on a chip and mounted in a waveguide. No wire bonding between the amplifier and coaxial cables or a printed circuit board is needed. At least one antenna on the chip may be used to couple energy between the waveguide and wireless JBA. The amplifier is capable of gains greater than 25 dB.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: April 17, 2018
    Assignee: Yale University
    Inventors: Anirudh Narla, Katrina Sliwa, Michael Hatridge, Shyam Shankar, Luigi Frunzio, Robert J. Schoelkopf, III, Michel Devoret
  • Patent number: 9509315
    Abstract: A three-terminal device that exhibits transistor-like functionality at cryogenic temperatures may be formed from a single layer of superconducting material. A main current-carrying channel of the device may be toggled between superconducting and normal conduction states by applying a control signal to a control terminal of the device. Critical-current suppression and device geometry are used to propagate a normal-conduction hotspot from a gate constriction across and along a portion of the main current-carrying channel. The three-terminal device may be used in various superconducting signal-processing circuitry.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 29, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Adam N. McCaughan, Karl K. Berggren
  • Patent number: 9362919
    Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 7, 2016
    Assignee: University of Notre Dame du Lac
    Inventors: Behnam Sedighi, Michael Niemier, X. Sharon Hu, Joseph J. Nahas
  • Patent number: 9136457
    Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 15, 2015
    Assignee: Hypres, Inc.
    Inventor: Sergey K. Tolpygo
  • Patent number: 9136574
    Abstract: This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, David Francis Berdy, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka
  • Publication number: 20140315723
    Abstract: A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 23, 2014
    Applicant: The Regents of the University of California
    Inventors: Stephanie Moyerman, Brian Keating
  • Patent number: 8852959
    Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Northrup Grumman Systems Corporation
    Inventors: John J. Talvacchio, Erica C. Folk, Sean R. McLaughlin, David J. Phillips
  • Patent number: 8822979
    Abstract: Disclosed is an arrangement including a support and a super-conductive film which is arranged thereon. The film has a plurality of holes in order to form a perforated grating. The holes are optionally round holes having increasing sizes, triangular holes, or holes which are arranged in a meandering manner in the film, and which produce improved properties in relation to signal conversion by a vortex diode and/or in a filter. A DC signal is directly removed therein without additional electronics.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 2, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventor: Roger Woerdenweber
  • Patent number: 8786476
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 22, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8648331
    Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described. The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 11, 2014
    Assignee: Microsoft Corporation
    Inventors: Parsa Bonderson, Roman Lutchyn
  • Patent number: 8395053
    Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 12, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang
  • Patent number: 8330145
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 11, 2012
    Assignees: The Chugoku Electric Power Co., Inc., Hitachi Ltd., Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
  • Patent number: 8263967
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: September 11, 2012
    Assignee: Board of Regents, The University of Texas Systems
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
  • Patent number: 8188460
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 29, 2012
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
  • Patent number: 8098179
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: January 17, 2012
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8076703
    Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 13, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Akif Sultan, James F. Buller, Kaveri Mathur
  • Publication number: 20110175628
    Abstract: Disclosed is a triple-gate or multi-gate component based on the quantum mechanical tunnel effect. The component comprises at least two tunneling electrodes on a substrate that are separated by a gap through which electrons can tunnel. The component comprises an arrangement for applying an electric field to the gap, which is such that the path of an electron tunneling between the tunneling electrodes is elongated as a result of the deflection caused by this field. In general, an arrangement can also be provided for applying an electric field to the gap, this electric field having a field component that is perpendicular to the direction of the tunnel current between the tunneling electrodes and is parallel to the substrate. Since the tunnel current between the tunneling electrodes exponentially depends on the distance traveled by the electrons in the gap, such an electric field has a penetration effect on the tunneling probability and thus on the tunnel current to be controlled.
    Type: Application
    Filed: June 19, 2009
    Publication date: July 21, 2011
    Inventor: Hermann Kohlstedt
  • Publication number: 20110148441
    Abstract: With a simple circuit configuration which does not conduct high frequency signal processing, a quantum computing device, a quantum bit readout processing unit of the quantum computing device, and a quantum bit readout processing method are provided. By controlling a quantum bit structure, which is formed with a counter electrode coupling with a quantum box electrode through a first tunnel barrier, with a gate voltage, a Cooper-pair extracted from the quantum box electrode after computation is accumulated in a trap electrode coupling with the quantum bit structure by sandwiching a second tunnel barrier. By coupling the trap electrode and an island electrode of a readout single electron transistor through a static capacitance, a change of electric charge in the trap electrode is read out as a direct current value of the single electron transistor.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2011
    Applicant: NEC CORPORATION
    Inventors: Tsuyoshi Yamamoto, Jaw-Shen Tsai
  • Patent number: 7923717
    Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 12, 2011
    Inventor: Katsuyuki Tsukui
  • Patent number: 7858966
    Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 28, 2010
    Assignee: Microsoft Corporation
    Inventor: Alexei Kitaev
  • Patent number: 7741634
    Abstract: A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 22, 2010
    Assignee: Massachusetts Institute of Technology
    Inventors: Heejae Shim, Jagadeesh S. Moodera
  • Patent number: 7323711
    Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: January 29, 2008
    Assignees: FUJITSU Limited, International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Hideo Suzuki, Masahiro Horibe, Keiichi Tanabe
  • Patent number: 7307275
    Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 11, 2007
    Assignees: D-Wave Systems Inc., The University of Toronto
    Inventors: Daniel Lidar, Lian-Ao Wu, Alexandre Blais
  • Patent number: 7250648
    Abstract: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: July 31, 2007
    Assignee: Intematix Corporation
    Inventors: Yi-Qun Li, Young Yoo, Qizhen Xue, Ning Wang, Daesig Kim
  • Patent number: 6995390
    Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 7, 2006
    Inventor: Katsuyuki Tsukui
  • Patent number: 6984846
    Abstract: A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, David P. DiVincenzo, Roger H. Koch, Glenn J. Martyna, Jim Rozen, Chang Chyi Tsuei
  • Patent number: 6979836
    Abstract: A superconducting structure that can operate, for example, as a qubit or a superconducting switch is presented. The structure includes a loop formed from two parts. A first part includes two superconducting materials separated by a junction. The junction can, for example, be a 45° grain boundary junction. The second part can couple the two superconducting materials across the junction. The second part includes a superconducting material coupled to each of the two superconducting materials of the first part through c-axis junctions. Further embodiments of the invention can be as a coherent unconventional superconducting switch, or a variable phase shift unconventional superconductor junction device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 27, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre M. Zagoskin, Alexander Ya. Tzalenchuk, Jeremy P. Hilton
  • Patent number: 6844566
    Abstract: The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (100) located over a substrate (115) and a quantum island (120) situated between the source and drain (105, 110), to form tunnel junctions (125, 130) between the source and drain (105, 110). The device (100) further includes a movable electrode (135) located adjacent the quantum island (120) and a displaceable dielectric (140) located between the moveable electrode (135) and the quantum island (120). The present invention also includes a method of fabricating a single-electron device (200), and a transistor circuit (300) that include a single-electron device (310).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 18, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Christoph Wasshuber
  • Publication number: 20040232405
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Application
    Filed: March 26, 2004
    Publication date: November 25, 2004
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6822255
    Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: November 23, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
  • Patent number: 6812484
    Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: November 2, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
  • Patent number: 6803599
    Abstract: A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform include read out, initialization, and entanglement. The state of a qubit can be determined by grounding the qubit, applying a current across the qubit, measuring the resulting potential drop across the qubit, and interpreting the potential drop as a state of the qubit. A qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction for a time sufficient that the quantum state of the qubit can relax into the selected state. In some embodiments, the qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction and then ramping the current to zero in order that the state of the qubit relaxes into the selected state.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: October 12, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Geordie Rose, Alexandre Zagoskin, Jeremy P. Hilton
  • Patent number: 6790675
    Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignees: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Yoshihiro Ishimaru, Masahiro Horibe, Osami Horibe, Yoshinobu Tarutani, Keiichi Tanabe
  • Patent number: 6791109
    Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 14, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexander Tzalenchuk, Zdravko Ivanov, Jeremy P. Hilton
  • Patent number: 6784451
    Abstract: In one embodiment, a two-junction phase qubit includes a superconducting loop and two Josephson junctions separated by a mesoscopic island on one side and a bulk loop on another side. The material forming the superconducting loop is a superconducting material with an order parameter that violates time reversal symmetry. In one embodiment, a two-junction phase qubit includes a loop of superconducting material, the loop having a bulk portion and a mesoscopic island portion. The loop further includes a relatively small gap located in the bulk portion. The loop further includes a first Josephson junction and a second Josephson junction separating the bulk portion from the mesoscopic island portion. The superconducting material on at least one side of the first and second Josephson junctions has an order parameter having a non-zero angular momentum in its pairing symmetry. In one embodiment, a qubit includes a superconducting loop having a bulk loop portion and a mesoscopic island portion.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 31, 2004
    Assignee: D-Wave Systems Inc.
    Inventors: Mohammad H. S. Amin, Alexandre Zagoskin, Geordie Rose, Jeremy P. Hilton
  • Patent number: 6777808
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber
  • Patent number: 6728131
    Abstract: A method for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors and shaped junctions that may be used as qubits for quantum computing.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 27, 2004
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexey V. Ustinov
  • Publication number: 20040000666
    Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.
    Type: Application
    Filed: April 4, 2003
    Publication date: January 1, 2004
    Inventors: Daniel Lidar, Lian-Ao Wu, Alexandre Blais