Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

Abstract: A semiconductor device with a shallow trench isolation structure includes a semiconductor substrate having a first region and a second region, a plurality of fins on the first and second regions, a first isolation region between the first and second regions, the first isolation region having an upper portion doped with ions, and a second isolation region between the fins. The doped upper portion is characterized by a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A semiconductor device includes: an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns in which a drain electrode and a source electrode are alternately arranged along an array direction determined in advance, on the semiconductor layer; and a group of gate fingers each having a shape extending in an extending direction which is different from the array direction. Each of the gate fingers is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers are arranged at positions displaced from one another in the extending direction.

Abstract: In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved. An insulating film is formed between an upper surface of a fin and each of a control gate electrode and a memory gate electrode in a memory cell region, so that in a gate insulating film of each of a control transistor and a memory transistor, thickness of a portion on the fin is larger than thickness of a portion covering side surfaces of the fin. The insulating film having a bird's beak at its end portion is formed to round a corner of the fin.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.

Abstract: A semiconductor device includes a plurality of semiconductor fins, an epitaxy structure, a capping layer, and a contact. The epitaxy structure adjoins the semiconductor fins. The epitaxy structure has a plurality of protrusive portions. The capping layer is over a sidewall of the epitaxy structure. The contact is in contact with the epitaxy structure and the capping layer. The contact has a portion between the protrusive portions. The portion of the contact between the protrusive portions has a bottom in contact with the epitaxy structure.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Abstract: A semiconductor and a method of creating the same are provided. The semiconductor structure includes a first set of fins and a second set of fins disposed on a substrate. There is a high-k dielectric disposed on top of the substrate and the first and second set of fins. There is a work-function metal disposed on top of the high-k dielectric. There is a pinch-off layer disposed on top of the work-function metal (WFM). There is a first dielectric layer disposed on top of the pinch-off layer. There is a second dielectric material configured as a gate cut between the first set of fins and the second set of fins, wherein the second dielectric material cuts through the nitride, pinch-off, and WFM layers.

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

Abstract: Semiconductor structures are provided. A first source and drain region of a first transistor is electrically connected to a first conductive line through a first contact and a first via over the first contact. A first gate electrode of the first transistor is electrically connected to a second conductive line through a second contact and a second via over the second contact. A second source and drain region of a second transistor is electrically connected to a third conductive line through a third contact and a third via over the third contact. A second gate electrode of the second transistor is electrically connected to a fourth conductive line of the metal layer directly through a fourth via. Projections of the second via and the first channel region are separated on the substrate, and projections of the fourth via and the second channel region are overlapped on the substrate.

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.

Abstract: An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.

Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

Abstract: A method of fabricating a semiconductor structure includes forming a plurality of Fin structures, doping first dopants at both sides of a first Fin structure of the Fin structures, and providing a first thermal diffusion operation to the semiconductor structure. The method also includes doping second dopants at both sides of a second Fin structure of the Fin structures, and providing a second thermal diffusion operation to the semiconductor structure. A first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and a second gate length for the second Fin structure using the second thermal diffusion operation. The first dopants are of the same type or a different type.

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

Abstract: Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.

Abstract: A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.

Abstract: A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate and a substrate having fins extending upwardly through the STI. The fins include: nFET fins disposed in an nFET epi well formed in the STI and disposed in a pFET epi well formed in the STI, a top the STI being above a top of the fins.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate, forming an amorphous layer in the substrate, performing a first etching process on the substrate using the amorphous layer as an etch stop layer to form a plurality of first fins, performing a channel stop ion implantation process into the amorphous layer to form an impurity region, and performing an annealing process to activate implanted dopants in the impurity region, wherein the amorphous layer disappears during the annealing process. The method also includes performing a second etching process on a region of the substrate disposed between the first fins to form second fins from the first fins, and forming an isolation region between adjacent second fins by filling at least a portion of an air gap between the second fins with an insulating material. The method prevents dopants of the channel stop implant from diffusing into the channel.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a base substrate having a first well and a second well region; a first insulation layer over the base substrate and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer; a gate structure over the base substrate in the first well region and the first region of the second well region; a first mask gate structure on a portion of the second region adjacent to the first region; a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer.

Abstract: At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

Abstract: The present disclosure generally relates to the field of receiver structures in radio communication systems and more specifically to passive mixers in the receiver structure and to a technique for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency.

Abstract: A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.