Abstract: Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

Abstract: A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.

Abstract: The present invention offers the semiconductor device which can solve each problem, such as Fermi level pinning, formation of gate electrode depletion, and a diffusion phenomenon, can adopt a material suitable for each gate electrode of the MOS structure from which threshold voltage differs, and can adjust (control) threshold voltage appropriately by the manufacturing process simplified more and which has a MOS structure. In the semiconductor device which has a MOS structure concerning the present invention, a PMOS transistor has the structure in which the gate insulating film, first metal layer, second metal layer, and polysilicon layer was formed in the order concerned. An NMOS transistor has the structure by which a gate insulating film and polysilicon were formed in the order concerned.

Abstract: A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics having gate-lengths less than 65 nm.

Abstract: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.

Abstract: A MOS isolation coupler is formed on a semiconductor chip by a CMOS process and comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.

Abstract: A high-voltage circuit protection device includes a p-n junction in a semiconductor substrate that is spaced apart from a first electrode region by a diode region. A semiconductor layer overlies the diode region and is separated therefrom by a dielectric layer. A shallow-doped region resides in the diode region spaced apart from the p-n junction by a predetermined distance. The predetermined distance preferably ranges from about 0 to about 50% of the length of the diode region. A process for fabricating the high-voltage device includes forming the shallow-doped region using a threshold adjustment mask followed by formation of the first electrode region using the semiconductor layer in a self-aligned doping process. The shallow-doped region functions to reduce the clamping voltage of the device.

Abstract: Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

Abstract: A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating layers, and the first and second gate lines implement first and second capacitors, the second and third ridges and the first gate line implement first driver and load transistors, and the fourth and fifth ridges and the second gate lines implement second load and driver transistors.

Abstract: A split drain magnetic field effect transistor (MAGFET) includes at least one supplemental gate to exert a lateral electrical field in the channel of the MAGFET. Connection of the supplemental gate in feedback with one of the two drain contacts allows the MAGFET to act as a latch sensitive to the presence of an external magnetic field. Preferably, the MAGFET includes two laterally spaced supplemental gates, allowing for the detection of an external magnetic field and its orientation.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: A semiconductor device, comprises a first electrode, a semiconductor film, a first insulating film and a second insulating film formed between the semiconductor film and the first electrode, a second electrode, and a third insulating film formed between the semiconductor film and the second electrode. The semiconductor film is formed on a flat surface of the second insulating film. A cross portion where the first electrode and the second electrode cross the semiconductor film at the same position is formed. The first electrode and the second electrode are connected to each other through an opening made in the first insulating film and the second insulating film outside the cross portion.

Abstract: An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type disposed in contact with the semiconductor thin film. A gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.

Abstract: In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelogram, and a second gate forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region and a drain region. In some embodiments, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient ? of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. A pair of source/drain areas having a second conductivity type is formed on a surface of the semiconductor substrate. A gate insulating film is provided on a channel area between the source/drain areas. A gate electrode having the first conductivity type is provided on the gate insulating film. The gate electrode has a first portion located above a channel area and second portions located above the source/drain area. The concentration of majority carriers in the second portion is lower than that in the first portion.

Abstract: Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

Abstract: A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, said memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of said memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of said memory cell lines aligned in a channel widthwise direction of the memory cells, wherein said memory cells on a common memory cell line are aligned to uniformly orient the directions from their s

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.

Abstract: A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract: It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode (3) at a subsequent step. In the meantime, the upper surface of the gate electrode (3) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall (4) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode (3) and to form a contact on the gate electrode (3).

Abstract: A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.

Abstract: A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.

Abstract: In a CMOS circuit formed on a substrate 101, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 107a are provided in an n-channel TFT. The LDD regions 113 overlaps the first wiring line 102a and does not overlap the second wiring line 107a. Thus, when a gate voltage is applied to the first wiring line, the GOLD structure is formed, while no applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract: A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (15) on a first side of the channel body, and an auxiliary gate (18) on a second side of the channel body. With a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state, the MISFET has a first data state in which the majority carriers are accumulated and a second data state in which the majority carriers are emitted.

Abstract: A semiconductor device comprises: a semiconductor substrate of a first conductivity type; a first electrode provided on the semiconductor substrate with the intervention of a gate insulation film; a second electrode provided at least on the first electrode with the intervention of an intermediate insulation film; and a pair of impurity regions of a second conductivity type provided in a spaced relation in the semiconductor substrate, at least one of the impurity regions comprising a low concentration impurity region, an intermediate concentration impurity region and a high concentration impurity region sequentially arranged in this order from a region located underneath the first electrode.

Abstract: A FinFET includes a fin formed on an insulating layer and a first gate material layer formed proximate to sides of the fin. The FinFET further includes a protective layer formed above the first gate material layer and the fin, and a second gate material layer formed above the protective layer and the fin. The second gate material layer may be formed into a gate for the fin that may be biased independently of gate(s) formed from the first gate material layer, thus providing additional design flexibility in controlling the potential in the fin during on/off switching of the FinFET.

Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.

Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) comprising a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) comprising a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.

Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.

Abstract: An aspect the present invention is to provide a semiconductor device including at least one MISFET structure having an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least the surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.

Abstract: A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract: In order to apply a predetermined voltage to a silicon layer (3) to control a threshold voltage, a second gate electrode (5) is provided on the surface of the silicon layer (3) with a gate oxide film (insulating layer) (4) interposed therebetween so as to fall within the same surface of the silicon layer (3) as a surface on which a source (7) and a drain (8) placed in the silicon layer (3) and a first gate electrode (6) are disposed.

Abstract: This invention is intended to provide a technique for improving characteristics of a TFT and realizing a structure of the TFT optimum for driving conditions of a pixel section and a driving circuit by using a small number of photomasks. The TFT includes a first electrode, a first insulating film put between a semiconductor film and the first electrode, a second electrode, and a second insulating film put between the semiconductor film and the second electrode. The first electrode and the second electrode are overlapped with each other, with a channel formation region of the semiconductor film put between the first electrode and the second electrode, and a constant voltage is always applied to the first electrode.

Abstract: Disclosed are a thin film transistor capable of controlling gray level of an organic LED element by discretely controlling current levels, a method of manufacturing the thin film transistor, an array substrate including the thin film transistor, a display device, and a method of driving the display device. The thin film transistor of the present invention includes an active layer formed on an insulating substrate, a plurality of insulating layers formed oppositely to each other with the active layer interposed therebetween, a first gate electrode and a second gate electrode formed adjacently to the insulating layers respectively, and wiring connected to the first and second gate electrodes respectively, the wiring controlling respective potentials of the first and second gate electrodes independently of each other. The area of the first gate electrode is different from the area of the second gate electrode, and current levels can be discretely controlled in at least four levels.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.