Overlapping Gate Electrodes Patents (Class 257/366)
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Patent number: 6661066Abstract: A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).Type: GrantFiled: September 22, 1999Date of Patent: December 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita, Katsuomi Shiozawa
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Patent number: 6646307Abstract: A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.Type: GrantFiled: February 21, 2002Date of Patent: November 11, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Eric N. Paton
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Patent number: 6621124Abstract: The semiconductor device has a semiconductor body (1) having a field effect transistor (4) at a first surface (2) and a second gate (10) at a second surface (3). The second gate is present in a recess (11) in the semiconductor body (1) which is accurately aligned with a first gate (8) of the field effect transistor (4) on the first surface (2). The method of manufacturing the semiconductor device comprises the step of implanting ions into a semiconductor body (1) which has a first gate (8) on a first surface (2) and a silicon oxide layer (17) on a second surface (3). The implantation is done from the first surface (2) in a direction substantially perpendicular to that surface. The implantation has the effect that behind the first gate (8) an implanted region (18) is formed in the semiconductor body (1) and a circumferential implanted zone (19) in the silicon oxide layer (17). Silicon oxide is formed in the implanted region (18) by dopant-enhanced oxidation.Type: GrantFiled: February 28, 2001Date of Patent: September 16, 2003Assignee: Koninklijke Philips Electronics N.V.Inventor: Youri Ponomarev
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Patent number: 6617651Abstract: A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (15) on a first side of the channel body, and an auxiliary gate (18) on a second side of the channel body. With a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state, the MISFET has a first data state in which the majority carriers are accumulated and a second data state in which the majority carriers are emitted.Type: GrantFiled: September 28, 2001Date of Patent: September 9, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Ohsawa
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Patent number: 6611029Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.Type: GrantFiled: November 8, 2002Date of Patent: August 26, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 6603453Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: August 28, 2002Date of Patent: August 5, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Patent number: 6597043Abstract: The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. Four substrate diffusion regions, each having a second conductivity type opposite the first conductivity type, are formed in the substrate diffusion region in a respective comer of the substrate region. The four diffusion regions are spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions. A common conductive gate electrode is formed to have four fingers, each one of the fingers extending over a corresponding substrate channel region. The fingers of the common conductive gate electrode are spaced-apart from the underlying substrate channel regions by dielectric material formed therebetween.Type: GrantFiled: November 13, 2001Date of Patent: July 22, 2003Assignee: National Semiconductor CorporationInventor: Abdalla Naem
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Patent number: 6583478Abstract: A semiconductor transfer circuit and a structure thereof are provided. The transfer circuit and the structure thereof include a stack gate MOS transistor having first and second gate electrodes that are sequentially stacked and a control MOS transistor connected to the stack gate MOS transistor. A drain of the control MOS transistor is connected to the first gate electrode.Type: GrantFiled: September 6, 2001Date of Patent: June 24, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Sung-Hoi Hur
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Patent number: 6580129Abstract: The present invention provides, in a TFT, a gate electrode and a channel domain that are plurally divided in the channel-length direction, a low-concentration domain that is formed between the divided channel domains, and a low-concentration drain domain that adjoins a second channel domain located closest to a drain domain side among the divided channel domains. Therefore, even if the impurity concentration is relatively high in the low-concentration domain located between the divided channel domains and a low-concentration drain domain, an abnormal increase of drain current in the saturated region can be prevented, and a TFT with a high drain current level can be obtained. Thus, the present invention provides a TFT and its manufacturing method where abnormal increase of drain current in the saturated region can be prevented and the drain current level in the saturated region is sufficiently high.Type: GrantFiled: December 13, 2001Date of Patent: June 17, 2003Assignee: Seiko Epson CorporationInventors: Basil Lui, Piero Migliorato, Ichio Yudasaka, Mitsutoshi Miyasaka
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Patent number: 6573556Abstract: A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel.Type: GrantFiled: July 1, 2002Date of Patent: June 3, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kelvin Yin-Yuh Doong, Ching-Hsiang Hsu
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Patent number: 6548870Abstract: In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity region and the second impurity region. At least two gate electrodes are formed on the gate insulating layer, and are insulated from one another by an intergate insulation layer.Type: GrantFiled: November 28, 2000Date of Patent: April 15, 2003Assignee: Hynix Semiconductor Inc.Inventor: Hi Deok Lee
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Patent number: 6548862Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.Type: GrantFiled: May 14, 2002Date of Patent: April 15, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hyuk-ju Ryu, Jong-hyon Ahn
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Publication number: 20030067041Abstract: A method for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The new method produces significantly larger tunneling currents for a given voltage than attained in prior work. The new method is advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs). These FLOTOX transistors are candidates for replacing the low power operation transistors found in DRAMs.Type: ApplicationFiled: November 1, 2002Publication date: April 10, 2003Applicant: Micron Technology, Inc.Inventors: Joseph E. Geusic, Leonard Forbes
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Patent number: 6545324Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.Type: GrantFiled: May 20, 2002Date of Patent: April 8, 2003Assignee: Motorola, Inc.Inventors: Sucharita Madhukar, Bich-Yen Nguyen
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Patent number: 6545323Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.Type: GrantFiled: December 14, 2001Date of Patent: April 8, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Yukihito Oowaki, Masako Yoshida, Makoto Yoshimi
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Patent number: 6528852Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.Type: GrantFiled: October 24, 2001Date of Patent: March 4, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiko Takemura
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Patent number: 6504215Abstract: A single crystal silicon is graphoepitaxially grown using a step formed on a substrate as a seed by a catalyst process, and the obtained single crystal silicon layer is used for a dual gate type MOSTFT in an electro-optical apparatus such as a display section of a peripheral driving circuit integration type LCD. A single crystal silicon thin film having high electron/hole mobility is formed into a uniform film at a relatively low temperature, which enables the manufacturing of an active matrix substrate incorporated with a high-performance driver which can be used in a TFT display.Type: GrantFiled: September 27, 1999Date of Patent: January 7, 2003Assignee: Sony CorporationInventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Satou, Hajime Yagi
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Patent number: 6462723Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: June 11, 1999Date of Patent: October 8, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20020130344Abstract: There is provided a semiconductor device including a transistor formed by means of a common contact hole that connects a gate electrode, and a diffused layer forming a source/drain terminal; and a semiconductor device comprising the gate electrode of the transistor, and a connecting terminal to which capacitance between substrates and capacitance between the gate electrode and the source/drain terminal are added, thereby improving the soft error resistance caused by alpha rays and neutron beams.Type: ApplicationFiled: December 6, 2001Publication date: September 19, 2002Inventors: Koji Nii, Motoshige Igarashi
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Patent number: 6445032Abstract: A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.Type: GrantFiled: May 4, 1998Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Arvind Kumar, Sandip Tiwari
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Patent number: 6429472Abstract: A split gate type flash memory having an active region that improves an endurance characteristic along with program/erase efficiency, wherein the split gate type flash memory provides for improvement in the endurance characteristic and program/erase efficiency by making the width of an active region in a portion in which a source is overlapped by a floating gate as large as possible.Type: GrantFiled: March 9, 2001Date of Patent: August 6, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-ki Kim, Won-il Ryu
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Patent number: 6383904Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a first layer of dielectric material is formed on the semiconductor substrate, and a layer of amorphous semiconductor material is deposited on the first layer of dielectric material. A second layer of dielectric material is deposited on the layer of amorphous semiconductor material, and a front gate opening is etched through the second layer of dielectric material to expose the layer of amorphous semiconductor material through the front gate opening. An amorphization dopant is implanted into the semiconductor substrate through the front gate opening to form a back gate region of amorphous semiconductor material in the semiconductor substrate such that the back gate region is formed to be aligned under the front gate opening. In addition, a back gate dopant is implanted into the back gate region of amorphous semiconductor material through the front gate opening.Type: GrantFiled: October 16, 2000Date of Patent: May 7, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6359312Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.Type: GrantFiled: August 3, 2000Date of Patent: March 19, 2002Assignee: Sony CorporationInventor: Hiroshi Komatsu
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Patent number: 6323561Abstract: The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.Type: GrantFiled: December 9, 1997Date of Patent: November 27, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Fred N. Hause, Charles E. May
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Patent number: 6316808Abstract: Disclosed is a type “BC” body contacted SOI transistor and process for making these transistors in a manufacturing environment by providing a structure and process which removes overlay tolerance from the effective transistor width. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an “UP misalignment will make the device with large, while a “DOWN” misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor.Type: GrantFiled: August 7, 1998Date of Patent: November 13, 2001Assignee: International Business Machines CorporationInventor: George E. Smith, III
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Patent number: 6297536Abstract: A diode structure compatible with silicide processes for electrostatic discharge protection is disclosed. The diode structure comprises a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region. The doped region has a doping concentration less than that of the diffusion region to provide a ballastic resistance under a high current stressing condition.Type: GrantFiled: March 18, 1999Date of Patent: October 2, 2001Assignee: Winbond Electronics Corp.Inventor: Ta-Lee Yu
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Patent number: 6281551Abstract: A back-plane for a semiconductor device, includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.Type: GrantFiled: August 9, 1999Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Christopher Peter D'Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari
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Patent number: 6255699Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.Type: GrantFiled: May 1, 2000Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: John A. Bracchitta, Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman
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Patent number: 6198133Abstract: Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display (LCD) on one substrate.Type: GrantFiled: February 16, 1999Date of Patent: March 6, 2001Assignee: Semiconductor Energy Laboratory Company, Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 6166412Abstract: A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.Type: GrantFiled: December 22, 1999Date of Patent: December 26, 2000Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyung Ki Kim, Jong Wook Lee
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Patent number: 6127704Abstract: A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.Type: GrantFiled: March 17, 1998Date of Patent: October 3, 2000Inventor: Dong Sun Kim
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Patent number: 6118157Abstract: A split-gate MOS transistor includes two separate but partially overlapping gates to reduce the electric field near the drain-channel interface region and, thereby, has an increased gated-diode breakdown voltage.Type: GrantFiled: March 18, 1998Date of Patent: September 12, 2000Assignee: National Semiconductor CorporationInventor: Albert Bergemont
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Patent number: 6104069Abstract: A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.Type: GrantFiled: November 4, 1998Date of Patent: August 15, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Michael Duane, Daniel Kadosh, Mark I. Gardner
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Patent number: 6055182Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.Type: GrantFiled: April 1, 1998Date of Patent: April 25, 2000Assignee: Sony CorporationInventors: Mikio Mukai, Yutaka Hayashi
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Patent number: 6043535Abstract: The invention comprises a transistor having a self-aligned implant under the gate. The transistor comprises a drain region, a source region opposite the drain region, and a channel region in a semiconductor substrate extending between the source region and the drain region. A front gate is disposed outwardly from the first substrate layer and is separated from the channel region by a dielectric layer. The front gate comprises a first gate layer disposed outwardly from the dielectric layer and a second gate layer disposed outwardly from the first gate layer. A self-aligned implant region is disposed inwardly from the channel region and in approximate vertical alignment with the front gate.Type: GrantFiled: August 26, 1998Date of Patent: March 28, 2000Assignee: Texas Instruments IncorporatedInventor: Theodore W. Houston
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Patent number: 6025633Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.Type: GrantFiled: December 2, 1998Date of Patent: February 15, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Daniel Kadosh, Mark I. Gardner
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Patent number: 6005273Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.Type: GrantFiled: December 10, 1997Date of Patent: December 21, 1999Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, David Kao
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Patent number: 5998842Abstract: A MOS semiconductor device with control electrodes for improved switching accuracy and operational speeds of the device at reduced power consumption levels. The semiconductor device includes a substrate, a source electrode region and a drain electrode region formed in said substrate, a first gate insulating film formed on said substrate, a semiconductor region formed on said first gate insulating film, a second gate insulating film formed on said semiconductor region, a gate electrode region formed on said second gate insulating film, and at least one control electrode region disposed in contact with said semiconductor region.Type: GrantFiled: July 23, 1996Date of Patent: December 7, 1999Assignee: Ricoh Company, Ltd.Inventor: Yutaka Sano
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Patent number: 5973367Abstract: A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC-DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC-DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC-DC converter.Type: GrantFiled: March 31, 1997Date of Patent: October 26, 1999Assignee: Siliconix incorporatedInventor: Richard K. Williams
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Patent number: 5955765Abstract: An insulated-gate thin-film semiconductor device having reduced leakage current. The device has a thin-film semiconductor in which source and drain regions are formed. First and second electrodes are formed on opposite sides of the thin-film semiconductor. At least one of the second electrodes electrically overlaps none of the source and drain regions. When a reverse bias voltage is applied to the first gate electrode (i.e., in an unselected state), a forward bias voltage is applied to the second gate electrode, thus controlling the leakage current path. Thus, the resistance in the unselected state is increased. Consequently, the leakage current is reduced. Because of this construction, the on/off current ratio of the thin-film transistor can be enhanced.Type: GrantFiled: March 14, 1997Date of Patent: September 21, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Yasuhiko Takemura
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Patent number: 5949094Abstract: An ESD protected semiconductor circuit and the ESD protection circuit. The protected circuit includes a terminal, a semiconductor device coupled to the terminal and an ESD protection circuit. The ESD protection circuit includes a substrate of a first conductivity type and has a surface. A first well of conductivity type opposite to the first conductivity type is disposed within the substrate and extends to the surface. A second well of the first conductivity type is disposed within the first well and is spaced from the substrate and extending to the surface. A third region of the opposite conductivity type is disposed within the second well and is spaced from the first well and extending to the surface. At least one of the substrate or the third region is coupled to the terminal.Type: GrantFiled: August 29, 1997Date of Patent: September 7, 1999Assignee: Texas Instruments IncorporatedInventor: E. Ajith Amerasekera
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Patent number: 5936275Abstract: A method of forming a line for floating gate transistors is described and which includes, providing a substrate having a plurality of discrete field oxide regions, and intervening active area regions therebetween; forming a first alternating series of floating gates over a first alternating series of active area regions; forming a second alternating series of floating gates over a second alternating series of active area regions, the second series of floating gates disposed in spaced, overlapping and partial covering relation relative to the first alternating series of floating gates; forming a layer of dielectric material over the first and second series of floating gates; and forming a control gate layer of electrically conductive material over the layer of dielectric material. The present invention further relates to a memory chip, and die having a line of floating gate transistors formed from the same method.Type: GrantFiled: December 11, 1997Date of Patent: August 10, 1999Assignee: Micron Technology, Inc.Inventor: Roger R. Lee
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Patent number: 5912497Abstract: Semiconductor switching devices having buried gate electrodes include a substrate, a drift region of first conductivity type (e.g., N-) extending to a face of the substrate and a first insulated gate electrode buried in the drift region. The first insulated gate electrode extends laterally in the substrate in spaced relation to the face. A second gate electrode is also provided on the face at a location extending opposite the first insulated gate electrode. A base region of second conductivity type (e.g., P) is also provided in the substrate, between the second gate electrode and an upper surface of the first insulated gate electrode. Similarly, an emitter region of first conductivity type (e.g., N+) is provided between the first face and the upper surface of the first insulated gate electrode. The base region is defined so that respective P-N junctions are formed with the emitter and drift regions.Type: GrantFiled: August 6, 1997Date of Patent: June 15, 1999Assignee: North Carolina State UniversityInventor: Bantval Jayant Baliga
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Patent number: 5912490Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.Type: GrantFiled: August 4, 1997Date of Patent: June 15, 1999Assignee: SpectrianInventors: Francois Hebert, Daniel Ng
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Patent number: 5905291Abstract: A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.Type: GrantFiled: July 18, 1995Date of Patent: May 18, 1999Assignee: Seiko Instruments Inc.Inventors: Fumiyasu Utsunomiya, Yutaka Saitoh, Naoto Saitoh, Jun Osanai, Haruo Konishi, Masanori Miyagi
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Patent number: 5847429Abstract: An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.Type: GrantFiled: July 31, 1996Date of Patent: December 8, 1998Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Paul Y. M. Shy
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Patent number: 5835172Abstract: A thin-film transistor liquid crystal display includes a substrate, an active layer on the substrate, having first and second impurity regions and first, second, and third non-impurity regions, gate insulating layer on the active layer, first and second electric field control layers on the second and third non-impurity regions, respectively, first and second subsidiary gate electrodes on the first and second electric field control layers, respectively, and a main gate electrode on the gate insulating layer, the main gate electrode contacting the first and second subsidiary gate electrodes and the first and second electric field control layers, respectively.Type: GrantFiled: June 13, 1997Date of Patent: November 10, 1998Assignee: LG Electronics, Inc.Inventors: Ju-Cheon Yeo, Sang-Gul Lee
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Patent number: 5821588Abstract: An object of the invention is to provide a transistor in which the channel length of the transistor is changed depending on voltages applied to plural gate electrodes which are dividedly formed, and plural kinds of operation states are attained. In a MOS transistor 31, a second gate electrode 36 is formed via an insulating film 35 on a first gate electrode 34 formed in a region E2. The channel length formed in a semiconductor substrate 32 is determined in accordance with the combination of voltages applied to the first and second gate electrodes 34 and 36. The MOS transistor 31 can operate in either of states of different threshold voltages.Type: GrantFiled: January 6, 1997Date of Patent: October 13, 1998Assignee: Sharp Kabushiki KaishaInventor: Tsutomu Ohmae
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Patent number: 5821560Abstract: A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gate electrode is narrower than a lateral length of the second gate electrode. Also, the first gate is electrically insulated from the active layer of semiconductor material by the first insulation layer so that the drain current saturates in a high drain voltage region.Type: GrantFiled: March 1, 1996Date of Patent: October 13, 1998Assignees: TKD Corporation, Semiconductor Energy Laboratory Co., Ltd.Inventors: Michio Arai, Kazushi Sugiura, Ichiro Takayama, Yukio Yamauchi, Isamu Kobori, Mitsufumi Codama, Naoya Sakamoto
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Patent number: 5808341Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.Type: GrantFiled: November 12, 1996Date of Patent: September 15, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Yasuo Yamaguchi, Il Jung Kim, Yasuo Inoue, Shigeto Maegawa, Takashi Ipposhi