Abstract: A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

Abstract: The present disclosure discloses an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer. The carrier-free region is not disposed below the gate electrode, but is disposed outside the corresponding region of the gate electrode in the channel layer, and the threshold voltage of the device can be regulated by regulating the width and number of the carrier-free region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, and a gate electrode. The source region and the drain region are in the substrate, and the gate electrode is partly buried in the substrate and between the source region and the drain region.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.

Abstract: A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region. The first insulating layer is provided around at least a portion of the first semiconductor region and at least a portion of the second semiconductor region. The first insulating layer contacts the second semiconductor region. The first insulating region is provided around at least a portion of the first insulating layer.

Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone having a surface formed in the substrate adjacent to the first well zone, a gate oxide formed on the first well zone and the second well zone of the substrate, a gate formed on the gate oxide, a channel formed in the first well zone underneath the gate oxide, an accumulation region formed in the second well zone underneath the gate oxide adjacent to the channel, wherein only a part of the accumulation region is implanted with a dopant to form an implant region therein, and an insulation region formed on the surface of the second well zone of the substrate adjacent to the accumulation region, wherein a boundary is formed between the insulation region and the accumulation region.

Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

Abstract: A nitride semiconductor device includes: a stacked structure portion having an active region; first and second main electrodes extending in a first direction; and a lead-out line (second lead-out line) electrically connected to the second main electrode and extends to one side in the first direction. The first main electrode has a first tip at an end which is on the side to which the lead-out line extends. The second main electrode has a second tip at an end which is on the side to which the lead-out line extends, and has, at a second tip-side in the first direction, a tapered portion having a width in a second direction which decreases with decreasing distance to the second tip. The lead-out line has a region projecting in the second direction from the tapered portion, and the first tip does not project further in the first direction than the second tip.

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract: A stack of MTJ layers is provided on a substrate comprising a bottom electrode, a pinned layer, a tunnel barrier layer, a free layer, and a top electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on its sidewalls. A dielectric spacer is formed on the MTJ device. The dielectric spacer is etched away on horizontal surfaces wherein the dielectric spacer on the sidewalls is partially etched away. The remaining dielectric spacer covers the pinned layer and bottom electrode. The dielectric spacer is removed from the free layer or is thinner on the free layer than on the pinned layer and bottom electrode. Sidewall damage is thereafter removed from the free layer by applying a horizontal etching to the MTJ device wherein the pinned layer and bottom electrode are protected from etching by the dielectric spacer layer.

Abstract: There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer.

Abstract: A magnetoresistive random-access memory (MRAM) cell with a dual sidewall spacer structure is provided. The MRAM cell includes an anti-ferromagnetic layer, a pin layer, a free layer, a first sidewall spacer layer, and a second sidewall spacer layer. The pin layer is arranged over the anti-ferromagnetic layer and has a fixed magnetic polarity. The free layer is arranged over the pin layer and has a variable magnetic polarity. The first sidewall spacer layer extends from over the pin layer along sidewalls of the free layer. The second sidewall spacer layer extends from over the anti-ferromagnetic layer along sidewalls of the pin layer and the first sidewall spacer layer. A method for manufacturing the MRAM cell is also provided.

Abstract: An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate structure extending completely around the first semiconductor structure in a plan view. An outermost perimeter of the gate structure comprises a first protruding arcuate section interposed between linear sections, the first protruding arcuate section aligned with the first semiconductor structure.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract: Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: Systems, apparatus, and associated methods of forming the systems and/or apparatus may include imaging devices that may comprise multiple arrays of ultrasonic transducer elements for use in a variety of applications. These multiple arrays of ultrasonic transducer elements can be arranged to form a three-dimensional imaging device. Non-coplanar arrays of ultrasonic transducer elements can be coupled together. These imaging devices may be used as medical imaging devices. Additional apparatus, systems, and methods are disclosed.

Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.

Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.

Abstract: A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.

Abstract: Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination region is two thirds of pitch between n drift region and p partition region of a first parallel pn layer in an active region. At boundaries between main SJ cells and fine SJ cells at four corners of the semiconductor substrate having rectangular shape in plan view, ends of two pitches of main SJ cells face the ends of three pitches of fine SJ cells. In this way, it is possible to reduce the influence of a process variation and thus reduce mutual diffusion between n drift region and p partition region of the fine SJ cell.

Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

Abstract: There is provided a light emitting diode package and a method of manufacturing the same. A light emitting diode package according to an aspect of the invention may include: an LED chip; a body part having the LED chip mounted thereon; a pair of reflective parts extending from the body part to face each other while interposing the LED chip therebetween, and reflecting light emitted from the LED chip; and a molding part provided between the pair of reflective parts to encapsulate the LED chip and having a top surface whose central region is curved inwards.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.

Abstract: A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type, a second region of a second conductivity type; and a third region of the first conductivity type. The third region is electrically connected to the second contact. A semiconductor zone of the second conductivity type and increased doping density is arranged in the second region. The semiconductor zone separates a first part of the second region from a second part of the second region. The semiconductor zone has a maximum doping density exceeding about 1016 cm?3 and a thickness along the direction from the first contact to the second contact of less than about 3 ?m.

Abstract: A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches.

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.