Abstract: A semiconductor device providing an improved effect of suppressing variation with time of reverse breakdown voltage applied to PN junction, particularly, a voltage-regulator device, is provided. The semiconductor device includes an impurity diffusion layer 15 formed on a surface of a certain-conductivity-type semiconductor substrate or well, the impurity diffusion layer having a conductivity opposite to that of the semiconductor substrate or well, and a device separating insulation film 12 formed at a distance from the impurity diffusion layer, and a distance between an end of the impurity diffusion layer and an end of the device separating insulation film is defined to be not less than 1.2 &mgr;m.

Abstract: A semiconductor structure which protects against damages to an integrated circuit caused by electrostatic discharge (ESD) at a power supply pin includes a channel stop field plate coupled between a power supply terminal associated with the power supply pin and contacts to N-type substrate or N-wells formed in the semiconductor structure receiving the power supply voltage. The field plate functions to inhibit surface leakage current and is also used to introduce a resistance between the power supply pin and connections to N-wells or the N-substrate, thereby providing protection to the wells or substrate against damages caused by an ESD event. By exploiting an existing structure used in typical integrated circuit for ESD protection, ESD immunity of a semiconductor device can be enhanced without consuming additional silicon area.

Abstract: A lateral high voltage semiconductor device having a sense terminal and a method for sensing a drain voltage of the same are provided. Specifically, the present invention relates to a thin layer, high voltage, lateral silicon-on-insulator (SOI) device having a field plate terminal that is disconnected from a source terminal. By measuring voltage or current on the separate field plate terminal, the drain voltage of the device can be sensed. This sensing capability is a protection scheme against overstress voltage conditions.

Abstract: A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.

Abstract: A CMOS SRAM cell with prescribed power-on data state having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (T1/T2; T3/T4) serially connected between Vdd and circuit ground to form a first inverter with a first data node (A) between the two transistors (T1/T2) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (B) between the two transistors (T3/T4) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (T5) is connected between a bit line (BL) and the first data node (A) and another access transistor (T6) is connected between a complementary bit line (BLC) and the second data node (B) to provide data access thereto.

Abstract: A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between Vdd and circuit ground to form a first inverter with a first data node (1) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (2) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node (1) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation.

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: The invention concerns an integrated circuit, including a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, and the overvoltage protection circuit includes means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means include two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: A semiconductor device has a PN junction between first and second regions of the device in which in the intended operation of the device reverse breakdown of the junction occurs. The first region is of lower impurity concentration than the second region and a first buried region of the same conductivity type as and of higher impurity concentration than the first region is provided in the first region adjacent to the junction. A second buried region of the same conductivity type as and of higher impurity concentration than the first buried region is provided in the first buried region and one of the first and second buried regions is formed with a plurality of separate regions of small area arranged so that reverse breakdown of the junction preferentially occurs through the second buried region.

Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure contiguous with the well region, a second isolation structure contiguous with well region and spaced apart from the first isolation structure, a dielectric layer disposed over the well region and the first and second isolation structures, and a layer of silicon, formed over the dielectric layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion, and a second n-type portion contiguous with the second p-type portion, wherein at least a portion of the first p-type and first n-type portions overlap the first isolation structure and at least a portion of the second p-type and second n-type portions overlap the second isolation structure.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor layer, a drain offset diffusion region, a source diffusion region, a drain diffusion region, a buried diffusion region of a first conductivity type that is buried in the drain offset diffusion region, at least one plate electrode in a floating state formed on a field insulating film, and a metal electrode that is formed on an interlayer insulating film positioned on the plate electrode and a part of which is electrically connected to the drain diffusion region and that is capacitively coupled to the plate electrode.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract: A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (3) when the diode is reverse biased, so permitting a higher doping (12) to be used for the intermediate drift region (3) for a given breakdown voltage. This improves both the turn-on and turn-off characteristics of the diode.

Abstract: A method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.

Abstract: Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over al the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration.

Abstract: The diode of the present invention includes: a cathode electrode and an anode electrode that are disposed on a semi-conductor substrate and are spaced apart from each other; and a shielding metal member placed between the cathode and anode electrodes.

Abstract: To isolate at least one electric or electronic element (6, 58), for example an interconnection integrated onto a semiconductor substrate (12), this device comprises at least one isolation means chosen from an isolating layer (84, 86, 90) extending in the substrate and an assembly whose height exceeds that of the element and which comprises, on either side of the element, at least two superposed conductors (60 62 64, 66 68 70), which are integrated into the substrate and extend along the element.

Abstract: A high-quality diode is formed in an SOI process, using standard steps and implant doses that are used in the process for other devices such as a FET and a buried resistor; in particular using a buried resistor mask and implant to form one side of the diode, using the FET gate oxide to terminate the P-N junction, and using the FET gate to protect the junction from shorting during the silicide step.

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100>direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract: A semiconductor device which comprises an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region comprises at least a gate dielectric; and an overvoltage control network coupled to the gate dielectric of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said gated device.

Abstract: The invention concerns an integrated circuit, comprising a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means comprise two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: A power field effect transistor includes a bulge portion and/or a constricted portion in at least one of the heavily doped drain contact region and the lightly doped channel forming region, and heavily doped source regions are formed in the lightly doped channel forming region at intervals, wherein the avalanche breakdown takes place at the bulge portion and/or the constricted portion due to the concentration of electric field in the presence of excess voltage applied to the heavily doped drain contact region, and the breakdown current flows through the gaps between the heavily doped source regions so that a emitter-base junction of a parasitic bipolar transistor is not strongly biased.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering.

Abstract: A surface voltage sustaining structure for semiconductor device which includes at least one high-side high-voltage device, comprises at least two surface voltage sustaining regions, wherein a first surface voltage sustaining region is for sustaining a voltage drop from a high voltage terminal of the high-side high-voltage device to a floating voltage terminal of the high-side high-voltage device, and a second surface voltage sustaining region is for sustaining a voltage drop from said high voltage terminal or from said floating voltage terminal to the substrate. The potential of the floating-voltage terminal of the high-side high-voltage device can vary (float) from the potential of the substrate up to the potential of the high voltage terminal.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: On a semiconductor integrated circuit chip, multiple equipotential power-line conductors are provided to supply power to circuit elements. First protecting elements are provided for interconnecting the power-line conductors for protecting the circuit elements. A number of input/output pads are also connected to the power-line conductors via second protecting elements. The arrangement is such that the contact positions of any of the first protecting elements and any of the second protecting elements on the power-line conductors are nearer to respective end portions of the conductors than the contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: An isolation structure capable of preventing deterioration of breakdown voltage of a semiconductor device is obtained. The isolation structure, positioned between first and second conductive regions formed on a major surface of a semiconductor substrate for electrically insulating the first and second conductive regions from each other, includes a first conductor formed on a position deeper than the major surface of the semiconductor substrate, an insulator positioned in a direction opposite to that of the position of the first conductive region as viewed from the first conductor and formed on a position deeper than the major surface of the semiconductor substrate and a second conductor positioned in a direction opposite to that of the position of the first conductor as viewed from the insulator and formed on a position deeper than the major surface of the semiconductor substrate.

Abstract: A device for limiting an alternating electric current includes a least one passive semiconductor configuration and a protection circuit. The semiconductor configuration is configured such that when a forward voltage is applied thereto, a forward current flows through the semiconductor configuration. The forward current increases monotonously with the forward voltage up to a saturation current at an associated saturation voltage. At a forward voltage above the saturation voltage, the forward current is limited to a limiting current that is smaller than the saturation current. The semiconductor configuration is further configured such that when a reverse voltage is applied, a reverse current flows through the passive semiconductor configuration.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

Abstract: An electrostatic discharge protective circuit under an input pad. The electrostatic discharge protective circuit has at least a MOS, wherein the MOS comprises a drain region, a gate structure and a source region. A metal silicon layer is on the gate structure and the source region, wherein the gate structure and the source region are coupled to each other through the metal silicon layer. A dielectric layer is over the drain region, the gate structure and the source region. A metal layer is over the dielectric layer. A via plug is in the dielectric layer, wherein the drain and the conductive layer are coupled to each other through the via plug. An input pad is over the MOS, wherein the metal layer is coupled to an input port and an internal circuit through the input pad.

Abstract: The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region.

Abstract: The breakdown strength of a lateral diode using a field plate is improved. There are provided a track-like first field plate connected to an anode electrode, a track-like second field plate formed outside the first field plate and connected to a cathode electrode, track-like third field plates provided concentrically between the first and second field plates, and fourth field plates provided so as to cross the first to third field plates and connected to each of them. The fourth field plates are so positioned that they allow more current to flow in the corner sections and under the electrodes where an electric field is liable to concentrate.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate. The split gate flash memory is fabricated using a process comprising the steps of: (a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein the floating gate is etched to have a reentrant angle such that its width generally increases with a distance from the substrate; (b) forming a CVD nitride spacer on the floating gate using a CVD nitride deposition, then anisotropic etching the CVD nitride to form a nitride spacer adjacent to the floating gate; (c) forming a control gate on the floating gate wherein the control gate and the floating gate are separated by the poly oxide and the nitride spacer; and (d) forming a source and drain in the substrate using a source and drain implantation.

Abstract: A semiconductor integrated circuit device has macrocells composed of CMOS transistors. In a first wiring layer of the macrocells, a power source line coupled to the sources of P-channel MOS transistors and a ground line coupled to the sources of N-channel MOS tranistors are formed so as to extend in a first direction. In a second wiring layer of the macrocells, a power supply line connected to the power source line, a ground voltage supply line connected to the ground line, a first bias line for feeding a bias to the N well for the P-channel MOS transistors, and a second bias line for feeding a bias to a semiconductor substrate are formed recurrently so as to extend-in a second direction perpendicular to the first direction.

Abstract: A polysilicon load structure and its manufacturing method for static random access memory, comprising the steps of first providing a semiconductor substrate, and then forming a first insulating layer over the substrate. Next, a trench is etched out from the insulating layer forming a step structure. Thereafter, a polysilicon layer is formed over the first insulating layer, and then a global ion implantation operation is performed. Next, a photoresist layer is formed over the polysilicon layer, and then a connector pattern is defined using a microlithographic process. Thereafter, the polysilicon layer is anisotropically etched to form a spacer on the sidewall of the trench. Subsequently, a second ion implantation is performed to adjust the resistance of the connector. Finally, microlithographic and etching processes are used to remove the unwanted portions of the polysilicon spacer and exposing the polysilicon spacer structure and the polysilicon connector structure.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral MOS device on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and over at least a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A zapping diode concerned with a P-N junction diode provided in an integrated circuit, whose P-N junction is subjected to breakdown by an overvoltage to perform fine adjustment in the value of capacitance or resistance involved in the circuit. The diode has a first impurity region of a first conductivity type formed in a first conductivity type semiconductor region, a second impurity region, an interlayer insulation film formed over the semiconductor region, and a third conductor film formed on the semiconductor region between the first and second impurity region. The third conductor film, when applied by a reverse-bias voltage, controls the direction of breakdown in the P-N junction to thereby provide a consistent value of residual resistance.

Abstract: Silicon is formed at selected locations on a silicon-on-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

Abstract: Disclosed is a semiconductor device, comprising a substrate having a first region and a second region surrounding the first region, a MOS transistor formed in the first region, a first conductive layer formed in the first region and constituting the lower layer of a two-layered gate electrode of the MOS transistor, a second conductive layer for isolation, the second conductive layer being formed in the second region and having an upper surface whose level is lower than that of the upper surface of the first conductive layer, a first insulating layer formed between the first and second regions, a second insulating layer formed on the second conductive layer, and a third conductive layer formed over the first conductive layer and the second insulating layer and constituting the upper layer of the two-layered gate electrode of the MOS transistor.

Abstract: A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.

Abstract: An improved transistor structure includes an insulated conductive gate spacer which is contacted and driven separately from the gate of the transistor. The gate spacer serves as a control or second gate for the transistor and may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistor are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistor is used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors using the gate spacers in a conventional manner.

Abstract: An integrated polysilicon diode contact having multiple doped layers. A first highly doped layer of a first dopant type is deposited on a silicon substrate. A second highly doped layer of a second, different dopant type is deposited on the substrate, separated by a spacer from the first highly doped layer. A third lower doped layer of the second dopant type is deposited on the first highly doped layer and second highly doped layers, the third lower doped layer forming a p-n junction with a source region having a dopant of the first type.

Abstract: An avalanche breakdown diode includes a p-doped trough in which a highly p-doped region is introduced. In addition to the trough, an n-doped region is introduced, which is underlaid by a p-doped layer. The trough and the p-doped layer define a precisely established interspace. The arrangement is introduced into a p-type substrate. An insulating layer and thereon, in turn, a conductive layer are applied over the region between the trough and the p-doped layer. The conductive layer and the n-doped region are connected to a positive voltage and the highly p-doped region is connected to a negative voltage. A drift of the breakdown voltage is thereby prevented. In addition, the resistance during the breakdown is small due to the defined interspace between the trough and the layer.

Abstract: A semiconductor device includes a diode element for protecting a transistor against an overvoltage. A first region of p-type conductivity is formed on an upper surface of an n-type semiconductor substrate in which base and emitter regions of the transistor are formed. A second region of n.sup.+ -type conductivity whose impurity concentration is higher than that of the n-type semiconductor substrate is formed on its upper surface to be spaced apart from the first region. An insulating film is formed to cover the upper surface of the semiconductor substrate. Furthermore, a conductive film is formed to partially overlap the first and second regions through the insulating film. The first region serves as an anode, the second region serves as a cathode, and the conductive film serves as a gate electrode; thus an overvoltage protection diode is obtained.