Abstract: The present invention provides a semiconductor device which is excellent in voltage sense characteristic and simple in manufacturing process. P diffusion regions 12 and 13 are selectively formed on a first major surface of an N.sup.- substrate 11, an electrode 31 is formed on the P diffusion region, a sense electrode 32 is formed on the P diffusion region 13, and an electrode 33 is formed on a second major surface of the N.sup.- substrate. Then, the electrode 31 is set at 0 V, constant current is led to the sense electrode 32, and the electrode 33 is positively biased. Thus, the voltage applied to the electrode 33 is sensed from a potential obtained at the sense electrode 32. A distance between the P diffusion regions 12 and 13 which determines a voltage sense characteristic can be accurately controlled, and a good voltage sense characteristic can be obtained. Moreover, a manufacturing process is relatively simple.

Abstract: A power diode having substantially no reverse-recovery time and relatively high conductance. The power diode is a majority carrier semiconductor having a structure that is similar to that of a metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate, and a body. In one embodiment, to increase conductance of the power diode, a linked-cell configuration that reverses the geometry of a conventional cell-type MOSFET is employed, thereby increasing the width of a conductance channel over that of a conventional MOSFET, and compensating for a relatively low level of inversion in the channel region. Negative and positive feedback circuits are used to further improve the conductance of the power diode by dynamically setting a bias voltage applied between the gate and the source to a level just below a threshold voltage.

Abstract: A semiconductor device with a semiconductor body (1) includes a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which includes a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e.

Abstract: A field plate avalanche diode has a field plate extending over the breakdown PN junction.

Abstract: This application is directed to an improved thin film SOI device in which a gate region extends over a thin layer of silicon having a lateral linear doping region on a buried oxide layer. The gate region of this invention includes a gate electrode and a field plate extending laterally from the gate electrode over the lateral linear doping region.

Abstract: A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.

Abstract: An insulated gate controlled avalanche bipolar transistor has a heavily doped (with doping of at least 1.times.10.sup.18 cm.sup.-3) substrate and a lightly doped channel layer of the same conductivity type on the substrate. The source/emitter and drain/collector regions extend through the lightly doped surface layer to reach the heavily doped substrate, so that the junction between the drain and the heavily doped substrate promotes avalanche breakdown. A lightly doped region of the same type as the substrate is provided betwen the heavily doped substrate and the contact to the substrate, to provide a resistance between the substrate, which acts as the base of the transistor, and the substrate contact, to permit biasing of the base by resistive voltage drop across the resistance, while the lightly doped channel layer permits a low FET threshold voltage.

Abstract: In a MOS type LSI comprising an n channel-open-drain-transistor capable of connecting with an analog IC driven by a high voltage, a surge breakdown voltage and a drain breakdown voltage of the open-drain-transistor is increased, and hence the reliability is increased. An n channel-open-drain-transistor includes a ring-shaped gate electrode and a drain region. A drain region is surrounded by a gate electrode. Drain region includes an n.sup.- region and an n.sup.+ region. An n channel MOS transistor includes a gate electrode and a drain region. Drain region includes an n.sup.- region and an n.sup.+ region. An impurity concentration of n.sup.- drain region of the n channel-open-drain-transistor is higher than an impurity concentration of n.sup.- drain region of the n channel MOS transistor.

Abstract: It is usual in high-voltage integrated circuits to provide one or several breakdown-voltage-raising rings at the edge of a high-voltage island in the form of surface zones of the conductivity type opposite to that of the island. According to the invention, the function of these rings is locally taken over by one or several zones forming part of a circuit element and also provided with a breakdown-voltage-raising edge. Since the breakdown-voltage-raising zones are locally omitted alongside the island insulation, a major space saving can be achieved.

Abstract: A semiconductor body (2) has adjacent a first major surface (3) a first region (5) of one conductivity type part of which defines an active device area (6) of a power semiconductor device (7) having at least two electrodes (8 and 9 or 8 and 10) and active device regions (11) each forming with the first region (5) a pn junction (11a) extending to the first major surface (3). A protection device (12) formed by a series-connected array of semiconductor rectifying elements (13) is provided on an insulating layer (14) on the first major surface (3). The protection device (12) is connected between at least two electrodes (8 and 9 or 10) of the power semiconductor device (7) so as to break down to cause conduction between the two electrodes when the voltage across the protection device (12) exceeds a predetermined limit.

Abstract: A voltage limiting device having gate and drain electrodes that include a serpentine configuration to form a pattern of breakdown corners at the traversals of the gate electrode over the drain electrode. The serpentine configuration may define a plurality of fingers. The number of breakdown corners determines the current-voltage (I-V) characteristics of the voltage limiting device. Either one of the gate electrode or the drain electrode may be configured in a manner to provide repeated traversals of one electrode over the other.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating region over the extended drain region is formed. A gate region is formed on a surface of the substrate. A first side of the gate region is adjacent to a first end of the extended drain region. A drain region of the first conductivity type is formed. The drain region is in contact with a second end of the extended drain region. A source region is formed on a second side of the gate region.

Abstract: An integrated circuit has an input, a terminal for a reference potential, and a semiconductor substrate. An input protection structure for the integrated circuit is disposed in the semiconductor substrate and is connected between the input and the terminal for a reference potential. The input protection structure includes at least one transistor and an integrated diode. The at least one transistor has a collector in the form of a buried zone connected to the input, an emitter in the form of at least one doped zone to be connected to the reference potential, the collector and emitter defining a collector-to-emitter path, and a base in the form of at least one doped zone being insulated except for electrical contact with the emitter and the collector. The integrated diode is formed by at least the buried zone and the semiconductor substrate and is connected parallel to the collector-to-emitter path of the transistor.

Abstract: A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and connected to a bit line, an insulation film in which carrier traps are formed, and a gate electrode that is opposite the high-concentration impurity region across the insulation film and connected to a word line. Carriers are captured by, and released from, the carrier traps formed in the insulation film, in response to bias voltages applied to the word and bit lines. Information stored in the memory cell depends on whether or not the carrier traps are holding carriers. The information is read out of the memory cell as the difference of a tunneling current flowing between the semiconductor substrate and the high-concentration impurity region.

Abstract: A metal insulated semiconductor field effect transistor (MIS-FET) includes a substrate, a semiconductor layer, and an oxide film on the semiconductor layer. Source and drain regions are formed by doping the semiconductor layer with impurities. A gate electrode is formed on the oxide film between the source and drain regions. An electrode is provided on the opposite side of the drain region from the gate electrode without contacting the gate electrode. The electrode is connected to either the source region or the substrate. Thus, a high strength against static electricity is performed without using a large area on the chip.