Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate, a conductive plate of a first metal layer over the substrate, a first resistor material of a resistor layer over the conductive plate, a high-K material formed between the first resistor material and the conductive plate, a first conductive line of a second metal layer over the resistor layer, and a first via formed between the first conductive line and the first resistor material. The conductive plate, the first resistor material and the high-K material form a capacitor between the first and second metal layers. The first distance between the first resistor material and the conductive plate is less than the second distance between the first resistor material and the first conductive line.

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.

Abstract: A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract: A method and device for laser-induced marking. The method comprises providing an article having a marking surface including a non-flat area, providing a first laser transfer foil, providing a first laser unit for emitting first laser light, providing a first hard adaptor that is essentially transparent to the first laser light, the first hard adaptor having a contacting surface that essentially is a negative of at least a part of the marking surface of the article, contacting the first laser transfer foil with the marking surface of the article by the first hard adaptor such that the first laser transfer foil is arranged between the marking surface of the article and the contacting surface of the first hard adaptor, and irradiating the first laser light through the first hard adaptor onto the first laser transfer foil.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A device includes a source/drain region, a gate electrode, and an intra-connection structure. The gate electrode has a top surface, a bottom surface that is opposite to the top surface thereof, and a sidewall that extends between the top and bottom surfaces thereof. The intra-connection structure is coupled electrically to the source/drain region and the sidewall of the gate electrode. A method for fabricating the device is also disclosed.

Abstract: A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A method includes forming an insulating carrier substrate, forming a shallow trench isolation region within the insulating carrier substrate, and forming a plurality of gate recesses on the shallow trench isolation region. The plurality of gate recesses is formed by forming a plurality of dummy gates on the shallow trench isolation region and etching the plurality of dummy gates. The method further includes depositing a metal resistor layer within the plurality of gate recesses.

Abstract: It is an objective to improve reverse surge withstand capability of a semiconductor device, for example, a Schottky barrier diode. A p-type semiconductor section 14 includes a p+ type semiconductor portion (first concentration portion) 14a and a p? type semiconductor portion (second concentration portion) 14b, which have different impurity concentrations from each other. Additionally, a part of a side surface 13S of a metal portion 13 and a part of a bottom surface 13B of the metal portion 13 connected to the side surface 13S thereof are in contact with a part of the p+ type semiconductor portion 14a. Further, at least a part of a side surface 14bS of the p? type semiconductor portion 14b is in contact with a side surface 14aS of the p+ type semiconductor portion 14a.

Abstract: A method for forming a FinFET device is provided. The method includes providing a substrate having a first region and a second region; and forming a plurality of fins on the substrate. The method also includes forming a plurality of doping regions with different doping concentrations in the fins in the first region; and forming a plurality of dummy gate structures over the plurality of fins. Further, the method includes forming source and drain regions in the plurality of fins at both sides of the dummy gate structures; and removing the dummy gate structures to form a plurality of openings to expose the plurality of fins. Further, the method also includes forming a plurality of work function layers with different work functions on the exposed fins in the openings in the second region; and forming gate structures in the openings.

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract: A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.

Abstract: Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (STI) structure disposed therein. A dummy gate electrode structure is patterned overlying semiconductor material of the semiconductor substrate, and a resistor structure is patterned overlying the STI structure. The dummy gate electrode structure and the resistor structure include a dummy layer overlying a metal capping layer. A gate dielectric layer underlies the metal capping layer. An interlayer dielectric layer is formed overlying the semiconductor substrate and the STI structure. End terminal recesses for the resistance element are concurrently patterned through the dummy layer of the resistor structure along with removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion.

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer. A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.

Abstract: A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.

Abstract: A multi-wavelength semiconductor laser device includes a block having a V-shaped groove with two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.

Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

Abstract: A polysilicon film that serves as a resistance element is formed. The polysilicon film is patterned to a predetermined shape. CVD oxide films covering the patterned polysilicon film are etched thereby removing the portion of the CVD oxide film where the contact region is formed, leaving the portion covering the portion of the polysilicon film that serves as the resistor main body. BF2 is implanted by using the portions of the remaining CVD oxide films covering the polysilicon film as an implantation mask thereby forming a high concentration region in the contact region.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.