Matrix Or Array Of Field Effect Transistors (e.g., Array Of Fets Only Some Of Which Are Completed, Or Structure For Mask Programmed Read-only Memory (rom)) Patents (Class 257/390)
  • Patent number: 11171143
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin and a second dielectric fin over a substrate. The first semiconductor fin is between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode wrapping the first dielectric fin, a channel region of the first semiconductor fin and the second dielectric fin and a first source/drain structure over a source/drain portion of the first semiconductor fin, being in contact with and interposing the first dielectric fin and the second dielectric fin.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11158604
    Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 26, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Weihua Cheng, Jun Liu
  • Patent number: 11152392
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-boong Lee, Jong-hoon Jung
  • Patent number: 11114437
    Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 7, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 11088151
    Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Chia-En Huang, Yen-Huei Chen, Yih Wang
  • Patent number: 11074962
    Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 11069632
    Abstract: The present disclosure provides an array substrate. The array substrate includes a plurality of shielding layers disposed on a glass substrate and arranged at intervals; a dielectric layer spread on the glass substrate and covering the shielding layers, wherein the dielectric layer includes a plurality of dielectric patterns, the dielectric patterns include main dielectric patterns and auxiliary dielectric patterns disposed on at least one side of the main dielectric patterns; and a gate insulating layer disposed on the dielectric layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 20, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chao He
  • Patent number: 11043490
    Abstract: A semiconductor device includes a dielectric dummy gate, a plurality of first semiconductor fins, and a plurality of second semiconductor fins. The dielectric dummy gate extends along a first direction. The first semiconductor fins extend along a second direction within a first core circuit region on a first side of the dielectric dummy gate, and the second direction is substantially perpendicular to the first direction. The second semiconductor fins extend along the second direction within a second core circuit region on a second side of the dielectric dummy gate opposite the first side of the dielectric dummy gate. A number of the second semiconductor fins within the second core circuit region is less than a number of the first semiconductor fins within the first core circuit region, and each of the second semiconductor fins has a width less than a width of each of the first semiconductor fins.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11037633
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Randy J. Koval, Hiroyuki Sanda
  • Patent number: 11031082
    Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 8, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Roberto Simola
  • Patent number: 11011429
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Patent number: 10998437
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pr
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuya Nishiwaki, Hideharu Kojima, Yoshiharu Takada, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Shingo Sato
  • Patent number: 10991289
    Abstract: The present disclosure is related to a memory-in-pixel circuit. The memory-in-pixel circuit comprises a switch sub-circuit, and a data input sub-circuit. The data input sub-circuit comprises a first floating gate transistor and a second floating gate transistor. The data input sub-circuit is configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 27, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangliang Shang, Chengyou Han, Mingfu Han, Lijun Yuan, Xing Yao, Haoliang Zheng
  • Patent number: 10978464
    Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
  • Patent number: 10978484
    Abstract: In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10964683
    Abstract: A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 10964782
    Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 30, 2021
    Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
  • Patent number: 10910378
    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 2, 2021
    Inventors: Kiseok Lee, Bong-Soo Kim, Jiyoung Kim, Hui-Jung Kim, Seokhan Park, Hunkook Lee, Yoosang Hwang
  • Patent number: 10902914
    Abstract: A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 26, 2021
    Assignee: CYBERSWARM, INC.
    Inventors: Viorel-Georgel Dumitru, Cristina Besleaga Stan, Alin Velea, Aurelian-Catalin Galca
  • Patent number: 10853552
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
  • Patent number: 10854297
    Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 1, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Cheng-Ying Wu, Cheng-Yu Chung, Wen-Chien Huang
  • Patent number: 10804135
    Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, a dummy gate structure being formed on the base, a source/drain doping region being formed in the base on both sides of the dummy gate structure, a dielectric layer being formed on the base exposed by the dummy gate structure, and the dielectric layer covering the source/drain doping region; etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region; forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region; after forming the contact plug, removing the dummy gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening. Embodiments of the present disclosure are advantageous to simplify process complexity and increase process windows.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 13, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhang Chenglong, Cui Long
  • Patent number: 10790305
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-Boong Lee, Jong-Hoon Jung
  • Patent number: 10777572
    Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Euntaek Jung, JoongShik Shin, JiHye Yun
  • Patent number: 10748814
    Abstract: A semiconductor device and fabrication method thereof are provided. The method includes: providing a base substrate with first gate structures on the base substrate; forming a spacer covering sidewalls of each first gate structure; forming sacrificial layers on sides of each first gate structure to cover corresponding spacers; forming a bottom dielectric layer covering sidewalls of the sacrificial layers; after forming the bottom dielectric layer, removing the sacrificial layers by etching to form first openings between the bottom dielectric layer and the spacer; and forming a plug in each first opening.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 18, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10706945
    Abstract: A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.
    Type: Grant
    Filed: September 9, 2018
    Date of Patent: July 7, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10707451
    Abstract: The present disclosure provides an organic light-emitting diode (OLED) substrate and a method for manufacturing same. The method includes providing a substrate that includes a non-pixel area, a first pixel area, a second pixel area, and a third pixel area; forming a first sacrificial layer in the first pixel area and the second pixel area, forming a third light-emitting material layer on the substrate, and removing the first sacrificial layer, so as to form a third pixel area organic layer; and using the same steps to form a second pixel area organic layer and a first pixel area organic layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Yamei Bai
  • Patent number: 10700072
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Balseanu, Ning Li, Sanjay Natarajan, Gill Yong Lee, In Seok Hwang, Nobuyuki Sasaki, Sung-Kwan Kang
  • Patent number: 10658374
    Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
  • Patent number: 10651189
    Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10580507
    Abstract: To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.
    Type: Grant
    Filed: September 9, 2018
    Date of Patent: March 3, 2020
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10560475
    Abstract: The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 11, 2020
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10541028
    Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10535720
    Abstract: Disclosed herein is an organic light emitting diode (OLED) lighting device capable of expressing characters or drawings with various colors. The OLED lighting device according to aspects of the present disclosure includes a thermochromic pattern arranged inside or outside of a substrate, the thermo chromic pattern having a property of changing a color thereof according to a change in temperature. By applying a reversible thermochromic pattern, which may maintain or lose an original color thereof according to a temperature change, to the inside or outside of the substrate, it is possible to express characters and drawings with various colors without designing a processing pattern inside the substrate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: January 14, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jungeun Lee
  • Patent number: 10529801
    Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
  • Patent number: 10530377
    Abstract: A current digital to analog converter (DAC) including an offset array including a plurality of unit cells of a first size, and a trimming array including a plurality of unit cells having the first size and a plurality of half cells, wherein the half cells have a larger size than the plurality of unit cells.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 7, 2020
    Assignee: NXP B.V.
    Inventor: Xu Zhang
  • Patent number: 10489590
    Abstract: The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 26, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10460131
    Abstract: A storage device comprising a memory, a controller, and a host interface operative to connect with a host. The memory containing data locations access to which are controllable by a protection application which is executable on a host. When the host interface operatively coupled to a host data locations in the memory are accessible to an operating system of the host only under permission from the protection application. The controller communicates with the protection application running on the host for allowing the protection application access to data locations in the memory. Upon a host request for access to a data location, the controller determines if permission to access the requested data location is acquired from the protection application. The permission is based on determination of the protection application that the data location does not contain malicious data harmful to the host operating system, to any application and/or to any data on the host.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eyal Sobol, Nir Ofek Paz
  • Patent number: 10453531
    Abstract: A content addressable memory element is provided that includes a vertical transistor including a first electrode coupled to a match line, a second electrode coupled to a ground line, a first gate electrode coupled to a search line, and a second gate electrode coupled to a complementary search line. The first gate electrode and the second gate electrode are disposed on opposite sides of the vertical transistor, and the vertical transistor includes a charge storage memory element.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventor: Christopher J. Petti
  • Patent number: 10410723
    Abstract: A nonvolatile memory (NVM) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a P-N diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the P-N diode are coupled to the second coupling capacitor and the word line, respectively. The first and second connection lines are coupled in parallel between the word line and the floating gate.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Sung Kun Park
  • Patent number: 10397215
    Abstract: A device binding system includes generating and storing at the device a unique identifier based on device characteristics and a cryptographic function. The unique identifier is then registered with an authority. The self-generation of the unique identifier allows binding with an authority to occur after the device leaves a secure manufacturing environment or even after the device is in the hands of an end-user consumer. Once the binding occurs, the device can be part of trusted transactions for location tracking, fitness tracking, financial transactions or other interactions where identity and privacy are factors.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: VISA INTERNATIONAL SERVICE ASSOCATION
    Inventors: Marc Kekicheff, Kiushan Pirzadeh, Yuexi Chen
  • Patent number: 10396086
    Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
  • Patent number: 10388663
    Abstract: A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Soo-Nam Jung
  • Patent number: 10387500
    Abstract: A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Bum Hong, Chang Min Hong
  • Patent number: 10373686
    Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 6, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Mark Reiten
  • Patent number: 10354952
    Abstract: A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10340261
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10332873
    Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Toshinao Ishii, Yasuhiko Tanuma
  • Patent number: 10325923
    Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. The methods further include placing sacrificial polysilicon around the memory hole before forming the bottom stack and removing the sacrificial polysilicon from the slit trench to allow a conducting gapfill to make electrical contact to the polysilicon inside the memory hole.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 18, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Vinod R. Purayath
  • Patent number: 10311947
    Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stephen Tang