Abstract: A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.

Abstract: The present disclosure provides an organic light-emitting diode (OLED) substrate and a method for manufacturing same. The method includes providing a substrate that includes a non-pixel area, a first pixel area, a second pixel area, and a third pixel area; forming a first sacrificial layer in the first pixel area and the second pixel area, forming a third light-emitting material layer on the substrate, and removing the first sacrificial layer, so as to form a third pixel area organic layer; and using the same steps to form a second pixel area organic layer and a first pixel area organic layer.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

Abstract: To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.

Abstract: The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.

Abstract: Disclosed herein is an organic light emitting diode (OLED) lighting device capable of expressing characters or drawings with various colors. The OLED lighting device according to aspects of the present disclosure includes a thermochromic pattern arranged inside or outside of a substrate, the thermo chromic pattern having a property of changing a color thereof according to a change in temperature. By applying a reversible thermochromic pattern, which may maintain or lose an original color thereof according to a temperature change, to the inside or outside of the substrate, it is possible to express characters and drawings with various colors without designing a processing pattern inside the substrate.

Abstract: A current digital to analog converter (DAC) including an offset array including a plurality of unit cells of a first size, and a trimming array including a plurality of unit cells having the first size and a plurality of half cells, wherein the half cells have a larger size than the plurality of unit cells.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Abstract: A storage device comprising a memory, a controller, and a host interface operative to connect with a host. The memory containing data locations access to which are controllable by a protection application which is executable on a host. When the host interface operatively coupled to a host data locations in the memory are accessible to an operating system of the host only under permission from the protection application. The controller communicates with the protection application running on the host for allowing the protection application access to data locations in the memory. Upon a host request for access to a data location, the controller determines if permission to access the requested data location is acquired from the protection application. The permission is based on determination of the protection application that the data location does not contain malicious data harmful to the host operating system, to any application and/or to any data on the host.

Abstract: A content addressable memory element is provided that includes a vertical transistor including a first electrode coupled to a match line, a second electrode coupled to a ground line, a first gate electrode coupled to a search line, and a second gate electrode coupled to a complementary search line. The first gate electrode and the second gate electrode are disposed on opposite sides of the vertical transistor, and the vertical transistor includes a charge storage memory element.

Abstract: A nonvolatile memory (NVM) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a P-N diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the P-N diode are coupled to the second coupling capacitor and the word line, respectively. The first and second connection lines are coupled in parallel between the word line and the floating gate.

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Abstract: A device binding system includes generating and storing at the device a unique identifier based on device characteristics and a cryptographic function. The unique identifier is then registered with an authority. The self-generation of the unique identifier allows binding with an authority to occur after the device leaves a secure manufacturing environment or even after the device is in the hands of an end-user consumer. Once the binding occurs, the device can be part of trusted transactions for location tracking, fitness tracking, financial transactions or other interactions where identity and privacy are factors.

Abstract: A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Abstract: A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.

Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

Abstract: A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.

Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. The methods further include placing sacrificial polysilicon around the memory hole before forming the bottom stack and removing the sacrificial polysilicon from the slit trench to allow a conducting gapfill to make electrical contact to the polysilicon inside the memory hole.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and control gate electrodes located over a substrate, a drain select gate device located above the alternating stack, and a vertical semiconductor channel extending through the alternating stack and through the drain select gate device. The drain select gate device contains a floating gate electrode located between the vertical semiconductor channel and a first drain select gate electrode.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. The first member is provided on the insulating member, is positioned between the stacked bodies in the first direction, and extends in a stacking direction of the plurality of electrode films of the stacked bodies. A width in the first direction of the insulating member is larger than a width in the first direction of the first member.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

Abstract: Provided are a 3-dimensional non-volatile memory device and a method of fabricating the same. The 3-dimensional non-volatile memory device may include a substrate; semiconductor pillars, which are arranged at a certain interval in a first direction and a second direction different from the first direction; a string isolation film, which is arranged between the semiconductor pillars arranged in the first direction among the semiconductor pillars and extends in the first direction and a third direction vertical to the main surface of the substrate; first sub-electrodes repeatedly stacked on the substrate in the third direction; second sub-electrodes, which are electrically isolated from the first sub-electrodes by the string isolation film, and are repeatedly stacked on the substrate in the third direction; and information storage films including a first information storage film and a second information storage film.

Abstract: A semiconductor device includes a substrate having a first active region; first and second gate electrodes disposed on the first active region; first, second and third impurity regions disposed in the first active region; first, second and third active contacts disposed on and connected to the first, second and third impurity regions; a first power line electrically connected to the first impurity region through the first active contact; and a first bit line electrically connected to the second and third impurity regions through the second and third active contacts. The first gate electrode and the first and second impurity regions form a first transistor of a first memory cell. The second gate electrode and the second and third impurity regions form a second transistor of a second memory cell. The second impurity region is a drain of the first and second transistors of the first and second memory cells.

Abstract: A semiconductor device includes an active pillar that protrudes above a substrate, the active pillar including a pair of vertical sections and a body interconnection between the pair of vertical sections, and each of the pair of vertical sections having a channel body and a lower impurity region below the channel body, word lines coupled to respective channel bodies, and buried bit lines in contact with respective lower impurity regions, wherein the channel bodies are connected to the substrate through the body interconnection.

Abstract: A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.

Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.

Abstract: A semiconductor device includes an active region comprising a source/drain region and a plurality of poly strips spaced apart and arranged along a first direction crossing over the active region. The first direction is substantially perpendicular to a lengthwise direction of the active region. A first metal pattern is disposed on the poly strips and arranged along the first direction. A plurality of first interconnect plugs is interposed in between the poly strips and the first metal pattern and in between the active region and the first metal pattern. A position of the first interconnect plugs being variable along the first direction.

Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. S stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

Abstract: Embodiments of the present disclosure disclose a thin film transistor, a fabrication method thereof, a repair method thereof, and an array substrate. The thin film transistor comprises a gate electrode (12), a gate insulating layer (13), an active layer (14), a source electrode (16) and a drain electrode (17). The source electrode (16) comprises a first source electrode portion (161) and a second source electrode portion (162) independent from each other, the first source electrode portion (161) and the second source electrode portion (162) are electrically connected with the active layer (14), respectively; and/or, the drain electrode (17) comprises a first drain electrode portion (171) and a second drain electrode portion (172) independent from each other, the first drain electrode portion (171) and the second drain electrode portion (172) are electrically connected with the active layer (14), respectively.

Abstract: A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).

Abstract: A capacitor structure is described. A capacitor structure including a substrate and at least one device formed on the substrate. The device including first and second sections. Each of the first and second sections including a plurality of source/drain regions formed in the substrate and a plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions to form a section channel between each pair of source/drain regions. The plurality of gates of the first and second sections are coupled with each other.

Abstract: A liquid crystal display (“LCD”) device has a pixel structure which enhances a viewing angle of the LCD device through the use of a sub-pixel in which a gray scale varies during a display period and to which a photoconductive element is applied, the photoconductive element including a photoconductive layer of which a resistance level varies corresponding to an amount of light.

Abstract: A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions formed in the substrate, and a plurality of gates formed above the substrate. The plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions of the plurality of source/drain regions to form a channel between each pair of source/drain regions.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate and an anti-fuse device having a select transistor, a bitline contact, and a split channel transistor. The select transistor includes a select gate structure, a bitline source/drain region, and a shared source/drain region. The bitline contact is disposed over and in electrical communication with the bitline source/drain region. The split channel transistor is in electrical communication with the select transistor through the shared source/drain region. The split channel transistor includes an anti-fuse gate structure having an anti-fuse gate and an anti-fuse dielectric layer and a stepped gate structure disposed between the anti-fuse gate structure and the shared source/drain region and having a stepped gate and a stepped dielectric layer. The stepped dielectric layer has a greater thickness than the anti-fuse dielectric layer.

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

Abstract: A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.