Abstract: A display apparatus includes a base layer including device counterparts and bridges, the bridges being located around the device counterparts and connecting the device counterparts to each other, an inorganic insulating layer located over the base layer and having openings exposing at least a portion of at least one of the bridges, organic layers filling the openings, wires located over the organic layers, display devices located over the device counterparts, and encapsulation films each of which has a form of an island to correspond to a corresponding one of the device counterparts, each of the encapsulation films including a first inorganic encapsulation film covering a corresponding one of the display devices, an organic encapsulation film located over the first inorganic encapsulation film, and a second inorganic encapsulation film covering the organic encapsulation film and contacting the first inorganic encapsulation film outside of the organic encapsulation film.

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

Abstract: Novel and advantageous methods and systems for performing spectral computed tomography are provided. An edge-on detector, such as a silicon strip detector, can be used to receive X-rays after passing through a sample to be imaged. An energy resolving process can be performed on the collected X-ray radiation. The CT scanner can have third-generation or fourth-generation geometry.

Abstract: A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member.

Abstract: An imaging apparatus that irradiates an object with a first measuring beam and a second measuring beam that differ from each other in a center wavelength, and acquires an image of the object using returning light from the object. A first adjustment unit adjusts a focusing position of the first measuring beam in a depth direction. A second adjustment unit adjusts a focusing position of the second measuring beam in the depth direction. A controlling unit controls at least one of the first adjustment unit and the second adjustment unit such that the focusing position of the first measuring beam and the focusing position of the second measuring beam are at different positions in the depth direction.

Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.

Abstract: A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.

Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

Abstract: A method is provided for preparing a printed metal surface for the deposition of an organic semiconductor material. The method provides a substrate with a top surface, and a metal layer is formed overlying the substrate top surface. Simultaneous with a thermal treatment of the metal layer, the metal layer is exposed to a gaseous atmosphere with thiol molecules. In response to exposing the metal layer to the gaseous atmosphere with thiol molecules, the work function of the metal layer is increased. Subsequent to the thermal treatment, an organic semiconductor material is deposited overlying the metal layer. In one aspect, the metal layer is exposed to the gaseous atmosphere with thiol molecules by evaporating a liquid containing thiol molecules in an ambient air atmosphere. Alternatively, a delivery gas is passed through a liquid containing thiol molecules. An organic thin-film transistor (OTFT) and OTFT fabrication process are also provided.

Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: A curable material is provided. The curable material has the structure of formula I or formula II: wherein, X, R1, R2, m1 to m3, and n1 to n3 are defined as cited in the description.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Abstract: A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: The Examiner objected to the abstract of the disclosure because it contains the phrase “comprising.” The Abstract does not include the phrase “comprising,” however, please amend the abstract as follows: An integrated circuit having a semiconductor component arrangement and production method is disclosed. The integrated circuit as described includes an oxide layer region is provided as a protection against oxidation in the edge region on the surface region of an underlying semiconductor material region.

Abstract: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by adding an impurity of a second conductivity type, the source region and the drain region being separated from each other by a predetermined gap; an insulating film disposed on the surface of the well region in the gap between the source region and the drain region; and a gate electrode disposed on the insulating film. The well region is composed of an epitaxial layer, and the epitaxial layer includes an impurity layer of the first conductivity type having a different impurity concentration.

Abstract: The present memory device includes first and second electrodes, an active layer and a passive layer, the active and passive layers being between the first and second electrodes, with either or both of the active layer and passive layer being made up a plurality of self-assembled sublayers.

Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.

Abstract: In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At least one of the source region and the drain region has a first low concentration region and a high concentration region. Also, the semiconductor device of the present invention is provided with a second low concentration region of the second conduction type between a channel stopper region formed below the element isolation and the source region, and between the channel stopper region and the drain region. The semiconductor layer immediately below the gate electrode projects to the channel stopper region side along the gate electrode, and the semiconductor layer and the channel stopper region make contact with each other.

Abstract: An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor having a gate electrode on a semiconductor substrate with a gate insulating film interposed between the semiconductor substrate and the gate electrode, and having a source region and a drain region formed in the semiconductor substrate on both sides of the gate electrode, the insulated gate field effect transistor including: a first diffusion layer of a P type formed in the semiconductor substrate at a position deeper than the source region and the drain region; and a second diffusion layer of the P type having a higher concentration than the first diffusion layer and formed in the semiconductor substrate at a position deeper than the first diffusion layer.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 ?m.

Abstract: A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high performance, especially when operated at high voltages with full or nearly full depletion of the substrate, the device can also include a guard ring positioned near channel regions, a biased channel stop, and a biased polysilicon electrode over the channel stop.

Abstract: A method and apparatus are disclosed wherein a battery comprises an electrode having at least one nanostructured surface. The nanostructured surface is disposed in a way such that an electrolyte fluid of the battery is prevented from contacting the electrode, thus preventing discharge of the battery when the battery is not in use. When a voltage is passed over the nanostructured surface, the electrolyte fluid is caused to penetrate the nanostructured surface and to contact the electrode, thus activating the battery. In one illustrative embodiment, the battery is an integrated part of an electronics package. In another embodiment, the battery is manufactured as a separate device and is then brought into contact with the electronics package. In yet another embodiment, the electronics package and an attached battery are disposed in a projectile that is used as a military targeting device.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

Abstract: A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region 22 formed to surround the heavily p-doped layer 25 and the intermediately p-doped layer 26. The heavily p-doped layer 25 has a higher dopant concentration than the well 21. The intermediately p-doped layer 26 has a higher dopant concentration than the well 21 and a lower dopant concentration than the heavily p-doped layer 25.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.

Abstract: A semiconductor device has: a gate insulator film of a transistor formed in a predetermined region on a region of a first conductivity type; a gate electrode of the transistor formed on the gate insulator film; a diffusion layer of a second conductivity type formed on both sides of the gate insulator film on the region of the first conductivity type; and a diffusion layer of the first conductivity type formed on the region of the first conductivity type so as to surround the gate insulator film and the diffusion layer of the second conductivity type. The diffusion layer of the first conductivity type has a higher impurity concentration than the region of the first conductivity type. In such a semiconductor device, the diffusion layer of the first conductivity type is formed so as to be separated from the gate insulator film.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

Abstract: A semiconductor device structure is described for reducing radiation induced current flow caused by incident ionizing radiation. The structure comprises a semiconductor substrate; two or more regions of a first conductivity type in the substrate; and a guard ring of a second conductivity type for obstructing radiation induced parasitic current flow between the two or more regions of the first conductivity type. The structure may be used in a pixel, e.g. in a diode or a transistor, for increasing radiation resistance.

Abstract: Multiple coupled inductors are formed in a well in a semiconductor device. The inductors, which preferably are spiral inductors, are strongly coupled with high quality factors. The coupled inductors may be used as efficient signal splitting and combining circuits.

Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

Abstract: A substrate support rim used in the fabrication of devices such as organic light emissive diodes (OLEDs) is disclosed. The support rim, which is located at the edge of a substrate, serves to reinforce the substrate, facilitating handling during and after the fabrication process to reduce damage to the device. The support rim comprises, for example, epoxy, adhesives or other materials that adhere to the substrate.

Abstract: Wafer buffering systems for use with a wafer processing system include a frame and wheel. The wheel includes a plurality of shelves for supporting a plurality of wafer carriers. The wheel is supported by the frame for rotation about a generally horizontal axis. The plane of the wheel faces a semiconductor processing system (e.g., a cluster tool) with an intervening wafer transfer robot located preferably between the wheel and the semiconductor processing system. A cassette transfer system moves cassettes from the wheel to a port for interfacing with the wafer transfer robot. In another arrangement, a horizontal carousel stocks cassettes above the processing system.

Abstract: An edge of a passivation film is positioned inside an edge of an overhanging emitter structure by a distance L so that a base electrode layer is formed at an interval not to overlap the edge of the passivation film even when the base electrode layer is formed by etching with the emitter structure as a mask.

Abstract: An isolation region is embedded in a semiconductor substrate. The height of the upper face of the isolation region is substantially equal to the height of the surface of the semiconductor substrate. A gate electrode is formed on a gate insulating film and over the isolation region. A first side face of the gate electrode is formed over the isolation region. A second side face of the gate electrode is formed over the active region. A field insulator is formed on the isolation region. A first side face of the field insulator contacts with the first side face of the gate electrode. A second side face of the field insulator is continuous with a plane obtained by extending the side face of the isolation region. A sidewall insulator has a sidewall contacting with the second side face of the field insulator and the second side face of the gate electrode.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.