Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.

Abstract: A charge or carrier injection transistor including a substrate, a gate electrode and an electric potential barrier layer forming an electric potential barrier against charges (either holes or electrons) injected by the gate electrode towards the substrate. A source and a drain are formed in the substrate on opposite sides of the gate electrode. A conduction channel, between the source and the drain, is formed on the substrate by charges passing through the electric potential barrier by a voltage applied to the gate electrode. When the applied voltage is removed, this channel disappears. That is, the transistor is ON when the charges from the gate electrode pass through the electric potential barrier and is OFF when no charges pass through it, thereby the charges perform a transistor switching function.

Abstract: A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

Abstract: A semiconductor element including a silicon substrate, a silicon oxide film formed on the silicon substrate, and a top electrode formed on the silicon oxide film, wherein chromium is included only in a region of the silicon oxide film, the region including the interface between the silicon oxide film and the top electrode and the vicinity of the interface, and the method of manufacturing the same.

Abstract: An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.

Abstract: A structure of a semiconductor device according to the present invention has a normally-off characteristic, a well controlability, a very low on-resistance, a capability for a high breakdown voltage, and is free from parasitic devices. For example, said semiconductor device has a plurality of bar-shaped trenches dug on the surface of an n type semiconductor substrate, which are arranged in stripe, and each of which cross sectional shape is a "U"-shape. At least one n.sup.+ type source region on the surface and it is sandwiched by the trenches. In the respective trenches, insulated electrodes whose potential is fixed to that of the source region, and whose conductive material is made of such that has a work function to generate a depletion region in the drain region around them are disposed. The depletion region functions as a barrier to interrupt between the source region and the drain region electrically.

Abstract: Electrical quality insulating films on n-type and p-type diamond substrates are provided in which an insulating film such as a silicon dioxide film is deposited onto the exposed face of a diamond substrate, such as by chemical vapor deposition. Forming a conducting layer atop the silicon dioxide allows the creation of a metal-oxide-silicon device with which semiconductor carriers can be controlled through the application of a bias voltage to the conductor surface.

Abstract: There is disclosed a semiconductor device having a vertical channel MOS gate structure wherein grooves (40) are formed from the top surface of source regions (5) through a body (3) into an N diffusion region (2) and wherein buried gate electrodes (4) fill an inner part of said grooves (40) which is in face-to-face relation to the N diffusion region (2) across gate oxide films (13) while buried oxide films (15) including diffusion source impurities fill an inner part thereof which is in face-to-face relation to the source regions (5). The impurity concentration of the source regions (5) is distributed uniformly in the vertical direction of the grooves (40) and decreases lateraly away from the grooves (40). A current flows through the source region along the grooves and a resistance thereagainst is held small in an ON-state. The grooves may be formed with narrow spacing. The size reduction and high integration of the semiconductor device are achieved as well as reduction in ON-resistance.

Abstract: A field-effect transistor comprising a semiconductor substrate having source and drain regions and a gate electrode, wherein a thin organic film including donor and acceptor molecules is provided between the semiconductor substrate and the gate electrode. When a predetermined voltage is applied to the gate electrode, charge transfer occurs between the donor and acceptor molecules included in the thin organic film, thereby controlling the surface potential of the semiconductor substrate.

Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.

Abstract: An artificial neural synapse (10) is constructed to function as a modifiable excitatory synapse. In accordance with an embodiment of the invention the synapse is fabricated as a silicon MOSFET that is modified to have ions within a gate oxide. The ions, such as lithium, sodium, potassium or fluoride ions, are selected for their ability to drift within the gate oxide under the influence of an applied electric field. In response to a positive voltage applied to a gate terminal of the device, positively charged ions, such as sodium or potassium ions, drift to a silicon/silicon dioxide interface, causing an increase in current flow through the device. The invention also pertains to assemblages of such devices that are interconnected to form an artificial neuron and to assemblages of such artificial neurons that form an artificial neural network.