Plural Gate Insulator Layers Patents (Class 257/406)
  • Patent number: 10199277
    Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: September 18, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Kuo Chiang, Chun-Hsien Lin
  • Patent number: 10008436
    Abstract: A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Aki Dote, Takeshi Ishitsuka, Hideki Kitada
  • Patent number: 9954021
    Abstract: Realization of an adequate hole accumulation layer and reduction in dark current are allowed to become mutually compatible. A solid-state imaging device 1 having a light-receiving portion 12 to photoelectrically convert incident light is characterized by including a film 21, which is disposed on a light-receiving surface 12s of the above-described light-receiving portion 12 and which lowers an interface state, and a film 22, which is disposed on the above-described film 21 to lower the interface state and which has a negative fixed charge, wherein a hole accumulation layer 23 is disposed on the light-receiving surface 12s side of the light-receiving portion 12.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 24, 2018
    Assignee: Sony Corporation
    Inventors: Tetsuji Yamaguchi, Yuko Ohgishi, Takashi Ando, Harumi Ikeda
  • Patent number: 9871121
    Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan, Da Yang, Choh Fei Yeap
  • Patent number: 9780211
    Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
  • Patent number: 9711616
    Abstract: A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 18, 2017
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Eric J. Stewart, Bettina A. Nechay, Karen M. Renaldo, Howell G. Henry, Ronald G. Freitag
  • Patent number: 9281395
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 8, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Min Gyu Lim, Jung Hwan Lee, Yi Sun Chung
  • Patent number: 9281370
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 8, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9245806
    Abstract: A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region, introducing arsenic to the gate stack layer in the NMOS region, introducing aluminum to the gate stack layer in the PMOS region, and etching the gate stack layers, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventor: Dong-Kyun Kang
  • Patent number: 9130026
    Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9018686
    Abstract: A device comprises: a first plurality of fins on a semiconductor substrate, the first plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a second plurality of fins on the semiconductor substrate, the second plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a chemox layer deposited on lower portions of the fins of the first plurality of fins; and a dielectric layer deposited on the fins of the second plurality of fins. The dielectric layer is thicker than the chemox layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita
  • Patent number: 9006837
    Abstract: A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
  • Patent number: 8963211
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8952458
    Abstract: A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yang Lee, Xiong-Fei Yu, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8941190
    Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8901674
    Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Dechao Guo, Unoh Kwon, Christopher Carr Parks, Yun-Yu Wang
  • Patent number: 8872285
    Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Carsten Grass, Richard Carter, Martin Trentzsch
  • Patent number: 8816447
    Abstract: Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 8809971
    Abstract: A semiconductor component comprising a semiconductor body, a channel zone in the semiconductor body, a channel control electrode adjacent to the channel zone, and a dielectric layer between the channel zone and the channel control electrode, wherein the dielectric layer has a relative dielectric constant ?r with a negative temperature coefficient.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: August 19, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Frank Pfirsch
  • Patent number: 8766377
    Abstract: A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8698249
    Abstract: A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Mise, Takahisa Eimori
  • Patent number: 8674429
    Abstract: A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Jung-Dal Choi, Kwang-Soo Seol
  • Patent number: 8674419
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Patent number: 8664711
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
  • Patent number: 8659071
    Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Zhi Tian
  • Patent number: 8633546
    Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
  • Patent number: 8629022
    Abstract: A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Sunfei Fang, Yue Liang, Xiaojun Yu, Jun Yuan
  • Patent number: 8618603
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Patent number: 8609490
    Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 17, 2013
    Assignee: Micrel, Inc.
    Inventor: David R. Zinn
  • Patent number: 8610214
    Abstract: Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Sukehiro Yamamoto
  • Patent number: 8558304
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: October 15, 2013
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 8530286
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
  • Patent number: 8524554
    Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 3, 2013
    Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
  • Patent number: 8507894
    Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 13, 2013
    Assignee: Qucor Pty Limited
    Inventors: Andrea Morello, Andrew Dzurak, Hans-Gregor Huebl, Robert Graham Clark, Laurens Henry Willems Van Beveren, Lloyd Christopher Leonard Hollenberg, David Normal Jamieson, Christopher Escott
  • Patent number: 8368149
    Abstract: The present disclosure provides various embodiments of a semiconductor device and method of fabricating the semiconductor device. An exemplary semiconductor device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate and a tuned, stressed metal gate layer disposed over the gate dielectric layer. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the semiconductor substrate having different surface characteristics. In an example, the gate stack is disposed over a portion of a fin of the semiconductor substrate, and the fin has a varying thickness, providing a fin with a roughened surface. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the fin having different thicknesses.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Robert James Pascoe Lander
  • Patent number: 8350341
    Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, William K. Henson, Unoh Kwon
  • Patent number: 8350338
    Abstract: A semiconductor device is disclosed. In an embodiment, a semiconductor device includes a N-well within a P-well in a silicon layer, the silicon layer positioned atop a buried oxide layer of a silicon-on-insulator (SOI) substrate; a first source region and a second source region within a portion of the P-well; a first drain region and a second drain region within a portion of the P-well and within a portion of the N-well; and a gate positioned atop the N-well, wherein a lateral high field region is generated between the N-well and the P-well and a vertical high field region is generated between the gate and the N-well. A related method is disclosed.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporations
    Inventors: William F. Clark, Jr., Yun Shi
  • Patent number: 8319316
    Abstract: A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Kenji Gomikawa, Yoshiko Kato, Mitsuhiro Noguchi, Masato Endo
  • Patent number: 8278168
    Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
  • Patent number: 8217440
    Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaihsa Toshiba
    Inventor: Yoshinori Tsuchiya
  • Patent number: 8207584
    Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 26, 2012
    Assignees: Renesas Electronics Corporation, Rohm Co., Ltd.
    Inventors: Toshihide Nabatame, Kunihiko Iwamoto, Yuuichi Kamimuta
  • Patent number: 8203188
    Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: June 19, 2012
    Assignee: Broadcom Corporation
    Inventor: Akiro Ito
  • Patent number: 8188547
    Abstract: A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Manabe, Toshihiro Iizuka, Daisuke Ikeno
  • Patent number: 8125019
    Abstract: An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped charge region.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Benjamin T. Voegeli, Kimball M. Watson
  • Patent number: 8114739
    Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8072024
    Abstract: A nonvolatile semiconductor memory device with a substrate. A plurality of dielectric films and electrode films are alternately stacked on the substrate and have a through hole penetrating in the stacking direction. A semiconductor pillar is formed inside the through hole. A charge storage layer is provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Ishikawa, Katsunori Yahashi
  • Patent number: 8044469
    Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
  • Patent number: 8044471
    Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: October 25, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Min Cao
  • Patent number: 8044452
    Abstract: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric constant insulating film are formed sequentially in this order on one surface of a silicon substrate.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: October 25, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Tominaga Koji, Iwamoto Kunihiko, Yasuda Tetsuji, Nabatame Toshihide
  • Patent number: 8030717
    Abstract: A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 4, 2011
    Assignees: Tokyo Electron Limited, National Institute of Advanced Industrial Science and Technology
    Inventors: Koji Akiyama, Wenwu Wang