With Gate Electrode Of Controlled Workfunction Material (e.g., Low Workfunction Gate Material) Patents (Class 257/407)
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Patent number: 7382021Abstract: A transistor includes one or more channel taps containing a stack consisting at least in part of a semiconductor an interfacial III-VI layered compound and a conductor. The III-VI compound consists primarily of atoms from Groups IIIA-B and from Group VIA of the Periodic Table of the Elements in an approximate 1:1 ratio. These materials may be formed as layers of covalently bonded elements from Groups IIIA-B and covalently bonded Group VIA elements, adjacent and respective planes of which may be bonded by Van der Waals forces (e.g., to form a single bilayer consisting of a single plane of atoms from Groups IIIA-B and a single plane of Group VIA atoms). One particular III-VI material from which the interfacial layer is made, especially for p-channel transistors, is GaSe. Other III-VI compounds, whether pure compounds or alloys of pure compounds, may also be used.Type: GrantFiled: December 9, 2004Date of Patent: June 3, 2008Assignee: Acorn Technologies, Inc.Inventors: Carl Faulkner, Daniel J. Connelly, Daniel E. Grupp
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Patent number: 7381999Abstract: A memory device having a thyristor-based storage element and an access device coupled to the thyristor-based storage element at a common storage node is described. The thyristor-based storage element has a first gate stack, where the first gate stack has a first workfunction configured to a base region of the thyristor-based storage element. The access device has a second gate stack, where the second gate stack has a second workfunction. The first gate stack includes a first conductive layer formed over a gate dielectric and a second conductive layer formed over the first conductive layer. The second gate stack includes the second conductive layer formed over the gate dielectric. The first workfunction is operationally distinct from the second workfunction.Type: GrantFiled: July 21, 2005Date of Patent: June 3, 2008Assignee: T-Ram Semiconductor, Inc.Inventor: Kevin J. Yang
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Publication number: 20080122016Abstract: A semiconductor device includes: a semiconductor substrate including source/drain regions and a channel between the source/drain regions; a gate oxide layer pattern on the channel; a metal nitride layer pattern on the gate oxide layer pattern; a silicide on the metal nitride layer pattern; and a spacer on a side of the gate oxide layer pattern, the metal nitride layer pattern, and the silicide. In one embodiment, the metal nitride layer pattern is ¼ to ½ as thick as the silicide.Type: ApplicationFiled: October 30, 2007Publication date: May 29, 2008Inventor: Yong ho Oh
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Patent number: 7365015Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.Type: GrantFiled: July 13, 2004Date of Patent: April 29, 2008Assignee: LSI Logic CorporationInventors: Hong Lin, Wai Lo, Sey-Shing Sun, Richard Carter
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Patent number: 7355249Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.Type: GrantFiled: April 28, 2005Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: William F. Clark, Jr., Edward J. Nowak
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Publication number: 20080073723Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Inventors: Willy Rachmady, Uday Shah, Jack T. Kavalieros, Brian S. Doyle
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Patent number: 7335958Abstract: Embodiments of the invention provide a method of forming a pixel cell and the resultant pixel cell a photo-conversion device formed at a surface of a substrate and a transistor adjacent to the photo-conversion device. The transistor comprises a gate overlying a channel region. The gate comprises at least one gate region having a work-function greater than a work-function of n+ polysilicon. The channel region comprises respective portions below each gate region. A dopant concentration in at least one portion of the channel region is determined at least in part by the work-function of the respective gate region.Type: GrantFiled: June 25, 2003Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 7324367Abstract: A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.Type: GrantFiled: November 10, 2005Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventor: Kris K. Brown
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Patent number: 7320931Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.Type: GrantFiled: July 30, 2004Date of Patent: January 22, 2008Assignee: Freescale Semiconductor Inc.Inventors: Shawn G. Thomas, Vida Ilderem, Papu D. Maniar
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Patent number: 7321154Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).Type: GrantFiled: August 17, 2006Date of Patent: January 22, 2008Assignee: Texas Instruments IncorporatedInventors: Luigi Colombo, James J Chambers, Mark R Visokay
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Patent number: 7304353Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.Type: GrantFiled: June 7, 2005Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventors: Mark Helm, Xianfeng Zhou
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Patent number: 7285829Abstract: A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.Type: GrantFiled: March 31, 2004Date of Patent: October 23, 2007Assignee: Intel CorporationInventors: Brian Doyle, Scott A. Hareland, Mark Doczy, Robert S. Chau
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Patent number: 7285833Abstract: A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically active dopant therein. A second of the gate electrodes is formed of the first gate electrode material having less than the first concentration of the electrically active dopant therein, and formed at least partially as an alloy with a second gate electrode material. The semiconductor product may be formed with enhanced efficiency.Type: GrantFiled: January 25, 2005Date of Patent: October 23, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen Ping Wang, Chih Hao Wang
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Publication number: 20070215956Abstract: It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor substrate so as to separate each other, each including: a silicide layer containing a first metal element as a main component having a vacuum work function of 4.6 eV or greater; and a layer containing at least one second metal element selected from the group of scandium elements and lanthanoid, the layer containing the second metal element including a segregating layer in which the highest areal density is 1×1014 cm?2 or higher, each region of the segregating layer with areal density of 1×1014 cm?2 or higher having a thickness smaller than 1 nm; a gate insulating film provided a region between the source and drain regions on the semiconductor substrate; and a gate electrode provided on the gate insulating film.Type: ApplicationFiled: February 23, 2007Publication date: September 20, 2007Inventors: Yoshinori Tsuchiya, Masato Koyama
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Patent number: 7271457Abstract: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly reduces the diffusion motion of other impurity dopants, such as As, P, In, and B in the regions of silicon where Ge resides in significant quantities (i.e. greater than 1E19 cm sup3).Type: GrantFiled: March 4, 2005Date of Patent: September 18, 2007Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Robert M. Quinn
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Patent number: 7268387Abstract: The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very narrow. A channel region of a memory transistor is divided into two regions of a writing control region and a writing region. The writing control region and the writing region have different threshold voltages. Writing is only carried out in the writing region. The writing control region turns off when the amount of electric charges accumulated in a floating gate reaches a specific value due to writing. The writing control region is used as a switch for a writing operation to automatically stop writing. Accordingly, an involatile memory comprising a memory transistor, in which writing can be carried out at a high speed with low consumption power and which is superior in controlling a threshold voltage after writing or erasing, can be obtained.Type: GrantFiled: August 19, 2003Date of Patent: September 11, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Kiyoshi Kato
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Patent number: 7256458Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.Type: GrantFiled: October 28, 2004Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventor: Edward J. Nowak
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Patent number: 7253485Abstract: A manufacturing method for a CMOS semiconductor device in which gate electrodes are adjusted to have different work function values comprises forming an device region of a first and second conductivity type for forming first and second MOS semiconductor element devices, respectively, in a semiconductor substrate, forming a gate insulator, forming a laminated film comprising a molybdenum film and nitrogen containing film for doping nitrogen into molybdenum, doping nitrogen from the nitrogen containing film into molybdenum, processing the laminated film into gate electrodes of the first and second MOS semiconductor element devices, removing the nitrogen containing film from the gate electrodes of the second MOS semiconductor element device and covering the gate electrode of the first MOS semiconductor element devices with a nitrogen diffusion preventing film, and reducing the nitrogen concentration in molybdenum of the gate electrodes of the second MOS semiconductor element device.Type: GrantFiled: August 25, 2004Date of Patent: August 7, 2007Assignee: Semiconductor Technology Academic Research CenterInventor: Kentaro Shibahara
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Patent number: 7242049Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: June 11, 2003Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7235847Abstract: A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.Type: GrantFiled: September 17, 2004Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Sinan Goktepeli, Alexander A. Demkov, Marius K. Orlowski
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Patent number: 7235837Abstract: Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for gates or capacitor plates.Type: GrantFiled: November 4, 2005Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Salman Akram
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Patent number: 7202539Abstract: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.Type: GrantFiled: May 19, 2005Date of Patent: April 10, 2007Assignee: Renesas Technology CorporationInventors: Toshihide Nabatame, Masaru Kadoshima
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Patent number: 7187044Abstract: A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.Type: GrantFiled: March 2, 2000Date of Patent: March 6, 2007Assignee: Intel CorporationInventors: Chunlin Liang, Gang Bai
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Patent number: 7179702Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.Type: GrantFiled: September 23, 2005Date of Patent: February 20, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Kouji Matsuo
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Patent number: 7176537Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 ? on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 ?.Type: GrantFiled: May 23, 2005Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ke, Min-Hwa Chi
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Patent number: 7176513Abstract: A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.Type: GrantFiled: November 9, 2004Date of Patent: February 13, 2007Assignee: Micron Technology, Inc.Inventor: Kris K. Brown
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Patent number: 7157751Abstract: The present invention realizes a display device having C-MOS p-Si TFTs which enable the high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in driving circuit or the like thereof. The present invention adopts a self-aligned C-MOS process which uses a half tone mask as an exposure mask for manufacturing the C-MOS p-Si TFTs mounted on the display device. With the use of the half tone mask, the alignment or positioning at a bonding portion between a P-MOS portion and an N-MOS portion becomes unnecessary and hence, the number of photolithography steps can be reduced and the high integration of C-MOS TFT circuits can be realized.Type: GrantFiled: March 21, 2003Date of Patent: January 2, 2007Assignee: Hitachi Displays, Ltd.Inventors: Daisuke Sonoda, Toshiki Kaneko
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Patent number: 7154153Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: July 29, 1997Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7151303Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.Type: GrantFiled: January 6, 2004Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, John K. Zahurak
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Patent number: 7148548Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.Type: GrantFiled: July 20, 2004Date of Patent: December 12, 2006Assignee: Intel CorporationInventors: Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Justin K. Brask, Suman Datta, Robert S. Chau
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Patent number: 7145208Abstract: A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.Type: GrantFiled: June 25, 2004Date of Patent: December 5, 2006Assignee: United Microelectronics Corp.Inventors: Chih-Wei Yang, Yi-Sheng Hsieh, Wei-Min Lin, Wen-Tai Chiang, Wei-Tsun Shiau
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Patent number: 7141858Abstract: A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.Type: GrantFiled: June 18, 2004Date of Patent: November 28, 2006Assignee: The Regents of the University of CaliforniaInventors: Igor Polishchuk, Pushkar Ranade, Tsu-Jae King, Chenming Hu
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Patent number: 7135742Abstract: An insulated gate type semiconductor device comprised of a semiconductor layer serving as an active region isolated from a semiconductor substrate by a substrate isolation insulating film and a T-shaped gate electrode comprised of a trunk-shaped main gate electrode and a crosspiece-shaped conductor pattern provided on the semiconductor layer, wherein the thickness of the gate insulating film directly under the crosspiece-shaped conductor pattern is made greater than the thickness of the gate insulating film directly under the main gate electrode, whereby it is possible to prevent short-circuits between electrodes, prevent short-circuits between separators, and prevent an increase of the parasitic capacitance.Type: GrantFiled: November 22, 2000Date of Patent: November 14, 2006Assignee: Fujitsu LimitedInventors: Akihiko Harada, Sadanori Akiya, Kazuhiro Furuya, Hisashi Watanabe
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Patent number: 7132718Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: GrantFiled: December 4, 2003Date of Patent: November 7, 2006Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
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Patent number: 7129544Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.Type: GrantFiled: October 6, 2004Date of Patent: October 31, 2006Assignee: Semiconductor Components Industries, L.L.C.Inventor: Peyman Hadizad
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Patent number: 7125762Abstract: A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.Type: GrantFiled: July 28, 2004Date of Patent: October 24, 2006Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
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Patent number: 7122414Abstract: The present invention relates generally to barrier layers in transistor gate stacks in integrated circuits, and to processes for forming such gate stacks.Type: GrantFiled: June 19, 2003Date of Patent: October 17, 2006Assignee: ASM International, Inc.Inventor: Hannu Huotari
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Patent number: 7122870Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.Type: GrantFiled: August 9, 2004Date of Patent: October 17, 2006Assignee: Intel CorporationInventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob M. Jensen
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Patent number: 7122472Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.Type: GrantFiled: December 2, 2004Date of Patent: October 17, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, Christian Lavoie, Clement H. Wann
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Patent number: 7119402Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.Type: GrantFiled: September 3, 2004Date of Patent: October 10, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Kinoshita, Junji Koga
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Patent number: 7109550Abstract: A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.Type: GrantFiled: January 13, 2005Date of Patent: September 19, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Ramachandran Muralidhar
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Patent number: 7109548Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: February 27, 2004Date of Patent: September 19, 2006Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7102203Abstract: A semiconductor device capable of inhibiting a threshold voltage from increase also when employing a gate electrode consisting of a metal is provided. This semiconductor device comprises a pair of source/drain regions lifted up in an elevated structure, a gate insulator film, formed on a channel region, consisting of a high dielectric constant insulator film having a dielectric constant larger than 3.9 and a gate electrode including a first metal layer coming into contact with the gate insulator film and having a work function controlled to have a Fermi level around the energy level of a band gap end of silicon constituting the source/drain regions.Type: GrantFiled: March 23, 2004Date of Patent: September 5, 2006Assignees: Sanyo Electric Co., Ltd., National Institute of Advanced Industrial Science and TechnologyInventors: Hideaki Fujiwara, Akira Toriumi
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Patent number: 7091569Abstract: Provided are a novel gate, a CMOS structure, and a MOS structure each of that has low resistance and excellent controllability. The gate is comprised of an intermetallic compound semiconductor that has an electric conductivity in a range of no less than 102 S·m?1, nor more than 105 S·m?1 without impurities and has a band structure like that of a semiconductor.Type: GrantFiled: March 1, 2002Date of Patent: August 15, 2006Assignee: National Institute for Materials ScienceInventors: Toyohiro Chikyo, Motoharu Imai
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Patent number: 7060568Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.Type: GrantFiled: June 30, 2004Date of Patent: June 13, 2006Assignee: Intel CorporationInventors: Matthew V. Metz, Suman Datta, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Robert S. Chau
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Patent number: 7057243Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.Type: GrantFiled: August 27, 2003Date of Patent: June 6, 2006Assignees: Elpida Memory, Inc., Hitachi, Ltd.Inventors: Satoru Yamada, Ryo Nagai, Kiyonori Oyu, Ryoichi Nakamura, Norikatsu Takaura
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Patent number: 7045406Abstract: A method forms a gate stack for a semiconductor device with a desired work function of the gate electrode. The work function is adjusted by changing the overall electronegativity of the gate electrode material in the region that determines the work function of the gate electrode during the gate electrode deposition. The gate stack is deposited by an atomic layer deposition type process and the overall electronegativity of the gate electrode is tuned by introducing at least one pulse of an additional precursor to selected deposition cycles of the gate electrode. The tuning of the work function of the gate electrode can be done not only by introducing additional material into the gate electrode, but also by utilizing the effects of a graded mode deposition and thickness variations of the lower gate part of the gate electrode in combination with the effects that the incorporation of the additional material pulses offers.Type: GrantFiled: May 5, 2003Date of Patent: May 16, 2006Assignee: ASM International, N.V.Inventors: Hannu Huotari, Suvi Haukka, Marko Tuominen
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Patent number: 7045844Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.Type: GrantFiled: October 13, 2004Date of Patent: May 16, 2006Assignee: Micron Technology, Inc.Inventor: Kris K. Brown
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Patent number: 7030430Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.Type: GrantFiled: August 15, 2003Date of Patent: April 18, 2006Assignee: Intel CorporationInventors: Mark Doczy, Nathan Baxter, Robert S. Chau, Kari Harkonen, Teemu Lang
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Patent number: 7023064Abstract: An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.Type: GrantFiled: June 16, 2004Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Cyril Cabral, Jr., Oleg Gluschenkov, Hyungjun Kim